[ConstraintElim] Support arbitrary incoming values for inductions (#68032)
Support arbitray incoming values for AddRecs by getting the loop predecessor and checking if its SCEV matches the AddRec start. This is done after the existing check, which can help to catch cases where the expression gets simplified by SCEV to either an IR constant or existing value which can be used instead.
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@@ -859,18 +859,18 @@ void State::addInfoForInductions(BasicBlock &BB) {
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return;
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auto *AR = dyn_cast_or_null<SCEVAddRecExpr>(SE.getSCEV(PN));
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if (!AR)
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BasicBlock *LoopPred = L->getLoopPredecessor();
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if (!AR || !LoopPred)
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return;
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const SCEV *StartSCEV = AR->getStart();
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Value *StartValue = nullptr;
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if (auto *C = dyn_cast<SCEVConstant>(StartSCEV))
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if (auto *C = dyn_cast<SCEVConstant>(StartSCEV)) {
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StartValue = C->getValue();
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else if (auto *U = dyn_cast<SCEVUnknown>(StartSCEV))
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StartValue = U->getValue();
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if (!StartValue)
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return;
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} else {
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StartValue = PN->getIncomingValueForBlock(LoopPred);
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assert(SE.getSCEV(StartValue) == StartSCEV && "inconsistent start value");
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}
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DomTreeNode *DTN = DT.getNode(InLoopSucc);
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auto Inc = SE.getMonotonicPredicateType(AR, CmpInst::ICMP_UGT);
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@@ -17,8 +17,7 @@ define void @start_value_of_inner_add_rec_is_add_rec_condition_can_be_simplified
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; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp eq i32 [[K_0]], [[LEN]]
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; CHECK-NEXT: br i1 [[CMP2_NOT]], label [[OUTER_LATCH]], label [[INNER_LATCH]]
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; CHECK: inner.latch:
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; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i32 [[K_0]], [[LEN]]
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; CHECK-NEXT: call void @use(i1 [[CMP_NOT_I]])
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; CHECK-NEXT: call void @use(i1 true)
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; CHECK-NEXT: [[K_INC]] = add i32 [[K_0]], 1
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; CHECK-NEXT: br label [[INNER_HEADER]]
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; CHECK: outer.latch:
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