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[RISCV] Accept '0(reg)' in addition to '(reg)' for vle1.v/vse1.v

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This commit is contained in:
Craig Topper
2025-03-17 20:48:02 -07:00
parent b9d27ac252
commit 0813c5cf5f
2 changed files with 10 additions and 4 deletions
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8
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
View File

@@ -1111,10 +1111,10 @@ def VLM_V : VUnitStrideLoadMask<"vlm.v">,
Sched<[WriteVLDM_WorstCase, ReadVLDX]>;
def VSM_V : VUnitStrideStoreMask<"vsm.v">,
Sched<[WriteVSTM_WorstCase, ReadVSTM_WorstCase, ReadVSTX]>;
def : InstAlias<"vle1.v $vd, (${rs1})",
(VLM_V VR:$vd, GPR:$rs1), 0>;
def : InstAlias<"vse1.v $vs3, (${rs1})",
(VSM_V VR:$vs3, GPR:$rs1), 0>;
def : InstAlias<"vle1.v $vd,$rs1",
(VLM_V VR:$vd, GPRMemZeroOffset:$rs1), 0>;
def : InstAlias<"vse1.v $vs3, $rs1",
(VSM_V VR:$vs3, GPRMemZeroOffset:$rs1), 0>;
def VS1R_V : VWholeStore<0, "vs1r.v", VR>,
Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>;

6
llvm/test/MC/RISCV/rvv/aliases.s
View File

@@ -93,9 +93,15 @@ vfabs.v v2, v1, v0.t
# ALIAS: vlm.v v8, (a0) # encoding: [0x07,0x04,0xb5,0x02]
# NO-ALIAS: vlm.v v8, (a0) # encoding: [0x07,0x04,0xb5,0x02]
vle1.v v8, (a0)
# ALIAS: vlm.v v8, (a0) # encoding: [0x07,0x04,0xb5,0x02]
# NO-ALIAS: vlm.v v8, (a0) # encoding: [0x07,0x04,0xb5,0x02]
vle1.v v8, 0(a0)
# ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02]
# NO-ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02]
vse1.v v8, (a0)
# ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02]
# NO-ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02]
vse1.v v8, 0(a0)
# ALIAS: vfredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0x04]
# NO-ALIAS: vfredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0x04]
vfredsum.vs v8, v4, v20, v0.t