[lldb][MachO] MachO corefile support for riscv32 binaries (#137092)
Add support for reading a macho corefile with CPU_TYPE_RISCV and the riscv32 general purpose register file. I added code for the floating point and exception registers too, but haven't exercised this. If we start putting the full CSR register bank in a riscv corefile, it'll be in separate 4k byte chunks, but I don't have a corefile to test against that so I haven't written the code to read it. The RegisterContextDarwin_riscv32 is copied & in the style of the other RegisterContextDarwin classes; it's not the first choice I would make for representing this, but it wasn't worth changing for this cputype. rdar://145014653
This commit is contained in:
Jason Molenda
@@ -12,6 +12,7 @@
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#include "Plugins/Process/Utility/RegisterContextDarwin_arm.h"
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#include "Plugins/Process/Utility/RegisterContextDarwin_arm64.h"
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#include "Plugins/Process/Utility/RegisterContextDarwin_i386.h"
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#include "Plugins/Process/Utility/RegisterContextDarwin_riscv32.h"
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#include "Plugins/Process/Utility/RegisterContextDarwin_x86_64.h"
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#include "lldb/Core/Debugger.h"
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#include "lldb/Core/Module.h"
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@@ -769,6 +770,147 @@ protected:
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}
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};
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class RegisterContextDarwin_riscv32_Mach
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: public RegisterContextDarwin_riscv32 {
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public:
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RegisterContextDarwin_riscv32_Mach(lldb_private::Thread &thread,
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const DataExtractor &data)
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: RegisterContextDarwin_riscv32(thread, 0) {
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SetRegisterDataFrom_LC_THREAD(data);
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}
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void InvalidateAllRegisters() override {
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// Do nothing... registers are always valid...
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}
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void SetRegisterDataFrom_LC_THREAD(const DataExtractor &data) {
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lldb::offset_t offset = 0;
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SetError(GPRRegSet, Read, -1);
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SetError(FPURegSet, Read, -1);
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SetError(EXCRegSet, Read, -1);
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SetError(CSRRegSet, Read, -1);
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bool done = false;
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while (!done) {
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int flavor = data.GetU32(&offset);
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uint32_t count = data.GetU32(&offset);
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lldb::offset_t next_thread_state = offset + (count * 4);
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switch (flavor) {
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case GPRRegSet:
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// x0-x31 + pc
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if (count >= 32) {
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for (uint32_t i = 0; i < 32; ++i)
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((uint32_t *)&gpr.x0)[i] = data.GetU32(&offset);
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gpr.pc = data.GetU32(&offset);
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SetError(GPRRegSet, Read, 0);
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}
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offset = next_thread_state;
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break;
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case FPURegSet: {
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// f0-f31 + fcsr
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if (count >= 32) {
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for (uint32_t i = 0; i < 32; ++i)
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((uint32_t *)&fpr.f0)[i] = data.GetU32(&offset);
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fpr.fcsr = data.GetU32(&offset);
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SetError(FPURegSet, Read, 0);
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}
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}
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offset = next_thread_state;
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break;
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case EXCRegSet:
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if (count == 3) {
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exc.exception = data.GetU32(&offset);
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exc.fsr = data.GetU32(&offset);
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exc.far = data.GetU32(&offset);
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SetError(EXCRegSet, Read, 0);
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}
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offset = next_thread_state;
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break;
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default:
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done = true;
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break;
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}
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}
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}
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static bool Create_LC_THREAD(Thread *thread, Stream &data) {
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RegisterContextSP reg_ctx_sp(thread->GetRegisterContext());
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if (reg_ctx_sp) {
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RegisterContext *reg_ctx = reg_ctx_sp.get();
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data.PutHex32(GPRRegSet); // Flavor
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data.PutHex32(GPRWordCount);
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PrintRegisterValue(reg_ctx, "x0", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x1", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x2", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x3", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x4", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x5", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x6", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x7", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x8", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x9", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x10", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x11", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x12", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x13", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x14", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x15", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x16", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x17", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x18", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x19", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x20", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x21", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x22", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x23", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x24", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x25", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x26", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x27", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x28", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x29", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x30", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "x31", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "pc", nullptr, 4, data);
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data.PutHex32(0); // uint32_t pad at the end
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// Write out the EXC registers
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data.PutHex32(EXCRegSet);
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data.PutHex32(EXCWordCount);
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PrintRegisterValue(reg_ctx, "exception", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "fsr", nullptr, 4, data);
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PrintRegisterValue(reg_ctx, "far", nullptr, 4, data);
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return true;
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}
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return false;
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}
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protected:
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int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr) override { return -1; }
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int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) override { return -1; }
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int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc) override { return -1; }
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int DoReadCSR(lldb::tid_t tid, int flavor, CSR &csr) override { return -1; }
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int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr) override {
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return 0;
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}
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int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) override {
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return 0;
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}
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int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc) override {
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return 0;
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}
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int DoWriteCSR(lldb::tid_t tid, int flavor, const CSR &csr) override {
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return 0;
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}
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};
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static uint32_t MachHeaderSizeFromMagic(uint32_t magic) {
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switch (magic) {
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case MH_MAGIC:
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@@ -5827,6 +5969,11 @@ ObjectFileMachO::GetThreadContextAtIndex(uint32_t idx,
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reg_ctx_sp =
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std::make_shared<RegisterContextDarwin_x86_64_Mach>(thread, data);
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break;
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case llvm::MachO::CPU_TYPE_RISCV:
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reg_ctx_sp =
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std::make_shared<RegisterContextDarwin_riscv32_Mach>(thread, data);
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break;
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}
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}
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}
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@@ -6695,6 +6842,11 @@ bool ObjectFileMachO::SaveCore(const lldb::ProcessSP &process_sp,
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RegisterContextDarwin_x86_64_Mach::Create_LC_THREAD(
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thread_sp.get(), LC_THREAD_datas[thread_idx]);
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break;
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case llvm::MachO::CPU_TYPE_RISCV:
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RegisterContextDarwin_riscv32_Mach::Create_LC_THREAD(
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thread_sp.get(), LC_THREAD_datas[thread_idx]);
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break;
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}
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}
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}
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@@ -20,6 +20,7 @@ add_lldb_library(lldbPluginProcessUtility
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RegisterContextDarwin_arm.cpp
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RegisterContextDarwin_arm64.cpp
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RegisterContextDarwin_i386.cpp
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RegisterContextDarwin_riscv32.cpp
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RegisterContextDarwin_x86_64.cpp
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RegisterContextDummy.cpp
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RegisterContextFreeBSD_i386.cpp
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,260 @@
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//===-- RegisterContextDarwin_riscv32.h -------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
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#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
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#include "lldb/Target/RegisterContext.h"
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#include "lldb/lldb-private.h"
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class RegisterContextDarwin_riscv32 : public lldb_private::RegisterContext {
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public:
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RegisterContextDarwin_riscv32(lldb_private::Thread &thread,
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uint32_t concrete_frame_idx);
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~RegisterContextDarwin_riscv32() override;
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void InvalidateAllRegisters() override;
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size_t GetRegisterCount() override;
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const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
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size_t GetRegisterSetCount() override;
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const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
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bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
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lldb_private::RegisterValue &value) override;
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bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
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const lldb_private::RegisterValue &value) override;
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bool ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;
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bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
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uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
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uint32_t num) override;
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struct GPR {
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uint32_t x0;
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uint32_t x1;
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uint32_t x2;
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uint32_t x3;
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uint32_t x4;
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uint32_t x5;
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uint32_t x6;
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uint32_t x7;
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uint32_t x8;
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uint32_t x9;
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uint32_t x10;
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uint32_t x11;
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uint32_t x12;
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uint32_t x13;
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uint32_t x14;
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uint32_t x15;
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uint32_t x16;
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uint32_t x17;
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uint32_t x18;
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uint32_t x19;
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uint32_t x20;
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uint32_t x21;
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uint32_t x22;
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uint32_t x23;
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uint32_t x24;
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uint32_t x25;
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uint32_t x26;
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uint32_t x27;
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uint32_t x28;
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uint32_t x29;
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uint32_t x30;
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uint32_t x31;
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uint32_t pc;
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};
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struct FPU {
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uint32_t f0;
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uint32_t f1;
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uint32_t f2;
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uint32_t f3;
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uint32_t f4;
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uint32_t f5;
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uint32_t f6;
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uint32_t f7;
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uint32_t f8;
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uint32_t f9;
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uint32_t f10;
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uint32_t f11;
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uint32_t f12;
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uint32_t f13;
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uint32_t f14;
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uint32_t f15;
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uint32_t f16;
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uint32_t f17;
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uint32_t f18;
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uint32_t f19;
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uint32_t f20;
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uint32_t f21;
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uint32_t f22;
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uint32_t f23;
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uint32_t f24;
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uint32_t f25;
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uint32_t f26;
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uint32_t f27;
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uint32_t f28;
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uint32_t f29;
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uint32_t f30;
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uint32_t f31;
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uint32_t fcsr;
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};
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struct EXC {
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uint32_t exception;
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uint32_t fsr;
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uint32_t far;
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};
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struct CSR {
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uint32_t csr[1024];
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};
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protected:
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enum {
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GPRRegSet = 2, // RV32_THREAD_STATE
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EXCRegSet = 3, // RV32_EXCEPTION_STATE
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FPURegSet = 4, // RV_FP32_STATE
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CSRRegSet1 = 6, // RV_CSR_STATE1
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CSRRegSet2 = 7, // RV_CSR_STATE2
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CSRRegSet3 = 8, // RV_CSR_STATE3
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CSRRegSet4 = 9, // RV_CSR_STATE4
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CSRRegSet = 10 // full 16kbyte CSR reg bank
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};
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enum {
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GPRWordCount = sizeof(GPR) / sizeof(uint32_t),
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FPUWordCount = sizeof(FPU) / sizeof(uint32_t),
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EXCWordCount = sizeof(EXC) / sizeof(uint32_t),
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CSRWordCount = sizeof(CSR) / sizeof(uint32_t)
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};
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enum { Read = 0, Write = 1, kNumErrors = 2 };
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GPR gpr;
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FPU fpr;
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EXC exc;
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CSR csr;
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int gpr_errs[2]; // Read/Write errors
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int fpr_errs[2]; // Read/Write errors
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int exc_errs[2]; // Read/Write errors
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int csr_errs[2]; // Read/Write errors
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void InvalidateAllRegisterStates() {
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SetError(GPRRegSet, Read, -1);
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SetError(FPURegSet, Read, -1);
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SetError(EXCRegSet, Read, -1);
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SetError(CSRRegSet, Read, -1);
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}
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int GetError(int flavor, uint32_t err_idx) const {
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if (err_idx < kNumErrors) {
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switch (flavor) {
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// When getting all errors, just OR all values together to see if
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// we got any kind of error.
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case GPRRegSet:
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return gpr_errs[err_idx];
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case FPURegSet:
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return fpr_errs[err_idx];
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case EXCRegSet:
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return exc_errs[err_idx];
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case CSRRegSet:
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return csr_errs[err_idx];
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default:
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break;
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}
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}
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return -1;
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}
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bool SetError(int flavor, uint32_t err_idx, int err) {
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if (err_idx < kNumErrors) {
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switch (flavor) {
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case GPRRegSet:
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gpr_errs[err_idx] = err;
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return true;
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case FPURegSet:
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fpr_errs[err_idx] = err;
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return true;
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case EXCRegSet:
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exc_errs[err_idx] = err;
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return true;
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case CSRRegSet:
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csr_errs[err_idx] = err;
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return true;
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default:
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break;
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}
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}
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return false;
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}
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bool RegisterSetIsCached(int set) const { return GetError(set, Read) == 0; }
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void LogGPR(lldb_private::Log *log, const char *title);
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int ReadGPR(bool force);
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int ReadFPU(bool force);
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int ReadEXC(bool force);
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int ReadCSR(bool force);
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int WriteGPR();
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int WriteFPU();
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int WriteEXC();
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int WriteCSR();
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// Subclasses override these to do the actual reading.
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virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr) = 0;
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virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpr) = 0;
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virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc) = 0;
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virtual int DoReadCSR(lldb::tid_t tid, int flavor, CSR &exc) = 0;
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virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
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virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpr) = 0;
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virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc) = 0;
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virtual int DoWriteCSR(lldb::tid_t tid, int flavor, const CSR &exc) = 0;
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int ReadRegisterSet(uint32_t set, bool force);
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int WriteRegisterSet(uint32_t set);
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static uint32_t GetRegisterNumber(uint32_t reg_kind, uint32_t reg_num);
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static int GetSetForNativeRegNum(int reg_num);
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static size_t GetRegisterInfosCount();
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static const lldb_private::RegisterInfo *GetRegisterInfos();
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};
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||||
|
||||
#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
|
||||
7
lldb/test/API/macosx/riscv32-corefile/Makefile
Normal file
7
lldb/test/API/macosx/riscv32-corefile/Makefile
Normal file
@@ -0,0 +1,7 @@
|
||||
MAKE_DSYM := NO
|
||||
CXX_SOURCES := create-empty-riscv-corefile.cpp
|
||||
EXE := create-empty-riscv-corefile
|
||||
|
||||
all: create-empty-riscv-corefile
|
||||
|
||||
include Makefile.rules
|
||||
@@ -0,0 +1,82 @@
|
||||
"""Test that all of the GPR registers are read correctly from a riscv32 corefile."""
|
||||
|
||||
import os
|
||||
import re
|
||||
import subprocess
|
||||
|
||||
import lldb
|
||||
from lldbsuite.test.decorators import *
|
||||
from lldbsuite.test.lldbtest import *
|
||||
from lldbsuite.test import lldbutil
|
||||
|
||||
|
||||
class TestRV32MachOCorefile(TestBase):
|
||||
NO_DEBUG_INFO_TESTCASE = True
|
||||
|
||||
@skipUnlessDarwin
|
||||
def test_riscv32_gpr_corefile_registers(self):
|
||||
self.build()
|
||||
create_corefile = self.getBuildArtifact("create-empty-riscv-corefile")
|
||||
corefile = self.getBuildArtifact("core")
|
||||
call(create_corefile + " " + corefile, shell=True)
|
||||
|
||||
target = self.dbg.CreateTarget("")
|
||||
process = target.LoadCore(corefile)
|
||||
|
||||
process = target.GetProcess()
|
||||
self.assertEqual(process.GetNumThreads(), 1)
|
||||
|
||||
thread = process.GetThreadAtIndex(0)
|
||||
self.assertEqual(thread.GetNumFrames(), 1)
|
||||
|
||||
frame = thread.GetFrameAtIndex(0)
|
||||
gpr_regs = frame.registers.GetValueAtIndex(0)
|
||||
|
||||
self.assertEqual(gpr_regs.GetName(), "General Purpose Registers")
|
||||
self.assertEqual(gpr_regs.GetNumChildren(), 33)
|
||||
regnames = [
|
||||
"zero",
|
||||
"ra",
|
||||
"sp",
|
||||
"gp",
|
||||
"tp",
|
||||
"t0",
|
||||
"t1",
|
||||
"t2",
|
||||
"fp",
|
||||
"s1",
|
||||
"a0",
|
||||
"a1",
|
||||
"a2",
|
||||
"a3",
|
||||
"a4",
|
||||
"a5",
|
||||
"a6",
|
||||
"a7",
|
||||
"s2",
|
||||
"s3",
|
||||
"s4",
|
||||
"s5",
|
||||
"s6",
|
||||
"s7",
|
||||
"s8",
|
||||
"s9",
|
||||
"s10",
|
||||
"s11",
|
||||
"t3",
|
||||
"t4",
|
||||
"t5",
|
||||
"t6",
|
||||
"pc",
|
||||
]
|
||||
|
||||
idx = 0
|
||||
while idx < len(regnames):
|
||||
self.assertEqual(gpr_regs.GetChildAtIndex(idx).GetName(), regnames[idx])
|
||||
idx = idx + 1
|
||||
|
||||
idx = 0
|
||||
while idx < len(regnames):
|
||||
val = idx | (idx << 8) | (idx << 16) | (idx << 24)
|
||||
self.assertEqual(gpr_regs.GetChildAtIndex(idx).GetValueAsUnsigned(), val)
|
||||
idx = idx + 1
|
||||
@@ -0,0 +1,116 @@
|
||||
#include <inttypes.h>
|
||||
#include <mach-o/loader.h>
|
||||
#include <mach/thread_status.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <string>
|
||||
#include <sys/errno.h>
|
||||
#include <uuid/uuid.h>
|
||||
#include <vector>
|
||||
|
||||
#define CPU_TYPE_RISCV 24
|
||||
#define CPU_SUBTYPE_RISCV_ALL 0
|
||||
#define RV32_THREAD_STATE 2
|
||||
// x0-x31 + pc, all 32-bit
|
||||
#define RV32_THREAD_STATE_COUNT 33
|
||||
|
||||
union uint32_buf {
|
||||
uint8_t bytebuf[4];
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
union uint64_buf {
|
||||
uint8_t bytebuf[8];
|
||||
uint64_t val;
|
||||
};
|
||||
|
||||
void add_uint64(std::vector<uint8_t> &buf, uint64_t val) {
|
||||
uint64_buf conv;
|
||||
conv.val = val;
|
||||
for (int i = 0; i < 8; i++)
|
||||
buf.push_back(conv.bytebuf[i]);
|
||||
}
|
||||
|
||||
void add_uint32(std::vector<uint8_t> &buf, uint32_t val) {
|
||||
uint32_buf conv;
|
||||
conv.val = val;
|
||||
for (int i = 0; i < 4; i++)
|
||||
buf.push_back(conv.bytebuf[i]);
|
||||
}
|
||||
|
||||
std::vector<uint8_t> lc_thread_load_command() {
|
||||
std::vector<uint8_t> data;
|
||||
add_uint32(data, LC_THREAD); // thread_command.cmd
|
||||
add_uint32(data, 4 + 4 + 4 + 4 +
|
||||
(RV32_THREAD_STATE_COUNT * 4)); // thread_command.cmdsize
|
||||
add_uint32(data, RV32_THREAD_STATE); // thread_command.flavor
|
||||
add_uint32(data, RV32_THREAD_STATE_COUNT); // thread_command.count
|
||||
for (int i = 0; i < RV32_THREAD_STATE_COUNT; i++) {
|
||||
add_uint32(data, i | (i << 8) | (i << 16) | (i << 24));
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
int main(int argc, char **argv) {
|
||||
if (argc != 2) {
|
||||
fprintf(stderr,
|
||||
"usage: create-empty-riscv-corefile output-corefile-name\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
cpu_type_t cputype = CPU_TYPE_RISCV;
|
||||
cpu_subtype_t cpusubtype = CPU_SUBTYPE_RISCV_ALL;
|
||||
|
||||
// An array of load commands (in the form of byte arrays)
|
||||
std::vector<std::vector<uint8_t>> load_commands;
|
||||
|
||||
// An array of corefile contents (page data, lc_note data, etc)
|
||||
std::vector<uint8_t> payload;
|
||||
|
||||
// First add all the load commands / payload so we can figure out how large
|
||||
// the load commands will actually be.
|
||||
load_commands.push_back(lc_thread_load_command());
|
||||
|
||||
int size_of_load_commands = 0;
|
||||
for (const auto &lc : load_commands)
|
||||
size_of_load_commands += lc.size();
|
||||
|
||||
int header_and_load_cmd_room =
|
||||
sizeof(struct mach_header_64) + size_of_load_commands;
|
||||
|
||||
// Erase the load commands / payload now that we know how much space is
|
||||
// needed, redo it.
|
||||
load_commands.clear();
|
||||
payload.clear();
|
||||
|
||||
load_commands.push_back(lc_thread_load_command());
|
||||
|
||||
struct mach_header mh;
|
||||
mh.magic = MH_MAGIC;
|
||||
mh.cputype = cputype;
|
||||
|
||||
mh.cpusubtype = cpusubtype;
|
||||
mh.filetype = MH_CORE;
|
||||
mh.ncmds = load_commands.size();
|
||||
mh.sizeofcmds = size_of_load_commands;
|
||||
mh.flags = 0;
|
||||
|
||||
FILE *f = fopen(argv[1], "w");
|
||||
|
||||
if (f == nullptr) {
|
||||
fprintf(stderr, "Unable to open file %s for writing\n", argv[1]);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
fwrite(&mh, sizeof(struct mach_header), 1, f);
|
||||
|
||||
for (const auto &lc : load_commands)
|
||||
fwrite(lc.data(), lc.size(), 1, f);
|
||||
|
||||
fseek(f, header_and_load_cmd_room, SEEK_SET);
|
||||
|
||||
fwrite(payload.data(), payload.size(), 1, f);
|
||||
|
||||
fclose(f);
|
||||
}
|
||||
Reference in New Issue
Block a user