[SPIR-V] Implement intrinsics llvm.scmp.* and llvm.ucmp.* (#117341)
This PR add translation of intrinsics `llvm.scmp.*` and `llvm.ucmp.*`.
This commit is contained in:
Vyacheslav Levytskyy
committed by
GitHub
GitHub
parent
243c979187
commit
0f13170438
@@ -210,6 +210,9 @@ private:
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bool selectTrunc(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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bool selectSUCmp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
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bool IsSigned) const;
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bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I,
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const SPIRVType *intTy, const SPIRVType *boolTy) const;
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@@ -241,8 +244,10 @@ private:
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bool selectPhi(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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bool selectExtInst(Register ResVReg, const SPIRVType *RestType,
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MachineInstr &I, GL::GLSLExtInst GLInst) const;
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[[maybe_unused]] bool selectExtInst(Register ResVReg,
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const SPIRVType *RestType,
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MachineInstr &I,
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GL::GLSLExtInst GLInst) const;
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bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I, CL::OpenCLExtInst CLInst) const;
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bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
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@@ -533,6 +538,11 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
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case TargetOpcode::G_UMAX:
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return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax);
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case TargetOpcode::G_SCMP:
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return selectSUCmp(ResVReg, ResType, I, true);
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case TargetOpcode::G_UCMP:
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return selectSUCmp(ResVReg, ResType, I, false);
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case TargetOpcode::G_FMA:
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return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
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@@ -2398,6 +2408,67 @@ bool SPIRVInstructionSelector::selectExt(Register ResVReg,
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return selectUnOp(ResVReg, ResType, I, Opcode);
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}
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bool SPIRVInstructionSelector::selectSUCmp(Register ResVReg,
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const SPIRVType *ResType,
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MachineInstr &I,
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bool IsSigned) const {
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MachineIRBuilder MIRBuilder(I);
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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MachineBasicBlock &BB = *I.getParent();
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// Ensure we have bool.
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SPIRVType *BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
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unsigned N = GR.getScalarOrVectorComponentCount(ResType);
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if (N > 1)
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BoolType = GR.getOrCreateSPIRVVectorType(BoolType, N, I, TII);
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Register BoolTypeReg = GR.getSPIRVTypeID(BoolType);
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// Build less-than-equal and less-than.
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// TODO: replace with one-liner createVirtualRegister() from
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// llvm/lib/Target/SPIRV/SPIRVUtils.cpp when PR #116609 is merged.
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Register IsLessEqReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
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MRI->setType(IsLessEqReg, LLT::scalar(64));
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GR.assignSPIRVTypeToVReg(ResType, IsLessEqReg, MIRBuilder.getMF());
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bool Result = BuildMI(BB, I, I.getDebugLoc(),
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TII.get(IsSigned ? SPIRV::OpSLessThanEqual
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: SPIRV::OpULessThanEqual))
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.addDef(IsLessEqReg)
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.addUse(BoolTypeReg)
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.addUse(I.getOperand(1).getReg())
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.addUse(I.getOperand(2).getReg())
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.constrainAllUses(TII, TRI, RBI);
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Register IsLessReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
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MRI->setType(IsLessReg, LLT::scalar(64));
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GR.assignSPIRVTypeToVReg(ResType, IsLessReg, MIRBuilder.getMF());
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Result &= BuildMI(BB, I, I.getDebugLoc(),
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TII.get(IsSigned ? SPIRV::OpSLessThan : SPIRV::OpULessThan))
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.addDef(IsLessReg)
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.addUse(BoolTypeReg)
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.addUse(I.getOperand(1).getReg())
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.addUse(I.getOperand(2).getReg())
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.constrainAllUses(TII, TRI, RBI);
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// Build selects.
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Register ResTypeReg = GR.getSPIRVTypeID(ResType);
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Register NegOneOrZeroReg =
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MRI->createVirtualRegister(GR.getRegClass(ResType));
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MRI->setType(NegOneOrZeroReg, LLT::scalar(64));
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GR.assignSPIRVTypeToVReg(ResType, NegOneOrZeroReg, MIRBuilder.getMF());
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unsigned SelectOpcode =
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N > 1 ? SPIRV::OpSelectVIVCond : SPIRV::OpSelectSISCond;
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Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode))
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.addDef(NegOneOrZeroReg)
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.addUse(ResTypeReg)
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.addUse(IsLessReg)
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.addUse(buildOnesVal(true, ResType, I)) // -1
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.addUse(buildZerosVal(ResType, I))
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.constrainAllUses(TII, TRI, RBI);
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return Result & BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode))
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.addDef(ResVReg)
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.addUse(ResTypeReg)
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.addUse(IsLessEqReg)
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.addUse(NegOneOrZeroReg) // -1 or 0
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.addUse(buildOnesVal(false, ResType, I))
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.constrainAllUses(TII, TRI, RBI);
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}
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bool SPIRVInstructionSelector::selectIntToBool(Register IntReg,
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Register ResVReg,
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MachineInstr &I,
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@@ -212,7 +212,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
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getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_ABS,
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G_BITREVERSE, G_SADDSAT, G_UADDSAT, G_SSUBSAT,
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G_USUBSAT})
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G_USUBSAT, G_SCMP, G_UCMP})
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.legalFor(allIntScalarsAndVectors)
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.legalIf(extendedScalarsAndVectors);
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148
llvm/test/CodeGen/SPIRV/llvm-intrinsics/scmp.ll
Normal file
148
llvm/test/CodeGen/SPIRV/llvm-intrinsics/scmp.ll
Normal file
@@ -0,0 +1,148 @@
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[TypeI8:.*]] = OpTypeInt 8 0
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; CHECK-DAG: %[[TypeI16:.*]] = OpTypeInt 16 0
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; CHECK-DAG: %[[TypeI32:.*]] = OpTypeInt 32 0
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; CHECK-DAG: %[[TypeI64:.*]] = OpTypeInt 64 0
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; CHECK-DAG: %[[CmpI64ConstMinusOne:.*]] = OpConstant %[[TypeI64]] 18446744073709551615
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; CHECK-DAG: %[[CmpI8ConstOne:.*]] = OpConstant %[[TypeI8]] 1
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; CHECK-DAG: %[[CmpI8ConstZero:.*]] = OpConstantNull %[[TypeI8]]
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; CHECK-DAG: %[[CmpI8ConstMinusOne:.*]] = OpConstant %[[TypeI8]] 255
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; CHECK-DAG: %[[CmpI16ConstOne:.*]] = OpConstant %[[TypeI16]] 1
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; CHECK-DAG: %[[CmpI16ConstZero:.*]] = OpConstantNull %[[TypeI16]]
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; CHECK-DAG: %[[CmpI16ConstMinusOne:.*]] = OpConstant %[[TypeI16]] 65535
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; CHECK-DAG: %[[CmpI32ConstOne:.*]] = OpConstant %[[TypeI32]] 1
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; CHECK-DAG: %[[CmpI32ConstZero:.*]] = OpConstantNull %[[TypeI32]]
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; CHECK-DAG: %[[CmpI32ConstMinusOne:.*]] = OpConstant %[[TypeI32]] 4294967295
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; CHECK-DAG: %[[CmpI64ConstOne:.*]] = OpConstant %[[TypeI64]] 1
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; CHECK-DAG: %[[CmpI64ConstZero:.*]] = OpConstantNull %[[TypeI64]]
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; CHECK-DAG: %[[TypeBool:.*]] = OpTypeBool
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; CHECK-DAG: %[[TypeVBool:.*]] = OpTypeVector %[[TypeBool]] 4
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; CHECK-DAG: %[[TypeV4I8:.*]] = OpTypeVector %[[TypeI8]] 4
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; CHECK-DAG: %[[TypeV4I16:.*]] = OpTypeVector %[[TypeI16]] 4
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; CHECK-DAG: %[[TypeV4I32:.*]] = OpTypeVector %[[TypeI32]] 4
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; CHECK-DAG: %[[TypeV4I64:.*]] = OpTypeVector %[[TypeI64]] 4
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; CHECK-DAG: %[[V4I8ConstOne:.*]] = OpConstantComposite %[[TypeV4I8]] %[[CmpI8ConstOne]] %[[CmpI8ConstOne]] %[[CmpI8ConstOne]] %[[CmpI8ConstOne]]
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; CHECK-DAG: %[[V4I8ConstZero:.*]] = OpConstantNull %[[TypeV4I8]]
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; CHECK-DAG: %[[V4I8ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I8]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstMinusOne]]
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; CHECK-DAG: %[[V4I16ConstOne:.*]] = OpConstantComposite %[[TypeV4I16]] %[[CmpI16ConstOne]] %[[CmpI16ConstOne]] %[[CmpI16ConstOne]] %[[CmpI16ConstOne]]
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; CHECK-DAG: %[[V4I16ConstZero:.*]] = OpConstantNull %[[TypeV4I16]]
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; CHECK-DAG: %[[V4I16ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I16]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstMinusOne]]
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; CHECK-DAG: %[[V4I32ConstOne:.*]] = OpConstantComposite %[[TypeV4I32]] %[[CmpI32ConstOne]] %[[CmpI32ConstOne]] %[[CmpI32ConstOne]] %[[CmpI32ConstOne]]
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; CHECK-DAG: %[[V4I32ConstZero:.*]] = OpConstantNull %[[TypeV4I32]]
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; CHECK-DAG: %[[V4I32ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I32]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstMinusOne]]
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; CHECK-DAG: %[[V4I64ConstOne:.*]] = OpConstantComposite %[[TypeV4I64]] %[[CmpI64ConstOne]] %[[CmpI64ConstOne]] %[[CmpI64ConstOne]] %[[CmpI64ConstOne]]
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; CHECK-DAG: %[[V4I64ConstZero:.*]] = OpConstantNull %[[TypeV4I64]]
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; CHECK-DAG: %[[V4I64ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I64]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstMinusOne]]
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; CHECK: OpFunction
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; CHECK: %[[CmpI8R1:.*]] = OpSLessThanEqual %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[CmpI8R2:.*]] = OpSLessThan %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[SelI8R1:.*]] = OpSelect %[[TypeI8]] %[[CmpI8R2]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstZero]]
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; CHECK: %[[SelI8R2:.*]] = OpSelect %[[TypeI8]] %[[CmpI8R1]] %[[SelI8R1]] %[[CmpI8ConstOne]]
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; CHECK: OpReturnValue %[[SelI8R2]]
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define range(i8 -1, 2) i8 @test_i8(i8 noundef %0, i8 noundef %1) {
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%3 = tail call i8 @llvm.scmp.i8.i8(i8 %0, i8 %1)
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ret i8 %3
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}
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; CHECK: OpFunction
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; CHECK: %[[CmpI16R1:.*]] = OpSLessThanEqual %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[CmpI16R2:.*]] = OpSLessThan %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[SelI16R1:.*]] = OpSelect %[[TypeI16]] %[[CmpI16R2]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstZero]]
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; CHECK: %[[SelI16R2:.*]] = OpSelect %[[TypeI16]] %[[CmpI16R1]] %[[SelI16R1]] %[[CmpI16ConstOne]]
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; CHECK: OpReturnValue %[[SelI16R2]]
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define range(i16 -1, 2) i16 @test_i16(i16 noundef %0, i16 noundef %1) {
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%3 = tail call i16 @llvm.scmp.i16.i16(i16 %0, i16 %1)
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ret i16 %3
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}
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; CHECK: OpFunction
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; CHECK: %[[CmpI32R1:.*]] = OpSLessThanEqual %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[CmpI32R2:.*]] = OpSLessThan %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[SelI32R1:.*]] = OpSelect %[[TypeI32]] %[[CmpI32R2]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstZero]]
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; CHECK: %[[SelI32R2:.*]] = OpSelect %[[TypeI32]] %[[CmpI32R1]] %[[SelI32R1]] %[[CmpI32ConstOne]]
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; CHECK: OpReturnValue %[[SelI32R2]]
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define range(i32 -1, 2) i32 @test_i32(i32 noundef %0, i32 noundef %1) {
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%3 = tail call i32 @llvm.scmp.i32.i32(i32 %0, i32 %1)
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ret i32 %3
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}
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; CHECK: OpFunction
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; CHECK: %[[CmpI64R1:.*]] = OpSLessThanEqual %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[CmpI64R2:.*]] = OpSLessThan %[[TypeBool]] %[[#]] %[[#]]
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; CHECK: %[[SelI64R1:.*]] = OpSelect %[[TypeI64]] %[[CmpI64R2]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstZero]]
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; CHECK: %[[SelI64R2:.*]] = OpSelect %[[TypeI64]] %[[CmpI64R1]] %[[SelI64R1]] %[[CmpI64ConstOne]]
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; CHECK: OpReturnValue %[[SelI64R2]]
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define range(i64 -1, 2) i64 @test_i64(i64 noundef %0, i64 noundef %1) {
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%3 = tail call i64 @llvm.scmp.i64.i64(i64 %0, i64 %1)
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ret i64 %3
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}
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; CHECK: OpFunction
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; CHECK: %[[V4I8R1:.*]] = OpSLessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[V4I8R2:.*]] = OpSLessThan %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[SelectV4I8R1:.*]] = OpSelect %[[TypeV4I8]] %[[V4I8R2]] %[[V4I8ConstMinusOne]] %[[V4I8ConstZero]]
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; CHECK: %[[SelectV4I8R2:.*]] = OpSelect %[[TypeV4I8]] %[[V4I8R1]] %[[SelectV4I8R1]] %[[V4I8ConstOne]]
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; CHECK: OpReturnValue %[[SelectV4I8R2]]
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define range(i8 -1, 2) <4 x i8> @test_v4i8(<4 x i8> noundef %0, <4 x i8> noundef %1) {
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%3 = tail call <4 x i8> @llvm.scmp.v4i8.v4i8(<4 x i8> %0, <4 x i8> %1)
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ret <4 x i8> %3
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}
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; CHECK: OpFunction
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; CHECK: %[[V4I16R1:.*]] = OpSLessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[V4I16R2:.*]] = OpSLessThan %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[SelectV4I16R1:.*]] = OpSelect %[[TypeV4I16]] %[[V4I16R2]] %[[V4I16ConstMinusOne]] %[[V4I16ConstZero]]
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; CHECK: %[[SelectV4I16R2:.*]] = OpSelect %[[TypeV4I16]] %[[V4I16R1]] %[[SelectV4I16R1]] %[[V4I16ConstOne]]
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; CHECK: OpReturnValue %[[SelectV4I16R2]]
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define range(i16 -1, 2) <4 x i16> @test_v4i16(<4 x i16> noundef %0, <4 x i16> noundef %1) {
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%3 = tail call <4 x i16> @llvm.scmp.v4i16.v4i16(<4 x i16> %0, <4 x i16> %1)
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ret <4 x i16> %3
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}
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; CHECK: OpFunction
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; CHECK: %[[V4I32R1:.*]] = OpSLessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[V4I32R2:.*]] = OpSLessThan %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[SelectV4I32R1:.*]] = OpSelect %[[TypeV4I32]] %[[V4I32R2]] %[[V4I32ConstMinusOne]] %[[V4I32ConstZero]]
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; CHECK: %[[SelectV4I32R2:.*]] = OpSelect %[[TypeV4I32]] %[[V4I32R1]] %[[SelectV4I32R1]] %[[V4I32ConstOne]]
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; CHECK: OpReturnValue %[[SelectV4I32R2]]
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define range(i32 -1, 2) <4 x i32> @test_v4i32(<4 x i32> noundef %0, <4 x i32> noundef %1) {
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%3 = tail call <4 x i32> @llvm.scmp.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %3
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}
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; CHECK: OpFunction
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; CHECK: %[[V4I64R1:.*]] = OpSLessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[V4I64R2:.*]] = OpSLessThan %[[TypeVBool]] %[[#]] %[[#]]
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; CHECK: %[[SelectV4I64R1:.*]] = OpSelect %[[TypeV4I64]] %[[V4I64R2]] %[[V4I64ConstMinusOne]] %[[V4I64ConstZero]]
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; CHECK: %[[SelectV4I64R2:.*]] = OpSelect %[[TypeV4I64]] %[[V4I64R1]] %[[SelectV4I64R1]] %[[V4I64ConstOne]]
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; CHECK: OpReturnValue %[[SelectV4I64R2]]
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define range(i64 -1, 2) <4 x i64> @test_v4i64(<4 x i64> noundef %0, <4 x i64> noundef %1) {
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%3 = tail call <4 x i64> @llvm.scmp.v4i64.v4i64(<4 x i64> %0, <4 x i64> %1)
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ret <4 x i64> %3
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}
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declare i8 @llvm.scmp.i8.i8(i8, i8)
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declare i16 @llvm.scmp.i16.i16(i16, i16)
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declare i32 @llvm.scmp.i32.i32(i32, i32)
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declare i64 @llvm.scmp.i64.i64(i64, i64)
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declare <4 x i8> @llvm.scmp.v4i8.v4i8(<4 x i8>, <4 x i8>)
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declare <4 x i16> @llvm.scmp.v4i16.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i32> @llvm.scmp.v4i32.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i64> @llvm.scmp.v4i64.v4i64(<4 x i64>, <4 x i64>)
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148
llvm/test/CodeGen/SPIRV/llvm-intrinsics/ucmp.ll
Normal file
148
llvm/test/CodeGen/SPIRV/llvm-intrinsics/ucmp.ll
Normal file
@@ -0,0 +1,148 @@
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[TypeI8:.*]] = OpTypeInt 8 0
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; CHECK-DAG: %[[TypeI16:.*]] = OpTypeInt 16 0
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||||
; CHECK-DAG: %[[TypeI32:.*]] = OpTypeInt 32 0
|
||||
; CHECK-DAG: %[[TypeI64:.*]] = OpTypeInt 64 0
|
||||
|
||||
; CHECK-DAG: %[[CmpI64ConstMinusOne:.*]] = OpConstant %[[TypeI64]] 18446744073709551615
|
||||
|
||||
; CHECK-DAG: %[[CmpI8ConstOne:.*]] = OpConstant %[[TypeI8]] 1
|
||||
; CHECK-DAG: %[[CmpI8ConstZero:.*]] = OpConstantNull %[[TypeI8]]
|
||||
; CHECK-DAG: %[[CmpI8ConstMinusOne:.*]] = OpConstant %[[TypeI8]] 255
|
||||
|
||||
; CHECK-DAG: %[[CmpI16ConstOne:.*]] = OpConstant %[[TypeI16]] 1
|
||||
; CHECK-DAG: %[[CmpI16ConstZero:.*]] = OpConstantNull %[[TypeI16]]
|
||||
; CHECK-DAG: %[[CmpI16ConstMinusOne:.*]] = OpConstant %[[TypeI16]] 65535
|
||||
|
||||
; CHECK-DAG: %[[CmpI32ConstOne:.*]] = OpConstant %[[TypeI32]] 1
|
||||
; CHECK-DAG: %[[CmpI32ConstZero:.*]] = OpConstantNull %[[TypeI32]]
|
||||
; CHECK-DAG: %[[CmpI32ConstMinusOne:.*]] = OpConstant %[[TypeI32]] 4294967295
|
||||
|
||||
; CHECK-DAG: %[[CmpI64ConstOne:.*]] = OpConstant %[[TypeI64]] 1
|
||||
; CHECK-DAG: %[[CmpI64ConstZero:.*]] = OpConstantNull %[[TypeI64]]
|
||||
|
||||
; CHECK-DAG: %[[TypeBool:.*]] = OpTypeBool
|
||||
; CHECK-DAG: %[[TypeVBool:.*]] = OpTypeVector %[[TypeBool]] 4
|
||||
|
||||
; CHECK-DAG: %[[TypeV4I8:.*]] = OpTypeVector %[[TypeI8]] 4
|
||||
; CHECK-DAG: %[[TypeV4I16:.*]] = OpTypeVector %[[TypeI16]] 4
|
||||
; CHECK-DAG: %[[TypeV4I32:.*]] = OpTypeVector %[[TypeI32]] 4
|
||||
; CHECK-DAG: %[[TypeV4I64:.*]] = OpTypeVector %[[TypeI64]] 4
|
||||
|
||||
; CHECK-DAG: %[[V4I8ConstOne:.*]] = OpConstantComposite %[[TypeV4I8]] %[[CmpI8ConstOne]] %[[CmpI8ConstOne]] %[[CmpI8ConstOne]] %[[CmpI8ConstOne]]
|
||||
; CHECK-DAG: %[[V4I8ConstZero:.*]] = OpConstantNull %[[TypeV4I8]]
|
||||
; CHECK-DAG: %[[V4I8ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I8]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstMinusOne]]
|
||||
|
||||
; CHECK-DAG: %[[V4I16ConstOne:.*]] = OpConstantComposite %[[TypeV4I16]] %[[CmpI16ConstOne]] %[[CmpI16ConstOne]] %[[CmpI16ConstOne]] %[[CmpI16ConstOne]]
|
||||
; CHECK-DAG: %[[V4I16ConstZero:.*]] = OpConstantNull %[[TypeV4I16]]
|
||||
; CHECK-DAG: %[[V4I16ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I16]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstMinusOne]]
|
||||
|
||||
; CHECK-DAG: %[[V4I32ConstOne:.*]] = OpConstantComposite %[[TypeV4I32]] %[[CmpI32ConstOne]] %[[CmpI32ConstOne]] %[[CmpI32ConstOne]] %[[CmpI32ConstOne]]
|
||||
; CHECK-DAG: %[[V4I32ConstZero:.*]] = OpConstantNull %[[TypeV4I32]]
|
||||
; CHECK-DAG: %[[V4I32ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I32]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstMinusOne]]
|
||||
|
||||
; CHECK-DAG: %[[V4I64ConstOne:.*]] = OpConstantComposite %[[TypeV4I64]] %[[CmpI64ConstOne]] %[[CmpI64ConstOne]] %[[CmpI64ConstOne]] %[[CmpI64ConstOne]]
|
||||
; CHECK-DAG: %[[V4I64ConstZero:.*]] = OpConstantNull %[[TypeV4I64]]
|
||||
; CHECK-DAG: %[[V4I64ConstMinusOne:.*]] = OpConstantComposite %[[TypeV4I64]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstMinusOne]]
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[CmpI8R1:.*]] = OpULessThanEqual %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[CmpI8R2:.*]] = OpULessThan %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelI8R1:.*]] = OpSelect %[[TypeI8]] %[[CmpI8R2]] %[[CmpI8ConstMinusOne]] %[[CmpI8ConstZero]]
|
||||
; CHECK: %[[SelI8R2:.*]] = OpSelect %[[TypeI8]] %[[CmpI8R1]] %[[SelI8R1]] %[[CmpI8ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelI8R2]]
|
||||
define range(i8 -1, 2) i8 @test_i8(i8 noundef %0, i8 noundef %1) {
|
||||
%3 = tail call i8 @llvm.ucmp.i8.i8(i8 %0, i8 %1)
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[CmpI16R1:.*]] = OpULessThanEqual %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[CmpI16R2:.*]] = OpULessThan %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelI16R1:.*]] = OpSelect %[[TypeI16]] %[[CmpI16R2]] %[[CmpI16ConstMinusOne]] %[[CmpI16ConstZero]]
|
||||
; CHECK: %[[SelI16R2:.*]] = OpSelect %[[TypeI16]] %[[CmpI16R1]] %[[SelI16R1]] %[[CmpI16ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelI16R2]]
|
||||
define range(i16 -1, 2) i16 @test_i16(i16 noundef %0, i16 noundef %1) {
|
||||
%3 = tail call i16 @llvm.ucmp.i16.i16(i16 %0, i16 %1)
|
||||
ret i16 %3
|
||||
}
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[CmpI32R1:.*]] = OpULessThanEqual %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[CmpI32R2:.*]] = OpULessThan %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelI32R1:.*]] = OpSelect %[[TypeI32]] %[[CmpI32R2]] %[[CmpI32ConstMinusOne]] %[[CmpI32ConstZero]]
|
||||
; CHECK: %[[SelI32R2:.*]] = OpSelect %[[TypeI32]] %[[CmpI32R1]] %[[SelI32R1]] %[[CmpI32ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelI32R2]]
|
||||
define range(i32 -1, 2) i32 @test_i32(i32 noundef %0, i32 noundef %1) {
|
||||
%3 = tail call i32 @llvm.ucmp.i32.i32(i32 %0, i32 %1)
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[CmpI64R1:.*]] = OpULessThanEqual %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[CmpI64R2:.*]] = OpULessThan %[[TypeBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelI64R1:.*]] = OpSelect %[[TypeI64]] %[[CmpI64R2]] %[[CmpI64ConstMinusOne]] %[[CmpI64ConstZero]]
|
||||
; CHECK: %[[SelI64R2:.*]] = OpSelect %[[TypeI64]] %[[CmpI64R1]] %[[SelI64R1]] %[[CmpI64ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelI64R2]]
|
||||
define range(i64 -1, 2) i64 @test_i64(i64 noundef %0, i64 noundef %1) {
|
||||
%3 = tail call i64 @llvm.ucmp.i64.i64(i64 %0, i64 %1)
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[V4I8R1:.*]] = OpULessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[V4I8R2:.*]] = OpULessThan %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelectV4I8R1:.*]] = OpSelect %[[TypeV4I8]] %[[V4I8R2]] %[[V4I8ConstMinusOne]] %[[V4I8ConstZero]]
|
||||
; CHECK: %[[SelectV4I8R2:.*]] = OpSelect %[[TypeV4I8]] %[[V4I8R1]] %[[SelectV4I8R1]] %[[V4I8ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelectV4I8R2]]
|
||||
define range(i8 -1, 2) <4 x i8> @test_v4i8(<4 x i8> noundef %0, <4 x i8> noundef %1) {
|
||||
%3 = tail call <4 x i8> @llvm.ucmp.v4i8.v4i8(<4 x i8> %0, <4 x i8> %1)
|
||||
ret <4 x i8> %3
|
||||
}
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[V4I16R1:.*]] = OpULessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[V4I16R2:.*]] = OpULessThan %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelectV4I16R1:.*]] = OpSelect %[[TypeV4I16]] %[[V4I16R2]] %[[V4I16ConstMinusOne]] %[[V4I16ConstZero]]
|
||||
; CHECK: %[[SelectV4I16R2:.*]] = OpSelect %[[TypeV4I16]] %[[V4I16R1]] %[[SelectV4I16R1]] %[[V4I16ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelectV4I16R2]]
|
||||
define range(i16 -1, 2) <4 x i16> @test_v4i16(<4 x i16> noundef %0, <4 x i16> noundef %1) {
|
||||
%3 = tail call <4 x i16> @llvm.ucmp.v4i16.v4i16(<4 x i16> %0, <4 x i16> %1)
|
||||
ret <4 x i16> %3
|
||||
}
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[V4I32R1:.*]] = OpULessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[V4I32R2:.*]] = OpULessThan %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelectV4I32R1:.*]] = OpSelect %[[TypeV4I32]] %[[V4I32R2]] %[[V4I32ConstMinusOne]] %[[V4I32ConstZero]]
|
||||
; CHECK: %[[SelectV4I32R2:.*]] = OpSelect %[[TypeV4I32]] %[[V4I32R1]] %[[SelectV4I32R1]] %[[V4I32ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelectV4I32R2]]
|
||||
define range(i32 -1, 2) <4 x i32> @test_v4i32(<4 x i32> noundef %0, <4 x i32> noundef %1) {
|
||||
%3 = tail call <4 x i32> @llvm.ucmp.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1)
|
||||
ret <4 x i32> %3
|
||||
}
|
||||
|
||||
; CHECK: OpFunction
|
||||
; CHECK: %[[V4I64R1:.*]] = OpULessThanEqual %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[V4I64R2:.*]] = OpULessThan %[[TypeVBool]] %[[#]] %[[#]]
|
||||
; CHECK: %[[SelectV4I64R1:.*]] = OpSelect %[[TypeV4I64]] %[[V4I64R2]] %[[V4I64ConstMinusOne]] %[[V4I64ConstZero]]
|
||||
; CHECK: %[[SelectV4I64R2:.*]] = OpSelect %[[TypeV4I64]] %[[V4I64R1]] %[[SelectV4I64R1]] %[[V4I64ConstOne]]
|
||||
; CHECK: OpReturnValue %[[SelectV4I64R2]]
|
||||
define range(i64 -1, 2) <4 x i64> @test_v4i64(<4 x i64> noundef %0, <4 x i64> noundef %1) {
|
||||
%3 = tail call <4 x i64> @llvm.ucmp.v4i64.v4i64(<4 x i64> %0, <4 x i64> %1)
|
||||
ret <4 x i64> %3
|
||||
}
|
||||
|
||||
declare i8 @llvm.ucmp.i8.i8(i8, i8)
|
||||
declare i16 @llvm.ucmp.i16.i16(i16, i16)
|
||||
declare i32 @llvm.ucmp.i32.i32(i32, i32)
|
||||
declare i64 @llvm.ucmp.i64.i64(i64, i64)
|
||||
declare <4 x i8> @llvm.ucmp.v4i8.v4i8(<4 x i8>, <4 x i8>)
|
||||
declare <4 x i16> @llvm.ucmp.v4i16.v4i16(<4 x i16>, <4 x i16>)
|
||||
declare <4 x i32> @llvm.ucmp.v4i32.v4i32(<4 x i32>, <4 x i32>)
|
||||
declare <4 x i64> @llvm.ucmp.v4i64.v4i64(<4 x i64>, <4 x i64>)
|
||||
Reference in New Issue
Block a user