caio/clang-p2996
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MC: Remove unneeded VK_None argument to MCSymbolRefExpr::create calls

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The MCSymbolRefExpr::create overload with the specifier parameter is
discouraged and being phased out. Expressions with relocation specifiers
should use MCSpecifierExpr instead.
This commit is contained in:
Fangrui Song
2025-06-27 21:22:46 -07:00
parent c6bd020714
commit 109b7d965c
5 changed files with 57 additions and 75 deletions
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5
bolt/lib/Core/BinaryFunction.cpp
View File

@@ -3328,10 +3328,7 @@ void BinaryFunction::duplicateConstantIslands() {
// Update instruction reference // Update instruction reference
Operand = MCOperand::createExpr(BC.MIB->getTargetExprFor( Operand = MCOperand::createExpr(BC.MIB->getTargetExprFor(
Inst, Inst, MCSymbolRefExpr::create(ColdSymbol, *BC.Ctx), *BC.Ctx, 0));
MCSymbolRefExpr::create(ColdSymbol, MCSymbolRefExpr::VK_None,
*BC.Ctx),
*BC.Ctx, 0));
++OpNum; ++OpNum;
} }
} }

3
bolt/lib/Passes/Instrumentation.cpp
View File

@@ -666,8 +666,7 @@ Error Instrumentation::runOnFunctions(BinaryContext &BC) {
auto IsLEA = [&BC](const MCInst &Inst) { return BC.MIB->isLEA64r(Inst); }; auto IsLEA = [&BC](const MCInst &Inst) { return BC.MIB->isLEA64r(Inst); };
const auto LEA = std::find_if( const auto LEA = std::find_if(
std::next(llvm::find_if(reverse(BB), IsLEA)), BB.rend(), IsLEA); std::next(llvm::find_if(reverse(BB), IsLEA)), BB.rend(), IsLEA);
LEA->getOperand(4).setExpr( LEA->getOperand(4).setExpr(MCSymbolRefExpr::create(Target, *BC.Ctx));
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *BC.Ctx));
} else { } else {
BC.errs() << "BOLT-WARNING: ___GLOBAL_init_65535 not found\n"; BC.errs() << "BOLT-WARNING: ___GLOBAL_init_65535 not found\n";
} }

17
bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
View File

@@ -1206,8 +1206,7 @@ public:
OI = Inst.begin() + 2; OI = Inst.begin() + 2;
} }
*OI = MCOperand::createExpr( *OI = MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
} }
/// Matches indirect branch patterns in AArch64 related to a jump table (JT), /// Matches indirect branch patterns in AArch64 related to a jump table (JT),
@@ -1633,8 +1632,7 @@ public:
.addImm(0)); .addImm(0));
Code.emplace_back(MCInstBuilder(AArch64::Bcc) Code.emplace_back(MCInstBuilder(AArch64::Bcc)
.addImm(AArch64CC::EQ) .addImm(AArch64CC::EQ)
.addExpr(MCSymbolRefExpr::create( .addExpr(MCSymbolRefExpr::create(Target, *Ctx)));
Target, MCSymbolRefExpr::VK_None, *Ctx)));
return Code; return Code;
} }
@@ -1656,8 +1654,7 @@ public:
.addImm(0)); .addImm(0));
Code.emplace_back(MCInstBuilder(AArch64::Bcc) Code.emplace_back(MCInstBuilder(AArch64::Bcc)
.addImm(AArch64CC::NE) .addImm(AArch64CC::NE)
.addExpr(MCSymbolRefExpr::create( .addExpr(MCSymbolRefExpr::create(Target, *Ctx)));
Target, MCSymbolRefExpr::VK_None, *Ctx)));
return Code; return Code;
} }
@@ -1957,8 +1954,7 @@ public:
Inst.setOpcode(IsTailCall ? AArch64::B : AArch64::BL); Inst.setOpcode(IsTailCall ? AArch64::B : AArch64::BL);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr(getTargetExprFor( Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
Inst, MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx), Inst, MCSymbolRefExpr::create(Target, *Ctx), *Ctx, 0)));
*Ctx, 0)));
if (IsTailCall) if (IsTailCall)
convertJmpToTailCall(Inst); convertJmpToTailCall(Inst);
} }
@@ -2228,9 +2224,8 @@ public:
MCContext *Ctx) const override { MCContext *Ctx) const override {
Inst.setOpcode(AArch64::B); Inst.setOpcode(AArch64::B);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr(getTargetExprFor( Inst.addOperand(MCOperand::createExpr(
Inst, MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx), getTargetExprFor(Inst, MCSymbolRefExpr::create(TBB, *Ctx), *Ctx, 0)));
*Ctx, 0)));
} }
bool shouldRecordCodeRelocation(uint32_t RelType) const override { bool shouldRecordCodeRelocation(uint32_t RelType) const override {

19
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
View File

@@ -171,8 +171,8 @@ public:
(void)Result; (void)Result;
assert(Result && "unimplemented branch"); assert(Result && "unimplemented branch");
Inst.getOperand(SymOpIndex) = MCOperand::createExpr( Inst.getOperand(SymOpIndex) =
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
} }
IndirectBranchType analyzeIndirectBranch( IndirectBranchType analyzeIndirectBranch(
@@ -233,8 +233,7 @@ public:
Inst.setOpcode(RISCV::JAL); Inst.setOpcode(RISCV::JAL);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createReg(RISCV::X0)); Inst.addOperand(MCOperand::createReg(RISCV::X0));
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx)));
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
} }
StringRef getTrapFillValue() const override { StringRef getTrapFillValue() const override {
@@ -246,8 +245,7 @@ public:
Inst.setOpcode(Opcode); Inst.setOpcode(Opcode);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr(MCSpecifierExpr::create( Inst.addOperand(MCOperand::createExpr(MCSpecifierExpr::create(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx), MCSymbolRefExpr::create(Target, *Ctx), ELF::R_RISCV_CALL_PLT, *Ctx)));
ELF::R_RISCV_CALL_PLT, *Ctx)));
} }
void createCall(MCInst &Inst, const MCSymbol *Target, void createCall(MCInst &Inst, const MCSymbol *Target,
@@ -563,8 +561,7 @@ public:
Insts.emplace_back(MCInstBuilder(RISCV::BEQ) Insts.emplace_back(MCInstBuilder(RISCV::BEQ)
.addReg(RegNo) .addReg(RegNo)
.addReg(RegTmp) .addReg(RegTmp)
.addExpr(MCSymbolRefExpr::create( .addExpr(MCSymbolRefExpr::create(Target, *Ctx)));
Target, MCSymbolRefExpr::VK_None, *Ctx)));
return Insts; return Insts;
} }
@@ -663,14 +660,12 @@ public:
if (IsTailCall) { if (IsTailCall) {
Inst.addOperand(MCOperand::createReg(RISCV::X0)); Inst.addOperand(MCOperand::createReg(RISCV::X0));
Inst.addOperand(MCOperand::createExpr(getTargetExprFor( Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
Inst, MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx), Inst, MCSymbolRefExpr::create(Target, *Ctx), *Ctx, 0)));
*Ctx, 0)));
convertJmpToTailCall(Inst); convertJmpToTailCall(Inst);
} else { } else {
Inst.addOperand(MCOperand::createReg(RISCV::X1)); Inst.addOperand(MCOperand::createReg(RISCV::X1));
Inst.addOperand(MCOperand::createExpr(getTargetExprFor( Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
Inst, MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx), Inst, MCSymbolRefExpr::create(Target, *Ctx), *Ctx, 0)));
*Ctx, 0)));
} }
} }

88
bolt/lib/Target/X86/X86MCPlusBuilder.cpp
View File

@@ -72,9 +72,9 @@ static InstructionListType createIncMemory(const MCSymbol *Target,
Insts.back().addOperand(MCOperand::createImm(1)); // ScaleAmt Insts.back().addOperand(MCOperand::createImm(1)); // ScaleAmt
Insts.back().addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg Insts.back().addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
Insts.back().addOperand(MCOperand::createExpr( Insts.back().addOperand(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, MCOperand::createExpr(MCSymbolRefExpr::create(Target,
*Ctx))); // Displacement *Ctx))); // Displacement
Insts.back().addOperand( Insts.back().addOperand(
MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
return Insts; return Insts;
@@ -1625,9 +1625,8 @@ public:
Inst.insert(Inst.begin(), Inst.insert(Inst.begin(),
MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
Inst.insert(Inst.begin(), Inst.insert(Inst.begin(),
MCOperand::createExpr( // Displacement MCOperand::createExpr( // Displacement
MCSymbolRefExpr::create(TargetLocation, MCSymbolRefExpr::create(TargetLocation, *Ctx)));
MCSymbolRefExpr::VK_None, *Ctx)));
Inst.insert(Inst.begin(), Inst.insert(Inst.begin(),
MCOperand::createReg(X86::NoRegister)); // IndexReg MCOperand::createReg(X86::NoRegister)); // IndexReg
Inst.insert(Inst.begin(), Inst.insert(Inst.begin(),
@@ -2420,8 +2419,7 @@ public:
.addReg(RegNo) .addReg(RegNo)
.addImm(Imm)); .addImm(Imm));
Code.emplace_back(MCInstBuilder(X86::JCC_1) Code.emplace_back(MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create( .addExpr(MCSymbolRefExpr::create(Target, *Ctx))
Target, MCSymbolRefExpr::VK_None, *Ctx))
.addImm(X86::COND_E)); .addImm(X86::COND_E));
return Code; return Code;
} }
@@ -2432,8 +2430,7 @@ public:
InstructionListType Code; InstructionListType Code;
Code.emplace_back(MCInstBuilder(X86::CMP64ri8).addReg(RegNo).addImm(Imm)); Code.emplace_back(MCInstBuilder(X86::CMP64ri8).addReg(RegNo).addImm(Imm));
Code.emplace_back(MCInstBuilder(X86::JCC_1) Code.emplace_back(MCInstBuilder(X86::JCC_1)
.addExpr(MCSymbolRefExpr::create( .addExpr(MCSymbolRefExpr::create(Target, *Ctx))
Target, MCSymbolRefExpr::VK_None, *Ctx))
.addImm(X86::COND_NE)); .addImm(X86::COND_NE));
return Code; return Code;
} }
@@ -2738,24 +2735,23 @@ public:
Inst.clear(); Inst.clear();
Inst.setOpcode(X86::JMP_1); Inst.setOpcode(X86::JMP_1);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx)));
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)));
} }
void createLongUncondBranch(MCInst &Inst, const MCSymbol *Target, void createLongUncondBranch(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) const override { MCContext *Ctx) const override {
Inst.setOpcode(X86::JMP_4); Inst.setOpcode(X86::JMP_4);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); MCOperand::createExpr(MCSymbolRefExpr::create(Target, *Ctx)));
} }
void createCall(MCInst &Inst, const MCSymbol *Target, void createCall(MCInst &Inst, const MCSymbol *Target,
MCContext *Ctx) override { MCContext *Ctx) override {
Inst.setOpcode(X86::CALL64pcrel32); Inst.setOpcode(X86::CALL64pcrel32);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); MCOperand::createExpr(MCSymbolRefExpr::create(Target, *Ctx)));
} }
void createTailCall(MCInst &Inst, const MCSymbol *Target, void createTailCall(MCInst &Inst, const MCSymbol *Target,
@@ -2779,8 +2775,8 @@ public:
MCContext *Ctx) const override { MCContext *Ctx) const override {
Inst.setOpcode(X86::JCC_1); Inst.setOpcode(X86::JCC_1);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); MCOperand::createExpr(MCSymbolRefExpr::create(Target, *Ctx)));
Inst.addOperand(MCOperand::createImm(CC)); Inst.addOperand(MCOperand::createImm(CC));
} }
@@ -2788,8 +2784,8 @@ public:
MCContext *Ctx) const override { MCContext *Ctx) const override {
Inst.setOpcode(X86::JCC_4); Inst.setOpcode(X86::JCC_4);
Inst.clear(); Inst.clear();
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); MCOperand::createExpr(MCSymbolRefExpr::create(Target, *Ctx)));
Inst.addOperand(MCOperand::createImm(CC)); Inst.addOperand(MCOperand::createImm(CC));
} }
@@ -2798,8 +2794,8 @@ public:
unsigned InvCC = getInvertedCondCode(getCondCode(Inst)); unsigned InvCC = getInvertedCondCode(getCondCode(Inst));
assert(InvCC != X86::COND_INVALID && "invalid branch instruction"); assert(InvCC != X86::COND_INVALID && "invalid branch instruction");
Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC); Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC);
Inst.getOperand(0) = MCOperand::createExpr( Inst.getOperand(0) =
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
} }
bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB, MCContext *Ctx, bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB, MCContext *Ctx,
@@ -2807,8 +2803,8 @@ public:
if (CC == X86::COND_INVALID) if (CC == X86::COND_INVALID)
return false; return false;
Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(CC); Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(CC);
Inst.getOperand(0) = MCOperand::createExpr( Inst.getOperand(0) =
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
return true; return true;
} }
@@ -2846,8 +2842,8 @@ public:
MCContext *Ctx) const override { MCContext *Ctx) const override {
assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) && assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
"Invalid instruction"); "Invalid instruction");
Inst.getOperand(0) = MCOperand::createExpr( Inst.getOperand(0) =
MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
} }
MCPhysReg getX86R11() const override { return X86::R11; } MCPhysReg getX86R11() const override { return X86::R11; }
@@ -2894,8 +2890,8 @@ public:
bool IsTailCall) override { bool IsTailCall) override {
Inst.clear(); Inst.clear();
Inst.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); Inst.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32);
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); MCOperand::createExpr(MCSymbolRefExpr::create(Target, *Ctx)));
if (IsTailCall) if (IsTailCall)
setTailCall(Inst); setTailCall(Inst);
} }
@@ -2905,8 +2901,8 @@ public:
Seq.clear(); Seq.clear();
MCInst Inst; MCInst Inst;
Inst.setOpcode(X86::JMP_1); Inst.setOpcode(X86::JMP_1);
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); MCOperand::createExpr(MCSymbolRefExpr::create(Target, *Ctx)));
if (IsTailCall) if (IsTailCall)
setTailCall(Inst); setTailCall(Inst);
Seq.emplace_back(Inst); Seq.emplace_back(Inst);
@@ -3332,8 +3328,8 @@ public:
Target.addOperand(MCOperand::createReg(FuncAddrReg)); Target.addOperand(MCOperand::createReg(FuncAddrReg));
if (Targets[i].first) { if (Targets[i].first) {
// Is this OK? // Is this OK?
Target.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( Target.addOperand(MCOperand::createExpr(
Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); MCSymbolRefExpr::create(Targets[i].first, *Ctx)));
} else { } else {
const uint64_t Addr = Targets[i].second; const uint64_t Addr = Targets[i].second;
// Immediate address is out of sign extended 32 bit range. // Immediate address is out of sign extended 32 bit range.
@@ -3409,8 +3405,8 @@ public:
Je.clear(); Je.clear();
Je.setOpcode(X86::JCC_1); Je.setOpcode(X86::JCC_1);
if (Targets[i].first) if (Targets[i].first)
Je.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( Je.addOperand(MCOperand::createExpr(
Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); MCSymbolRefExpr::create(Targets[i].first, *Ctx)));
else else
Je.addOperand(MCOperand::createImm(Targets[i].second)); Je.addOperand(MCOperand::createImm(Targets[i].second));
@@ -3422,8 +3418,8 @@ public:
// Jump to next compare if target addresses don't match. // Jump to next compare if target addresses don't match.
Jne.clear(); Jne.clear();
Jne.setOpcode(X86::JCC_1); Jne.setOpcode(X86::JCC_1);
Jne.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( Jne.addOperand(
NextTarget, MCSymbolRefExpr::VK_None, *Ctx))); MCOperand::createExpr(MCSymbolRefExpr::create(NextTarget, *Ctx)));
Jne.addOperand(MCOperand::createImm(X86::COND_NE)); Jne.addOperand(MCOperand::createImm(X86::COND_NE));
// Call specific target directly. // Call specific target directly.
@@ -3442,8 +3438,8 @@ public:
CallOrJmp.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); CallOrJmp.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32);
if (Targets[i].first) if (Targets[i].first)
CallOrJmp.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( CallOrJmp.addOperand(MCOperand::createExpr(
Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); MCSymbolRefExpr::create(Targets[i].first, *Ctx)));
else else
CallOrJmp.addOperand(MCOperand::createImm(Targets[i].second)); CallOrJmp.addOperand(MCOperand::createImm(Targets[i].second));
} }
@@ -3545,8 +3541,8 @@ public:
// Jump to target if indices match // Jump to target if indices match
JEInst.setOpcode(X86::JCC_1); JEInst.setOpcode(X86::JCC_1);
JEInst.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( JEInst.addOperand(MCOperand::createExpr(
Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); MCSymbolRefExpr::create(Targets[i].first, *Ctx)));
JEInst.addOperand(MCOperand::createImm(X86::COND_E)); JEInst.addOperand(MCOperand::createImm(X86::COND_E));
} }
@@ -3571,9 +3567,9 @@ private:
Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg
Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, MCOperand::createExpr(MCSymbolRefExpr::create(Src,
*Ctx))); // Displacement *Ctx))); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
} }
@@ -3585,9 +3581,9 @@ private:
Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg
Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg
Inst.addOperand(MCOperand::createExpr( Inst.addOperand(
MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, MCOperand::createExpr(MCSymbolRefExpr::create(Src,
*Ctx))); // Displacement *Ctx))); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
} }
}; };