From 150e7b14f9474bc4d6891faaae4de6b8c5f6c797 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 11 Apr 2025 19:05:07 +0100
Subject: [PATCH] [X86] Add test coverage for #134602

---
 llvm/test/CodeGen/X86/pr134602.ll | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/pr134602.ll

diff --git a/llvm/test/CodeGen/X86/pr134602.ll b/llvm/test/CodeGen/X86/pr134602.ll
new file mode 100644
index 000000000000..e4376cbeab10
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr134602.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=X64
+
+; FIXME: incorrect vector codegen due to bad handling of splats of binops containing undefs
+define i32 @PR134602(i16 %a0) {
+; X86-LABEL: PR134602:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    orl $1, %eax
+; X86-NEXT:    addl $3, %eax
+; X86-NEXT:    cwtl
+; X86-NEXT:    retl
+;
+; X64-LABEL: PR134602:
+; X64:       # %bb.0:
+; X64-NEXT:    xorl %eax, %eax
+; X64-NEXT:    retq
+  %splat= insertelement <4 x i16> zeroinitializer, i16 %a0, i64 0
+  %mul = mul <4 x i16> %splat, <i16 1, i16 1, i16 0, i16 0>
+  %or = or <4 x i16> splat (i16 1), %mul
+  %reduce = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %or)
+  %ret_32 = sext i16 %reduce to i32
+  ret i32 %ret_32
+}