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[LSR] Add test cases showing bad handling of extends of post-inc uses.

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Tests from #38847, #62852.
This commit is contained in:
Florian Hahn
2023-06-15 10:15:12 +01:00
parent 05634f7346
commit 1665cb0630
1 changed files with 88 additions and 0 deletions
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llvm/test/Transforms/LoopStrengthReduce/postinc-iv-used-by-urem.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -loop-reduce -S %s | FileCheck %s
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx"
declare void @use(i64)
define i32 @test_pr38847() {
; CHECK-LABEL: define i32 @test_pr38847() {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 1, [[ENTRY:%.*]] ]
; CHECK-NEXT: call void @use(i64 [[LSR_IV]])
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -1
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[LSR_IV_NEXT]] to i8
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i8 [[TMP1]], -1
; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 [[LSR_IV_NEXT]], 9
; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4294967287
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[LSR_IV_NEXT]]
; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: ret i32 [[TMP]]
;
entry:
br label %loop
loop:
%iv = phi i8 [ 1, %entry ], [ %iv.next, %loop ]
%iv.next = add nsw i8 %iv, -1
%ext = zext i8 %iv to i64
call void @use(i64 %ext)
%cmp2 = icmp sgt i8 %iv.next, -1
br i1 %cmp2, label %loop, label %exit
exit:
%sext = sext i8 %iv.next to i32
%rem = urem i32 %sext, 9
ret i32 %rem
}
define i32 @test_pr62852() {
; CHECK-LABEL: define i32 @test_pr62852() {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[LSR_IV4:%.*]] = phi i64 [ [[LSR_IV_NEXT5:%.*]], [[LOOP]] ], [ -1, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[LOOP]] ], [ 1, [[ENTRY]] ]
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 2, [[ENTRY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV4]], 1
; CHECK-NEXT: call void @use(i64 [[TMP0]])
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -1
; CHECK-NEXT: [[TMP:%.*]] = trunc i64 [[LSR_IV_NEXT]] to i32
; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nsw i64 [[LSR_IV1]], -1
; CHECK-NEXT: [[LSR_IV_NEXT5]] = add nsw i64 [[LSR_IV4]], 1
; CHECK-NEXT: [[CMP6_1:%.*]] = icmp sgt i32 [[TMP]], 0
; CHECK-NEXT: br i1 [[CMP6_1]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: call void @use(i64 [[LSR_IV_NEXT]])
; CHECK-NEXT: call void @use(i64 [[LSR_IV_NEXT5]])
; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[LSR_IV_NEXT2]], 53
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4294967243
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], [[LSR_IV_NEXT]]
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], -1
; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP4]] to i32
; CHECK-NEXT: ret i32 [[TMP3]]
;
entry:
br label %loop
loop:
%iv.1 = phi i32 [ 1, %entry ], [ %dec.1, %loop ]
%iv.2 = phi i64 [ 0, %entry ], [ %inc.1, %loop ]
%inc.1 = add nsw i64 %iv.2, 1
%dec.1 = add nsw i32 %iv.1, -1
call void @use(i64 %iv.2)
%cmp6.1 = icmp sgt i32 %iv.1, 0
br i1 %cmp6.1, label %loop, label %exit
exit:
%iv.1.ext = zext i32 %iv.1 to i64
call void @use(i64 %iv.1.ext)
call void @use(i64 %iv.2)
%rem = urem i32 %dec.1, 53
ret i32 %rem
}