From 287d39dd5adbb3c6fd8a2c5007596ecdbe91eb38 Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Thu, 1 Jul 2021 13:07:28 +0100 Subject: [PATCH] [NFC] Fix a few whitespace issues and typos. --- llvm/include/llvm/Analysis/VecFuncs.def | 2 +- llvm/include/llvm/Analysis/VectorUtils.h | 2 +- llvm/include/llvm/CodeGen/MachineInstr.h | 3 -- llvm/include/llvm/IR/Intrinsics.td | 2 +- .../include/llvm/Target/TargetSelectionDAG.td | 1 - llvm/lib/Analysis/IVDescriptors.cpp | 1 + llvm/lib/Analysis/VectorUtils.cpp | 1 - llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 2 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 +- .../SelectionDAG/LegalizeVectorTypes.cpp | 1 + .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 ++- llvm/lib/CodeGen/StackSlotColoring.cpp | 2 +- llvm/lib/IR/Constants.cpp | 1 + llvm/lib/IR/Instructions.cpp | 1 + .../lib/Target/AArch64/AArch64FrameLowering.h | 2 +- .../Target/AArch64/AArch64ISelLowering.cpp | 3 +- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 2 +- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 42 +++++++++---------- llvm/lib/Target/AArch64/SVEInstrFormats.td | 36 ++++++++-------- .../InstCombine/InstCombineVectorOps.cpp | 2 + .../Vectorize/LoopVectorizationLegality.cpp | 5 ++- 21 files changed, 61 insertions(+), 59 deletions(-) diff --git a/llvm/include/llvm/Analysis/VecFuncs.def b/llvm/include/llvm/Analysis/VecFuncs.def index 2539ff0c9106..2e37e696fab3 100644 --- a/llvm/include/llvm/Analysis/VecFuncs.def +++ b/llvm/include/llvm/Analysis/VecFuncs.def @@ -22,7 +22,7 @@ #if !(defined(TLI_DEFINE_VECFUNC)) #define TLI_DEFINE_VECFUNC(SCAL, VEC, VF) {SCAL, VEC, VF}, -#endif +#endif #if defined(TLI_DEFINE_ACCELERATE_VECFUNCS) // Accelerate framework's Vector Functions diff --git a/llvm/include/llvm/Analysis/VectorUtils.h b/llvm/include/llvm/Analysis/VectorUtils.h index fc4203effcfd..437c9af9c438 100644 --- a/llvm/include/llvm/Analysis/VectorUtils.h +++ b/llvm/include/llvm/Analysis/VectorUtils.h @@ -31,7 +31,7 @@ enum class VFParamKind { OMP_LinearPos, // declare simd linear(i:c) uniform(c) OMP_LinearValPos, // declare simd linear(val(i:c)) uniform(c) OMP_LinearRefPos, // declare simd linear(ref(i:c)) uniform(c) - OMP_LinearUValPos, // declare simd linear(uval(i:c)) uniform(c + OMP_LinearUValPos, // declare simd linear(uval(i:c)) uniform(c) OMP_Uniform, // declare simd uniform(i) GlobalPredicate, // Global logical predicate that acts on all lanes // of the input and output mask concurrently. For diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 7fc1576fe5a0..42bf0af58958 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -1474,9 +1474,6 @@ public: /// /// If GroupNo is not NULL, it will receive the number of the operand group /// containing OpIdx. - /// - /// The flag operand is an immediate that can be decoded with methods like - /// InlineAsm::hasRegClassConstraint(). int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; /// Compute the static register class constraint for operand OpIdx. diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 975a10952635..7799321f2b16 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -216,7 +216,7 @@ class LLVMVectorOfAnyPointersToElt : LLVMMatchType; class LLVMVectorElementType : LLVMMatchType; // Match the type of another intrinsic parameter that is expected to be a -// vector type, but change the element count to be half as many +// vector type, but change the element count to be half as many. class LLVMHalfElementsVectorType : LLVMMatchType; // Match the type of another intrinsic parameter that is expected to be a diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td index c7f22bf17391..44ec2250a9c5 100644 --- a/llvm/include/llvm/Target/TargetSelectionDAG.td +++ b/llvm/include/llvm/Target/TargetSelectionDAG.td @@ -707,7 +707,6 @@ def assertsext : SDNode<"ISD::AssertSext", SDT_assert>; def assertzext : SDNode<"ISD::AssertZext", SDT_assert>; def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>; - //===----------------------------------------------------------------------===// // Selection DAG Condition Codes diff --git a/llvm/lib/Analysis/IVDescriptors.cpp b/llvm/lib/Analysis/IVDescriptors.cpp index 76bbfc5c0a0f..5edf9b85e460 100644 --- a/llvm/lib/Analysis/IVDescriptors.cpp +++ b/llvm/lib/Analysis/IVDescriptors.cpp @@ -646,6 +646,7 @@ bool RecurrenceDescriptor::hasMultipleUsesOf( return false; } + bool RecurrenceDescriptor::isReductionPHI(PHINode *Phi, Loop *TheLoop, RecurrenceDescriptor &RedDes, DemandedBits *DB, AssumptionCache *AC, diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index 884a9fa213cf..0a14a1432934 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -903,7 +903,6 @@ bool llvm::maskIsAllZeroOrUndef(Value *Mask) { return true; } - bool llvm::maskIsAllOneOrUndef(Value *Mask) { assert(isa(Mask->getType()) && isa(Mask->getType()->getScalarType()) && diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index d6ad64c9324f..ee14423ca3d0 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -1236,6 +1236,7 @@ void DwarfDebug::beginModule(Module *M) { if (!GVMapEntry.size() || (Expr && Expr->isConstant())) GVMapEntry.push_back({nullptr, Expr}); } + DenseSet Processed; for (auto *GVE : CUNode->getGlobalVariables()) { DIGlobalVariable *GV = GVE->getVariable(); @@ -1553,6 +1554,7 @@ void DwarfDebug::collectVariableInfoFromMFTable( RegVar->initializeMMI(VI.Expr, VI.Slot); LLVM_DEBUG(dbgs() << "Created DbgVariable for " << VI.Var->getName() << "\n"); + if (DbgVariable *DbgVar = MFVars.lookup(Var)) DbgVar->addMMIEntry(*RegVar); else if (InfoHolder.addScopeVariable(Scope, RegVar.get())) { diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index acf466f18dcd..0b2e6e11c329 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3549,7 +3549,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) { } } - // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C)) + // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C)) if (N1.getOpcode() == ISD::VSCALE) { const APInt &IntVal = N1.getConstantOperandAPInt(0); return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal)); @@ -12031,6 +12031,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { AddToWorklist(ExtLoad.getNode()); return SDValue(N, 0); // Return N so it doesn't get rechecked! } + // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse() && diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index c018cfd0a2ea..f286bc9067b7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -2854,6 +2854,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) { HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); } + // Concatenate them to get the full intermediate truncation result. EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements); SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo, diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index a6f2f7ad33ca..359140f9091f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1769,7 +1769,7 @@ static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef M) { SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef Mask) { assert(VT.getVectorNumElements() == Mask.size() && - "Must have the same number of vector elements as mask elements!"); + "Must have the same number of vector elements as mask elements!"); assert(VT == N1.getValueType() && VT == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); @@ -5693,6 +5693,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, const APInt &Val = N1C->getAPIntValue(); return SignExtendInReg(Val, VT); } + if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) { SmallVector Ops; llvm::EVT OpVT = N1.getOperand(0).getValueType(); @@ -5830,7 +5831,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, return getConstant(Val.extractBits(ElementSize, Shift), DL, VT); } break; - case ISD::EXTRACT_SUBVECTOR: + case ISD::EXTRACT_SUBVECTOR: { EVT N1VT = N1.getValueType(); assert(VT.isVector() && N1VT.isVector() && "Extract subvector VTs must be vectors!"); @@ -5873,6 +5874,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, return N1.getOperand(1); break; } + } // Perform trivial constant folding. if (SDValue SV = FoldConstantArithmetic(Opcode, DL, VT, {N1, N2})) diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp index bd5653f63a61..ebe00bd7402f 100644 --- a/llvm/lib/CodeGen/StackSlotColoring.cpp +++ b/llvm/lib/CodeGen/StackSlotColoring.cpp @@ -76,7 +76,7 @@ namespace { // OrigAlignments - Alignments of stack objects before coloring. SmallVector OrigAlignments; - // OrigSizes - Sizess of stack objects before coloring. + // OrigSizes - Sizes of stack objects before coloring. SmallVector OrigSizes; // AllColors - If index is set, it's a spill slot, i.e. color. diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp index bc197b98b327..791c684d3bb6 100644 --- a/llvm/lib/IR/Constants.cpp +++ b/llvm/lib/IR/Constants.cpp @@ -442,6 +442,7 @@ Constant *Constant::getAggregateElement(unsigned Elt) const { if (const auto *CDS = dyn_cast(this)) return Elt < CDS->getNumElements() ? CDS->getElementAsConstant(Elt) : nullptr; + return nullptr; } diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index 2a41fde8666e..68df26932a69 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -2092,6 +2092,7 @@ void ShuffleVectorInst::setShuffleMask(ArrayRef Mask) { ShuffleMask.assign(Mask.begin(), Mask.end()); ShuffleMaskForBitcode = convertShuffleMaskForBitcode(Mask, getType()); } + Constant *ShuffleVectorInst::convertShuffleMaskForBitcode(ArrayRef Mask, Type *ResultTy) { Type *Int32Ty = Type::getInt32Ty(ResultTy->getContext()); diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.h b/llvm/lib/Target/AArch64/AArch64FrameLowering.h index 88acc9602301..f8adaf36db84 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.h +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.h @@ -87,7 +87,7 @@ public: TargetStackID::Value getStackIDForScalableVectors() const override; void processFunctionBeforeFrameFinalized(MachineFunction &MF, - RegScavenger *RS) const override; + RegScavenger *RS) const override; void processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF, diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index dc4565924d3b..4315dacd9334 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -5158,7 +5158,6 @@ SDValue AArch64TargetLowering::LowerFormalArguments( ExtType, DL, VA.getLocVT(), Chain, FIN, MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), MemVT); - } if (VA.getLocInfo() == CCValAssign::Indirect) { @@ -12528,6 +12527,7 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG, // e.g. 6=3*2=(2+1)*2. // TODO: consider lowering more cases, e.g. C = 14, -6, -14 or even 45 // which equals to (1+2)*16-(1+2). + // TrailingZeroes is used to test if the mul can be lowered to // shift+add+shift. unsigned TrailingZeroes = ConstValue.countTrailingZeros(); @@ -15952,7 +15952,6 @@ static SDValue getScaledOffsetForBitWidth(SelectionDAG &DAG, SDValue Offset, /// [.[S|D]{, #}] /// /// where = sizeof() * k, for k = 0, 1, ..., 31. - inline static bool isValidImmForSVEVecImmAddrMode(unsigned OffsetInBytes, unsigned ScalarSizeInBytes) { // The immediate is not a multiple of the scalar size. diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index dd22e64ab713..406cfb03d584 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -455,7 +455,7 @@ unsigned getBLRCallOpcode(const MachineFunction &MF); // struct TSFlags { #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits -#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bit +#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bits #define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits #define TSFLAG_INSTR_FLAGS(X) ((X) << 9) // 2-bits // } diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 7e7ac6ddcc3e..ff32e3dcf743 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -209,8 +209,8 @@ def AArch64clz_mt : SDNode<"AArch64ISD::CTLZ_MERGE_PASSTHRU", SDT_AArch64Arit def AArch64cnt_mt : SDNode<"AArch64ISD::CTPOP_MERGE_PASSTHRU", SDT_AArch64Arith>; def AArch64fneg_mt : SDNode<"AArch64ISD::FNEG_MERGE_PASSTHRU", SDT_AArch64Arith>; def AArch64fabs_mt : SDNode<"AArch64ISD::FABS_MERGE_PASSTHRU", SDT_AArch64Arith>; -def AArch64abs_mt : SDNode<"AArch64ISD::ABS_MERGE_PASSTHRU", SDT_AArch64Arith>; -def AArch64neg_mt : SDNode<"AArch64ISD::NEG_MERGE_PASSTHRU", SDT_AArch64Arith>; +def AArch64abs_mt : SDNode<"AArch64ISD::ABS_MERGE_PASSTHRU", SDT_AArch64Arith>; +def AArch64neg_mt : SDNode<"AArch64ISD::NEG_MERGE_PASSTHRU", SDT_AArch64Arith>; def AArch64sxt_mt : SDNode<"AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU", SDT_AArch64IntExtend>; def AArch64uxt_mt : SDNode<"AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU", SDT_AArch64IntExtend>; def AArch64frintp_mt : SDNode<"AArch64ISD::FCEIL_MERGE_PASSTHRU", SDT_AArch64Arith>; @@ -337,9 +337,9 @@ let Predicates = [HasSVE] in { defm UMAXV_VPZ : sve_int_reduce_1<0b001, "umaxv", AArch64umaxv_p>; defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv", AArch64sminv_p>; defm UMINV_VPZ : sve_int_reduce_1<0b011, "uminv", AArch64uminv_p>; - defm ORV_VPZ : sve_int_reduce_2<0b000, "orv", AArch64orv_p>; - defm EORV_VPZ : sve_int_reduce_2<0b001, "eorv", AArch64eorv_p>; - defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv", AArch64andv_p>; + defm ORV_VPZ : sve_int_reduce_2<0b000, "orv", AArch64orv_p>; + defm EORV_VPZ : sve_int_reduce_2<0b001, "eorv", AArch64eorv_p>; + defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv", AArch64andv_p>; defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn", or>; defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon", xor>; @@ -398,10 +398,10 @@ let Predicates = [HasSVE] in { defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd", "SABD_ZPZZ", int_aarch64_sve_sabd, DestructiveBinaryComm>; defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd", "UABD_ZPZZ", int_aarch64_sve_uabd, DestructiveBinaryComm>; - defm SMAX_ZPZZ : sve_int_bin_pred_bhsd; - defm UMAX_ZPZZ : sve_int_bin_pred_bhsd; - defm SMIN_ZPZZ : sve_int_bin_pred_bhsd; - defm UMIN_ZPZZ : sve_int_bin_pred_bhsd; + defm SMAX_ZPZZ : sve_int_bin_pred_bhsd; + defm UMAX_ZPZZ : sve_int_bin_pred_bhsd; + defm SMIN_ZPZZ : sve_int_bin_pred_bhsd; + defm UMIN_ZPZZ : sve_int_bin_pred_bhsd; defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe", int_aarch64_sve_frecpe_x>; defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte", int_aarch64_sve_frsqrte_x>; @@ -534,8 +534,8 @@ let Predicates = [HasSVE] in { defm FMINV_VPZ : sve_fp_fast_red<0b111, "fminv", AArch64fminv_p>; // Splat immediate (unpredicated) - defm DUP_ZI : sve_int_dup_imm<"dup">; - defm FDUP_ZI : sve_int_dup_fpimm<"fdup">; + defm DUP_ZI : sve_int_dup_imm<"dup">; + defm FDUP_ZI : sve_int_dup_fpimm<"fdup">; defm DUPM_ZI : sve_int_dup_mask_imm<"dupm">; // Splat immediate (predicated) @@ -969,7 +969,7 @@ let Predicates = [HasSVE] in { // st1h z0.d, p0, [x0, z0.d, uxtw] defm SST1B_D : sve_mem_64b_sst_sv_32_unscaled<0b000, "st1b", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only, nxv2i8>; defm SST1H_D : sve_mem_64b_sst_sv_32_unscaled<0b010, "st1h", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8, nxv2i16>; - defm SST1W_D : sve_mem_64b_sst_sv_32_unscaled<0b100, "st1w", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8,nxv2i32>; + defm SST1W_D : sve_mem_64b_sst_sv_32_unscaled<0b100, "st1w", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8, nxv2i32>; defm SST1D : sve_mem_64b_sst_sv_32_unscaled<0b110, "st1d", AArch64st1_scatter_sxtw, AArch64st1_scatter_uxtw, ZPR64ExtSXTW8, ZPR64ExtUXTW8, nxv2i64>; // Scatters using packed, unscaled 32-bit offsets, e.g. @@ -1402,10 +1402,10 @@ let Predicates = [HasSVE] in { defm LSL_ZPZI : sve_int_shift_pred_bhsd; let Predicates = [HasSVE, UseExperimentalZeroingPseudos] in { - defm ASR_ZPZZ : sve_int_bin_pred_zeroing_bhsd; - defm LSR_ZPZZ : sve_int_bin_pred_zeroing_bhsd; - defm LSL_ZPZZ : sve_int_bin_pred_zeroing_bhsd; - defm ASRD_ZPZI : sve_int_bin_pred_shift_imm_right_zeroing_bhsd; + defm ASR_ZPZZ : sve_int_bin_pred_zeroing_bhsd; + defm LSR_ZPZZ : sve_int_bin_pred_zeroing_bhsd; + defm LSL_ZPZZ : sve_int_bin_pred_zeroing_bhsd; + defm ASRD_ZPZI : sve_int_bin_pred_shift_imm_right_zeroing_bhsd; } defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr", "ASR_ZPZZ", int_aarch64_sve_asr, "ASRR_ZPmZ">; @@ -1415,9 +1415,9 @@ let Predicates = [HasSVE] in { defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr", "LSRR_ZPZZ", null_frag, "LSR_ZPmZ", /*isReverseInstr*/ 1>; defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr", "LSLR_ZPZZ", null_frag, "LSL_ZPmZ", /*isReverseInstr*/ 1>; - defm ASR_ZPZZ : sve_int_bin_pred_bhsd; - defm LSR_ZPZZ : sve_int_bin_pred_bhsd; - defm LSL_ZPZZ : sve_int_bin_pred_bhsd; + defm ASR_ZPZZ : sve_int_bin_pred_bhsd; + defm LSR_ZPZZ : sve_int_bin_pred_bhsd; + defm LSL_ZPZZ : sve_int_bin_pred_bhsd; defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr", int_aarch64_sve_asr_wide>; defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr", int_aarch64_sve_lsr_wide>; @@ -1798,12 +1798,10 @@ let Predicates = [HasSVE] in { // Add more complex addressing modes here as required multiclass pred_load { - // reg + reg let AddedComplexity = 1 in { def _reg_reg_z : Pat<(Ty (Load (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp), (SVEDup0Undef))), (RegRegInst PPR:$gp, GPR64:$base, GPR64:$offset)>; } - // reg + imm let AddedComplexity = 2 in { def _reg_imm_z : Pat<(Ty (Load (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), (PredTy PPR:$gp), (SVEDup0Undef))), (RegImmInst PPR:$gp, GPR64:$base, simm4s1:$offset)>; @@ -1845,12 +1843,10 @@ let Predicates = [HasSVE] in { multiclass pred_store { - // reg + reg let AddedComplexity = 1 in { def _reg_reg : Pat<(Store (Ty ZPR:$vec), (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp)), (RegRegInst ZPR:$vec, PPR:$gp, GPR64:$base, GPR64:$offset)>; } - // reg + imm let AddedComplexity = 2 in { def _reg_imm : Pat<(Store (Ty ZPR:$vec), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), (PredTy PPR:$gp)), (RegImmInst ZPR:$vec, PPR:$gp, GPR64:$base, simm4s1:$offset)>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 02ac788b16e5..f60f6cacf2c3 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -2544,13 +2544,13 @@ multiclass sve_int_bin_pred_arit_0 opc, string asm, string Ps, string revname="", bit isReverseInstr=0> { let DestructiveInstType = flags in { def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; } def : SVE_3_Op_Pat(NAME # _B)>; @@ -2564,13 +2564,13 @@ multiclass sve_int_bin_pred_arit_1 opc, string asm, string Ps, DestructiveInstTypeEnum flags> { let DestructiveInstType = flags in { def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>, - SVEPseudo2Instr; + SVEPseudo2Instr; def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>, - SVEPseudo2Instr; + SVEPseudo2Instr; def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>, - SVEPseudo2Instr; + SVEPseudo2Instr; def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>, - SVEPseudo2Instr; + SVEPseudo2Instr; } def : SVE_3_Op_Pat(NAME # _B)>; @@ -2584,13 +2584,13 @@ multiclass sve_int_bin_pred_arit_2 opc, string asm, string Ps, DestructiveInstTypeEnum flags> { let DestructiveInstType = flags in { def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>, - SVEPseudo2Instr; + SVEPseudo2Instr; def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>, - SVEPseudo2Instr; + SVEPseudo2Instr; def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>, - SVEPseudo2Instr; + SVEPseudo2Instr; def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>, - SVEPseudo2Instr; + SVEPseudo2Instr; } def : SVE_3_Op_Pat(NAME # _B)>; @@ -2606,9 +2606,9 @@ multiclass sve_int_bin_pred_arit_2_div opc, string asm, string Ps, string revname="", bit isReverseInstr=0> { let DestructiveInstType = flags in { def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; } def : SVE_3_Op_Pat(NAME # _S)>; @@ -3179,13 +3179,13 @@ multiclass sve2_int_arith_pred opc, string asm, SDPatternOperator op, string revname="", bit isReverseInstr=0> { let DestructiveInstType = flags in { def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; } def : SVE_3_Op_Pat(NAME # _B)>; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp index c207f079bfce..32b15376f898 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -365,6 +365,7 @@ Instruction *InstCombinerImpl::visitExtractElementInst(ExtractElementInst &EI) { return replaceInstUsesWith(EI, Idx); } } + // InstSimplify should handle cases where the index is invalid. // For fixed-length vector, it's invalid to extract out-of-range element. if (!EC.isScalable() && IndexC->getValue().uge(NumElts)) @@ -400,6 +401,7 @@ Instruction *InstCombinerImpl::visitExtractElementInst(ExtractElementInst &EI) { } } } + if (Instruction *I = foldBitcastExtElt(EI, Builder, DL.isBigEndian())) return I; diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp index e97620e9fb0a..722b16a32b81 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp @@ -586,7 +586,7 @@ bool LoopVectorizationLegality::setupOuterLoopInductions() { /// Checks if a function is scalarizable according to the TLI, in /// the sense that it should be vectorized and then expanded in -/// multiple scalarcalls. This is represented in the +/// multiple scalar calls. This is represented in the /// TLI via mappings that do not specify a vector name, as in the /// following example: /// @@ -885,6 +885,7 @@ bool LoopVectorizationLegality::canVectorizeMemory() { "loop not vectorized: ", *LAR); }); } + if (!LAI->canVectorizeMemory()) return false; @@ -894,9 +895,9 @@ bool LoopVectorizationLegality::canVectorizeMemory() { "CantVectorizeStoreToLoopInvariantAddress", ORE, TheLoop); return false; } + Requirements->addRuntimePointerChecks(LAI->getNumRuntimePointerChecks()); PSE.addPredicate(LAI->getPSE().getUnionPredicate()); - return true; }