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[mlir][VectorOps] Loosen restrictions on vector.reduction types

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LLVM can deal with any integer or float type, don't arbitrarily restrict
it to f32/f64/i32/i64.

Differential Revision: https://reviews.llvm.org/D88010
This commit is contained in:
Benjamin Kramer
2020-09-21 12:04:33 +02:00
parent f4c5cadbcb
commit 2d76274b99
3 changed files with 25 additions and 6 deletions
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4
mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
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@@ -561,7 +561,7 @@ public:
auto kind = reductionOp.kind();
Type eltType = reductionOp.dest().getType();
Type llvmType = typeConverter.convertType(eltType);
if (eltType.isSignlessInteger(32) || eltType.isSignlessInteger(64)) {
if (eltType.isSignlessInteger()) {
// Integer reductions: add/mul/min/max/and/or/xor.
if (kind == "add")
rewriter.replaceOpWithNewOp<LLVM::experimental_vector_reduce_add>(
@@ -588,7 +588,7 @@ public:
return failure();
return success();
} else if (eltType.isF32() || eltType.isF64()) {
} else if (eltType.isa<FloatType>()) {
// Floating-point reductions: add/mul/min/max
if (kind == "add") {
// Optional accumulator (or zero).