[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
Add a prologue to the kernel entry to handle cases where code designed for kernarg preloading is executed on hardware equipped with incompatible firmware. If hardware has compatible firmware the 256 bytes at the start of the kernel entry will be skipped. This skipping is done automatically by hardware that supports the feature. A pass is added which is intended to be run at the very end of the pipeline to avoid any optimizations that would assume the prologue is a real predecessor block to the actual code start. In reality we have two possible entry points for the function. 1. The optimized path that supports kernarg preloading which begins at an offset of 256 bytes. 2. The backwards compatible entry point which starts at offset 0.
This commit is contained in:
Austin Kerbow
@@ -5914,10 +5914,7 @@ additional 256 bytes to the kernel_code_entry_byte_offset. This addition
|
||||
facilitates the incorporation of a prologue to the kernel entry to handle cases
|
||||
where code designed for kernarg preloading is executed on hardware equipped with
|
||||
incompatible firmware. If hardware has compatible firmware the 256 bytes at the
|
||||
start of the kernel entry will be skipped. Additionally, the compiler backend
|
||||
may insert a trap instruction at the start of the kernel prologue to manage
|
||||
situations where kernarg preloading is attempted on hardware with incompatible
|
||||
firmware.
|
||||
start of the kernel entry will be skipped.
|
||||
|
||||
With code object V5 and later, hidden kernel arguments that are normally
|
||||
accessed through the Implicit Argument Ptr, may be preloaded into User SGPRs.
|
||||
|
||||
@@ -64,6 +64,7 @@ createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
|
||||
ModulePass *createAMDGPULowerBufferFatPointersPass();
|
||||
FunctionPass *createSIModeRegisterPass();
|
||||
FunctionPass *createGCNPreRAOptimizationsPass();
|
||||
FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
|
||||
|
||||
struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
|
||||
AMDGPUSimplifyLibCallsPass() {}
|
||||
@@ -230,6 +231,9 @@ extern char &AMDGPUPerfHintAnalysisLegacyID;
|
||||
void initializeGCNRegPressurePrinterPass(PassRegistry &);
|
||||
extern char &GCNRegPressurePrinterID;
|
||||
|
||||
void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
|
||||
extern char &AMDGPUPreloadKernArgPrologLegacyID;
|
||||
|
||||
// Passes common to R600 and SI
|
||||
FunctionPass *createAMDGPUPromoteAlloca();
|
||||
void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
|
||||
|
||||
@@ -9,6 +9,7 @@
|
||||
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
|
||||
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
|
||||
|
||||
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/CodeGen/Register.h"
|
||||
#include "llvm/Pass.h"
|
||||
@@ -161,6 +162,8 @@ struct AMDGPUFunctionArgInfo {
|
||||
|
||||
// Map the index of preloaded kernel arguments to its descriptor.
|
||||
SmallDenseMap<int, KernArgPreloadDescriptor> PreloadKernArgs{};
|
||||
// The first user SGPR allocated for kernarg preloading.
|
||||
Register FirstKernArgPreloadReg;
|
||||
|
||||
std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
|
||||
getPreloadedValue(PreloadedValue Value) const;
|
||||
|
||||
@@ -207,12 +207,6 @@ void AMDGPUAsmPrinter::emitFunctionBodyStart() {
|
||||
|
||||
if (STM.isAmdHsaOS())
|
||||
HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
|
||||
|
||||
if (MFI.getNumKernargPreloadedSGPRs() > 0) {
|
||||
assert(AMDGPU::hasKernargPreload(STM));
|
||||
getTargetStreamer()->EmitKernargPreloadHeader(*getGlobalSTI(),
|
||||
STM.isAmdHsaOS());
|
||||
}
|
||||
}
|
||||
|
||||
void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
|
||||
|
||||
211
llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
Normal file
211
llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
Normal file
@@ -0,0 +1,211 @@
|
||||
//===- AMDGPUPreloadKernArgProlog.cpp - Preload KernArg Prolog ------------===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
/// \file This pass creates a backward compatibility layer for kernel argument
|
||||
/// preloading in situations where code is compiled with kernel argument
|
||||
/// preloading enabled but executed on hardware without firmware support for it.
|
||||
///
|
||||
/// To avoid recompilation, the pass inserts a block at the beginning of the
|
||||
/// program that loads the kernel arguments into SGPRs using s_load
|
||||
/// instructions. This sets up the registers exactly as they would be on systems
|
||||
/// with compatible firmware.
|
||||
///
|
||||
/// This effectively creates two entry points for the kernel. Firmware that
|
||||
/// supports the feature will automatically jump past the first 256 bytes of the
|
||||
/// program, skipping the compatibility layer and directly starting execution on
|
||||
/// the optimized code path.
|
||||
///
|
||||
/// This pass should be run as late as possible to prevent any optimizations
|
||||
/// that might assume the padding is dead code or that the added prologue is a
|
||||
/// true predecessor of the kernel entry block.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "AMDGPUPreloadKernArgProlog.h"
|
||||
#include "AMDGPU.h"
|
||||
#include "GCNSubtarget.h"
|
||||
#include "SIMachineFunctionInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/TargetParser/TargetParser.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "amdgpu-preload-kern-arg-prolog"
|
||||
|
||||
namespace {
|
||||
|
||||
// Used to build s_loads maping user SGPRs to kernel arguments
|
||||
struct LoadConfig {
|
||||
unsigned Size;
|
||||
const TargetRegisterClass *RegClass;
|
||||
unsigned Opcode;
|
||||
Register LoadReg = Register();
|
||||
};
|
||||
|
||||
class AMDGPUPreloadKernArgProlog {
|
||||
public:
|
||||
AMDGPUPreloadKernArgProlog(MachineFunction &MF);
|
||||
|
||||
bool run();
|
||||
|
||||
private:
|
||||
MachineFunction &MF;
|
||||
const GCNSubtarget &ST;
|
||||
const SIMachineFunctionInfo &MFI;
|
||||
const SIInstrInfo &TII;
|
||||
const TargetRegisterInfo &TRI;
|
||||
|
||||
// Create a new block before the entry point to the kernel. Firmware that
|
||||
// supports preloading kernel arguments will automatically jump past this
|
||||
// block to the alternative kernel entry point.
|
||||
void createBackCompatBlock(unsigned NumKernArgPreloadSGPRs);
|
||||
|
||||
// Add instructions to load kernel arguments into SGPRs.
|
||||
void addBackCompatLoads(MachineBasicBlock *BackCompatMBB,
|
||||
Register KernArgSegmentPtr,
|
||||
unsigned NumKernArgPreloadSGPRs);
|
||||
};
|
||||
|
||||
class AMDGPUPreloadKernArgPrologLegacy : public MachineFunctionPass {
|
||||
public:
|
||||
static char ID;
|
||||
|
||||
AMDGPUPreloadKernArgPrologLegacy() : MachineFunctionPass(ID) {}
|
||||
|
||||
StringRef getPassName() const override {
|
||||
return "AMDGPU Preload Kernel Arguments Prolog";
|
||||
}
|
||||
|
||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||
};
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char AMDGPUPreloadKernArgPrologLegacy::ID = 0;
|
||||
|
||||
INITIALIZE_PASS(AMDGPUPreloadKernArgPrologLegacy, DEBUG_TYPE,
|
||||
"AMDGPU Preload Kernel Arguments Prolog", false, false)
|
||||
|
||||
char &llvm::AMDGPUPreloadKernArgPrologLegacyID =
|
||||
AMDGPUPreloadKernArgPrologLegacy::ID;
|
||||
|
||||
FunctionPass *llvm::createAMDGPUPreloadKernArgPrologLegacyPass() {
|
||||
return new AMDGPUPreloadKernArgPrologLegacy();
|
||||
}
|
||||
|
||||
bool AMDGPUPreloadKernArgPrologLegacy::runOnMachineFunction(
|
||||
MachineFunction &MF) {
|
||||
return AMDGPUPreloadKernArgProlog(MF).run();
|
||||
}
|
||||
|
||||
AMDGPUPreloadKernArgProlog::AMDGPUPreloadKernArgProlog(MachineFunction &MF)
|
||||
: MF(MF), ST(MF.getSubtarget<GCNSubtarget>()),
|
||||
MFI(*MF.getInfo<SIMachineFunctionInfo>()), TII(*ST.getInstrInfo()),
|
||||
TRI(*ST.getRegisterInfo()) {}
|
||||
|
||||
bool AMDGPUPreloadKernArgProlog::run() {
|
||||
if (!ST.hasKernargPreload())
|
||||
return false;
|
||||
|
||||
unsigned NumKernArgPreloadSGPRs = MFI.getNumKernargPreloadedSGPRs();
|
||||
if (!NumKernArgPreloadSGPRs)
|
||||
return false;
|
||||
|
||||
createBackCompatBlock(NumKernArgPreloadSGPRs);
|
||||
return true;
|
||||
}
|
||||
|
||||
void AMDGPUPreloadKernArgProlog::createBackCompatBlock(
|
||||
unsigned NumKernArgPreloadSGPRs) {
|
||||
auto KernelEntryMBB = MF.begin();
|
||||
MachineBasicBlock *BackCompatMBB = MF.CreateMachineBasicBlock();
|
||||
MF.insert(KernelEntryMBB, BackCompatMBB);
|
||||
|
||||
assert(MFI.getUserSGPRInfo().hasKernargSegmentPtr() &&
|
||||
"Kernel argument segment pointer register not set.");
|
||||
Register KernArgSegmentPtr = MFI.getArgInfo().KernargSegmentPtr.getRegister();
|
||||
BackCompatMBB->addLiveIn(KernArgSegmentPtr);
|
||||
|
||||
// Load kernel arguments to SGPRs
|
||||
addBackCompatLoads(BackCompatMBB, KernArgSegmentPtr, NumKernArgPreloadSGPRs);
|
||||
|
||||
// Wait for loads to complete
|
||||
AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST.getCPU());
|
||||
unsigned Waitcnt =
|
||||
AMDGPU::encodeWaitcnt(IV, getVmcntBitMask(IV), getExpcntBitMask(IV), 0);
|
||||
BuildMI(BackCompatMBB, DebugLoc(), TII.get(AMDGPU::S_WAITCNT))
|
||||
.addImm(Waitcnt);
|
||||
|
||||
// Branch to kernel start
|
||||
BuildMI(BackCompatMBB, DebugLoc(), TII.get(AMDGPU::S_BRANCH))
|
||||
.addMBB(&*KernelEntryMBB);
|
||||
BackCompatMBB->addSuccessor(&*KernelEntryMBB);
|
||||
|
||||
// Create a new basic block for padding to 256 bytes
|
||||
MachineBasicBlock *PadMBB = MF.CreateMachineBasicBlock();
|
||||
MF.insert(++BackCompatMBB->getIterator(), PadMBB);
|
||||
PadMBB->setAlignment(Align(256));
|
||||
PadMBB->addSuccessor(&*KernelEntryMBB);
|
||||
}
|
||||
|
||||
/// Find the largest possible load size that fits with SGPR alignment
|
||||
static LoadConfig getLoadParameters(const TargetRegisterInfo &TRI,
|
||||
Register KernArgPreloadSGPR,
|
||||
unsigned NumKernArgPreloadSGPRs) {
|
||||
static constexpr LoadConfig Configs[] = {
|
||||
{8, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM},
|
||||
{4, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM},
|
||||
{2, &AMDGPU::SReg_64RegClass, AMDGPU::S_LOAD_DWORDX2_IMM}};
|
||||
|
||||
for (const auto &Config : Configs) {
|
||||
if (NumKernArgPreloadSGPRs >= Config.Size) {
|
||||
Register LoadReg = TRI.getMatchingSuperReg(KernArgPreloadSGPR,
|
||||
AMDGPU::sub0, Config.RegClass);
|
||||
if (LoadReg) {
|
||||
LoadConfig C(Config);
|
||||
C.LoadReg = LoadReg;
|
||||
return C;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Fallback to a single register
|
||||
return LoadConfig{1, &AMDGPU::SReg_32RegClass, AMDGPU::S_LOAD_DWORD_IMM,
|
||||
KernArgPreloadSGPR};
|
||||
}
|
||||
|
||||
void AMDGPUPreloadKernArgProlog::addBackCompatLoads(
|
||||
MachineBasicBlock *BackCompatMBB, Register KernArgSegmentPtr,
|
||||
unsigned NumKernArgPreloadSGPRs) {
|
||||
Register KernArgPreloadSGPR = MFI.getArgInfo().FirstKernArgPreloadReg;
|
||||
unsigned Offset = 0;
|
||||
// Fill all user SGPRs used for kernarg preloading with sequential data from
|
||||
// the kernarg segment
|
||||
while (NumKernArgPreloadSGPRs > 0) {
|
||||
LoadConfig Config =
|
||||
getLoadParameters(TRI, KernArgPreloadSGPR, NumKernArgPreloadSGPRs);
|
||||
|
||||
BuildMI(BackCompatMBB, DebugLoc(), TII.get(Config.Opcode), Config.LoadReg)
|
||||
.addReg(KernArgSegmentPtr)
|
||||
.addImm(Offset)
|
||||
.addImm(0);
|
||||
|
||||
Offset += 4 * Config.Size;
|
||||
KernArgPreloadSGPR = KernArgPreloadSGPR.asMCReg() + Config.Size;
|
||||
NumKernArgPreloadSGPRs -= Config.Size;
|
||||
}
|
||||
}
|
||||
|
||||
PreservedAnalyses
|
||||
AMDGPUPreloadKernArgPrologPass::run(MachineFunction &MF,
|
||||
MachineFunctionAnalysisManager &) {
|
||||
if (!AMDGPUPreloadKernArgProlog(MF).run())
|
||||
return PreservedAnalyses::all();
|
||||
|
||||
return PreservedAnalyses::none();
|
||||
}
|
||||
25
llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.h
Normal file
25
llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.h
Normal file
@@ -0,0 +1,25 @@
|
||||
//===- AMDGPUPreloadKernargProlog.h ----------------------------*- C++ -*-===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_AMDGPU_PRELOAD_KERNARG_PROLOG_H
|
||||
#define LLVM_LIB_TARGET_AMDGPU_PRELOAD_KERNARG_PROLOG_H
|
||||
|
||||
#include "llvm/CodeGen/MachinePassManager.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class AMDGPUPreloadKernArgPrologPass
|
||||
: public PassInfoMixin<AMDGPUPreloadKernArgPrologPass> {
|
||||
public:
|
||||
PreservedAnalyses run(MachineFunction &MF,
|
||||
MachineFunctionAnalysisManager &AM);
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif // LLVM_LIB_TARGET_AMDGPU_PRELOAD_KERNARG_PROLOG_H
|
||||
@@ -540,6 +540,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
|
||||
initializeGCNPreRALongBranchRegPass(*PR);
|
||||
initializeGCNRewritePartialRegUsesPass(*PR);
|
||||
initializeGCNRegPressurePrinterPass(*PR);
|
||||
initializeAMDGPUPreloadKernArgPrologLegacyPass(*PR);
|
||||
}
|
||||
|
||||
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
|
||||
@@ -1669,6 +1670,7 @@ void GCNPassConfig::addPreEmitPass() {
|
||||
addPass(&AMDGPUInsertDelayAluID);
|
||||
|
||||
addPass(&BranchRelaxationPassID);
|
||||
addPass(createAMDGPUPreloadKernArgPrologLegacyPass());
|
||||
}
|
||||
|
||||
TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
|
||||
|
||||
@@ -88,6 +88,7 @@ add_llvm_target(AMDGPUCodeGen
|
||||
AMDGPUPerfHintAnalysis.cpp
|
||||
AMDGPUPostLegalizerCombiner.cpp
|
||||
AMDGPUPreLegalizerCombiner.cpp
|
||||
AMDGPUPreloadKernArgProlog.cpp
|
||||
AMDGPUPrintfRuntimeBinding.cpp
|
||||
AMDGPUPromoteAlloca.cpp
|
||||
AMDGPUPromoteKernelArguments.cpp
|
||||
|
||||
@@ -338,15 +338,6 @@ bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AMDGPUTargetAsmStreamer::EmitKernargPreloadHeader(
|
||||
const MCSubtargetInfo &STI, bool TrapEnabled) {
|
||||
OS << (TrapEnabled ? "\ts_trap 2" : "\ts_endpgm")
|
||||
<< " ; Kernarg preload header. Trap with incompatible firmware that "
|
||||
"doesn't support preloading kernel arguments.\n";
|
||||
OS << "\t.fill 63, 4, 0xbf800000 ; s_nop 0\n";
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
|
||||
const uint32_t Encoded_s_code_end = 0xbf9f0000;
|
||||
const uint32_t Encoded_s_nop = 0xbf800000;
|
||||
@@ -935,20 +926,6 @@ bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AMDGPUTargetELFStreamer::EmitKernargPreloadHeader(
|
||||
const MCSubtargetInfo &STI, bool TrapEnabled) {
|
||||
const uint32_t Encoded_s_nop = 0xbf800000;
|
||||
const uint32_t Encoded_s_trap = 0xbf920002;
|
||||
const uint32_t Encoded_s_endpgm = 0xbf810000;
|
||||
const uint32_t TrapInstr = TrapEnabled ? Encoded_s_trap : Encoded_s_endpgm;
|
||||
MCStreamer &OS = getStreamer();
|
||||
OS.emitInt32(TrapInstr);
|
||||
for (int i = 0; i < 63; ++i) {
|
||||
OS.emitInt32(Encoded_s_nop);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
|
||||
const uint32_t Encoded_s_code_end = 0xbf9f0000;
|
||||
const uint32_t Encoded_s_nop = 0xbf800000;
|
||||
|
||||
@@ -96,12 +96,6 @@ public:
|
||||
/// \returns True on success, false on failure.
|
||||
virtual bool EmitCodeEnd(const MCSubtargetInfo &STI) { return true; }
|
||||
|
||||
/// \returns True on success, false on failure.
|
||||
virtual bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI,
|
||||
bool TrapEnabled) {
|
||||
return true;
|
||||
}
|
||||
|
||||
virtual void
|
||||
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName,
|
||||
const AMDGPU::MCKernelDescriptor &KernelDescriptor,
|
||||
@@ -168,10 +162,6 @@ public:
|
||||
/// \returns True on success, false on failure.
|
||||
bool EmitCodeEnd(const MCSubtargetInfo &STI) override;
|
||||
|
||||
/// \returns True on success, false on failure.
|
||||
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI,
|
||||
bool TrapEnabled) override;
|
||||
|
||||
void
|
||||
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName,
|
||||
const AMDGPU::MCKernelDescriptor &KernelDescriptor,
|
||||
@@ -225,10 +215,6 @@ public:
|
||||
/// \returns True on success, false on failure.
|
||||
bool EmitCodeEnd(const MCSubtargetInfo &STI) override;
|
||||
|
||||
/// \returns True on success, false on failure.
|
||||
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI,
|
||||
bool TrapEnabled) override;
|
||||
|
||||
void
|
||||
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName,
|
||||
const AMDGPU::MCKernelDescriptor &KernelDescriptor,
|
||||
|
||||
@@ -262,6 +262,8 @@ SmallVectorImpl<MCRegister> *SIMachineFunctionInfo::addPreloadedKernArg(
|
||||
// If the available register tuples are aligned with the kernarg to be
|
||||
// preloaded use that register, otherwise we need to use a set of SGPRs and
|
||||
// merge them.
|
||||
if (!ArgInfo.FirstKernArgPreloadReg)
|
||||
ArgInfo.FirstKernArgPreloadReg = getNextUserSGPR();
|
||||
Register PreloadReg =
|
||||
TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC);
|
||||
if (PreloadReg &&
|
||||
|
||||
@@ -144,6 +144,7 @@
|
||||
; GCN-O0-NEXT: SI Final Branch Preparation
|
||||
; GCN-O0-NEXT: Post RA hazard recognizer
|
||||
; GCN-O0-NEXT: Branch relaxation pass
|
||||
; GCN-O0-NEXT: AMDGPU Preload Kernel Arguments Prolog
|
||||
; GCN-O0-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O0-NEXT: Remove Loads Into Fake Uses
|
||||
; GCN-O0-NEXT: Live DEBUG_VALUE analysis
|
||||
@@ -424,6 +425,7 @@
|
||||
; GCN-O1-NEXT: Post RA hazard recognizer
|
||||
; GCN-O1-NEXT: AMDGPU Insert Delay ALU
|
||||
; GCN-O1-NEXT: Branch relaxation pass
|
||||
; GCN-O1-NEXT: AMDGPU Preload Kernel Arguments Prolog
|
||||
; GCN-O1-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O1-NEXT: Remove Loads Into Fake Uses
|
||||
; GCN-O1-NEXT: Live DEBUG_VALUE analysis
|
||||
@@ -732,6 +734,7 @@
|
||||
; GCN-O1-OPTS-NEXT: Post RA hazard recognizer
|
||||
; GCN-O1-OPTS-NEXT: AMDGPU Insert Delay ALU
|
||||
; GCN-O1-OPTS-NEXT: Branch relaxation pass
|
||||
; GCN-O1-OPTS-NEXT: AMDGPU Preload Kernel Arguments Prolog
|
||||
; GCN-O1-OPTS-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O1-OPTS-NEXT: Remove Loads Into Fake Uses
|
||||
; GCN-O1-OPTS-NEXT: Live DEBUG_VALUE analysis
|
||||
@@ -1046,6 +1049,7 @@
|
||||
; GCN-O2-NEXT: Post RA hazard recognizer
|
||||
; GCN-O2-NEXT: AMDGPU Insert Delay ALU
|
||||
; GCN-O2-NEXT: Branch relaxation pass
|
||||
; GCN-O2-NEXT: AMDGPU Preload Kernel Arguments Prolog
|
||||
; GCN-O2-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O2-NEXT: Remove Loads Into Fake Uses
|
||||
; GCN-O2-NEXT: Live DEBUG_VALUE analysis
|
||||
@@ -1373,6 +1377,7 @@
|
||||
; GCN-O3-NEXT: Post RA hazard recognizer
|
||||
; GCN-O3-NEXT: AMDGPU Insert Delay ALU
|
||||
; GCN-O3-NEXT: Branch relaxation pass
|
||||
; GCN-O3-NEXT: AMDGPU Preload Kernel Arguments Prolog
|
||||
; GCN-O3-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O3-NEXT: Remove Loads Into Fake Uses
|
||||
; GCN-O3-NEXT: Live DEBUG_VALUE analysis
|
||||
|
||||
@@ -4,18 +4,28 @@
|
||||
|
||||
define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_block_count_x:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dword s4, s[0:1], 0x8
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB0_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB0_0:
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s4
|
||||
; GFX940-NEXT: global_store_dword v0, v1, s[2:3] sc0 sc1
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_block_count_x:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dword s8, s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB0_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB0_0:
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s8
|
||||
; GFX90a-NEXT: global_store_dword v0, v1, s[6:7]
|
||||
@@ -28,18 +38,30 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0
|
||||
|
||||
define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inreg %out, i32 inreg) #0 {
|
||||
; GFX940-LABEL: preload_unused_arg_block_count_x:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s6, s[0:1], 0x10
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB1_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB1_0:
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s6
|
||||
; GFX940-NEXT: global_store_dword v0, v1, s[2:3] sc0 sc1
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_unused_arg_block_count_x:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x10
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB1_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB1_0:
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s10
|
||||
; GFX90a-NEXT: global_store_dword v0, v1, s[6:7]
|
||||
@@ -52,9 +74,13 @@ define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inr
|
||||
|
||||
define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %out, i256 inreg) {
|
||||
; GFX940-LABEL: no_free_sgprs_block_count_x:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB2_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB2_0:
|
||||
; GFX940-NEXT: s_load_dword s0, s[4:5], 0x28
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -63,9 +89,13 @@ define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %o
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: no_free_sgprs_block_count_x:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[12:15], s[8:9], 0x0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB2_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB2_0:
|
||||
; GFX90a-NEXT: s_load_dword s0, s[8:9], 0x28
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -135,9 +165,13 @@ define amdgpu_kernel void @mixed_inreg_block_count_x(ptr addrspace(1) %out, i32
|
||||
|
||||
define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: incorrect_type_i64_block_count_x:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB5_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB5_0:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x8
|
||||
; GFX940-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -146,9 +180,13 @@ define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inr
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: incorrect_type_i64_block_count_x:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB5_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB5_0:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -163,9 +201,13 @@ define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inr
|
||||
|
||||
define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: incorrect_type_i16_block_count_x:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB6_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB6_0:
|
||||
; GFX940-NEXT: s_load_dword s0, s[0:1], 0x8
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -174,9 +216,13 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: incorrect_type_i16_block_count_x:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB6_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB6_0:
|
||||
; GFX90a-NEXT: s_load_dword s0, s[4:5], 0x8
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -191,18 +237,28 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr
|
||||
|
||||
define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_block_count_y:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB7_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB7_0:
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s5
|
||||
; GFX940-NEXT: global_store_dword v0, v1, s[2:3] sc0 sc1
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_block_count_y:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB7_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB7_0:
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s9
|
||||
; GFX90a-NEXT: global_store_dword v0, v1, s[6:7]
|
||||
@@ -216,9 +272,13 @@ define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0
|
||||
|
||||
define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: random_incorrect_offset:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB8_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB8_0:
|
||||
; GFX940-NEXT: s_mov_b32 s4, 8
|
||||
; GFX940-NEXT: s_load_dword s0, s[0:1], s4 offset:0x2
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
@@ -228,9 +288,13 @@ define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out)
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: random_incorrect_offset:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB8_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB8_0:
|
||||
; GFX90a-NEXT: s_mov_b32 s0, 8
|
||||
; GFX90a-NEXT: s_load_dword s0, s[4:5], s0 offset:0x2
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
@@ -247,18 +311,30 @@ define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out)
|
||||
|
||||
define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_block_count_z:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s6, s[0:1], 0x10
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB9_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB9_0:
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s6
|
||||
; GFX940-NEXT: global_store_dword v0, v1, s[2:3] sc0 sc1
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_block_count_z:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x10
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB9_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB9_0:
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s10
|
||||
; GFX90a-NEXT: global_store_dword v0, v1, s[6:7]
|
||||
@@ -272,9 +348,15 @@ define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0
|
||||
|
||||
define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspace(1) inreg %out, i8 inreg %val) #0 {
|
||||
; GFX940-LABEL: preload_block_count_x_imparg_align_ptr_i8:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s6, s[0:1], 0x10
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB10_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB10_0:
|
||||
; GFX940-NEXT: s_and_b32 s0, s4, 0xff
|
||||
; GFX940-NEXT: s_add_i32 s0, s6, s0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
@@ -283,9 +365,15 @@ define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspa
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_block_count_x_imparg_align_ptr_i8:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x10
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB10_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB10_0:
|
||||
; GFX90a-NEXT: s_and_b32 s0, s8, 0xff
|
||||
; GFX90a-NEXT: s_add_i32 s0, s10, s0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
@@ -302,9 +390,15 @@ define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspa
|
||||
|
||||
define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_block_count_xyz:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s6, s[0:1], 0x10
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB11_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB11_0:
|
||||
; GFX940-NEXT: v_mov_b32_e32 v3, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, s4
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s5
|
||||
@@ -313,9 +407,15 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out)
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_block_count_xyz:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x10
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB11_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB11_0:
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v3, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, s8
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s9
|
||||
@@ -338,9 +438,14 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out)
|
||||
|
||||
define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_workgroup_size_x:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB12_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB12_0:
|
||||
; GFX940-NEXT: s_and_b32 s0, s7, 0xffff
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -348,9 +453,14 @@ define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out)
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_workgroup_size_x:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB12_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB12_0:
|
||||
; GFX90a-NEXT: s_and_b32 s0, s11, 0xffff
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -366,9 +476,14 @@ define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out)
|
||||
|
||||
define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_workgroup_size_y:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB13_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB13_0:
|
||||
; GFX940-NEXT: s_lshr_b32 s0, s7, 16
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -376,9 +491,14 @@ define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out)
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_workgroup_size_y:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB13_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB13_0:
|
||||
; GFX90a-NEXT: s_lshr_b32 s0, s11, 16
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -394,9 +514,15 @@ define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out)
|
||||
|
||||
define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_workgroup_size_z:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s8, s[0:1], 0x18
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB14_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB14_0:
|
||||
; GFX940-NEXT: s_and_b32 s0, s8, 0xffff
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -404,9 +530,15 @@ define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out)
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_workgroup_size_z:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB14_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB14_0:
|
||||
; GFX90a-NEXT: s_and_b32 s0, s12, 0xffff
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -422,9 +554,15 @@ define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out)
|
||||
|
||||
define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_workgroup_size_xyz:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s8, s[0:1], 0x18
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB15_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB15_0:
|
||||
; GFX940-NEXT: s_lshr_b32 s0, s7, 16
|
||||
; GFX940-NEXT: s_and_b32 s1, s7, 0xffff
|
||||
; GFX940-NEXT: s_and_b32 s4, s8, 0xffff
|
||||
@@ -436,9 +574,15 @@ define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %ou
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_workgroup_size_xyz:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB15_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB15_0:
|
||||
; GFX90a-NEXT: s_lshr_b32 s0, s11, 16
|
||||
; GFX90a-NEXT: s_and_b32 s1, s11, 0xffff
|
||||
; GFX90a-NEXT: s_and_b32 s2, s12, 0xffff
|
||||
@@ -467,9 +611,15 @@ define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %ou
|
||||
|
||||
define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_remainder_x:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s8, s[0:1], 0x18
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB16_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB16_0:
|
||||
; GFX940-NEXT: s_lshr_b32 s0, s8, 16
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -477,9 +627,15 @@ define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_remainder_x:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB16_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB16_0:
|
||||
; GFX90a-NEXT: s_lshr_b32 s0, s12, 16
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -495,9 +651,15 @@ define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 {
|
||||
|
||||
define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preloadremainder_y:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB17_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB17_0:
|
||||
; GFX940-NEXT: s_and_b32 s0, s9, 0xffff
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -505,9 +667,15 @@ define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preloadremainder_y:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB17_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB17_0:
|
||||
; GFX90a-NEXT: s_and_b32 s0, s13, 0xffff
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -523,9 +691,15 @@ define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 {
|
||||
|
||||
define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preloadremainder_z:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB18_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB18_0:
|
||||
; GFX940-NEXT: s_lshr_b32 s0, s9, 16
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -533,9 +707,15 @@ define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preloadremainder_z:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB18_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB18_0:
|
||||
; GFX90a-NEXT: s_lshr_b32 s0, s13, 16
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -551,9 +731,15 @@ define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 {
|
||||
|
||||
define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preloadremainder_xyz:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB19_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB19_0:
|
||||
; GFX940-NEXT: s_lshr_b32 s0, s9, 16
|
||||
; GFX940-NEXT: s_lshr_b32 s1, s8, 16
|
||||
; GFX940-NEXT: s_and_b32 s4, s9, 0xffff
|
||||
@@ -565,9 +751,15 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preloadremainder_xyz:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB19_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB19_0:
|
||||
; GFX90a-NEXT: s_lshr_b32 s0, s13, 16
|
||||
; GFX90a-NEXT: s_lshr_b32 s1, s12, 16
|
||||
; GFX90a-NEXT: s_and_b32 s2, s13, 0xffff
|
||||
@@ -596,9 +788,13 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0
|
||||
|
||||
define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inreg %out) {
|
||||
; GFX940-LABEL: no_free_sgprs_preloadremainder_z:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB20_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB20_0:
|
||||
; GFX940-NEXT: s_lshr_b32 s0, s15, 16
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s0
|
||||
@@ -606,9 +802,13 @@ define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inr
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: no_free_sgprs_preloadremainder_z:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[8:9], 0x0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB20_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB20_0:
|
||||
; GFX90a-NEXT: s_load_dword s0, s[8:9], 0x1c
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -628,18 +828,31 @@ define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inr
|
||||
|
||||
define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg %out, i192 inreg %t0, i32 inreg %t1) #0 {
|
||||
; GFX940-LABEL: preload_block_max_user_sgprs:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dword s12, s[0:1], 0x28
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB21_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB21_0:
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s12
|
||||
; GFX940-NEXT: global_store_dword v0, v1, s[2:3] sc0 sc1
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_block_max_user_sgprs:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_load_dword s14, s[4:5], 0x20
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB21_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB21_0:
|
||||
; GFX90a-NEXT: s_load_dword s0, s[4:5], 0x28
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
@@ -654,9 +867,15 @@ define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg %
|
||||
|
||||
define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(ptr addrspace(1) inreg %out) #0 {
|
||||
; GFX940-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
|
||||
; GFX940: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX940-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX940-NEXT: ; %bb.0:
|
||||
; GFX940: ; %bb.1:
|
||||
; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; GFX940-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
|
||||
; GFX940-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_branch .LBB22_0
|
||||
; GFX940-NEXT: .p2align 8
|
||||
; GFX940-NEXT: ; %bb.2:
|
||||
; GFX940-NEXT: .LBB22_0:
|
||||
; GFX940-NEXT: s_lshr_b32 s0, s9, 16
|
||||
; GFX940-NEXT: s_and_b32 s1, s8, 0xffff
|
||||
; GFX940-NEXT: v_mov_b32_e32 v3, 0
|
||||
@@ -667,9 +886,15 @@ define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(pt
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
; GFX90a-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
|
||||
; GFX90a: s_trap 2 ; Kernarg preload header. Trap with incompatible firmware that doesn't support preloading kernel arguments.
|
||||
; GFX90a-NEXT: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; GFX90a-NEXT: ; %bb.0:
|
||||
; GFX90a: ; %bb.1:
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
|
||||
; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
|
||||
; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x18
|
||||
; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX90a-NEXT: s_branch .LBB22_0
|
||||
; GFX90a-NEXT: .p2align 8
|
||||
; GFX90a-NEXT: ; %bb.2:
|
||||
; GFX90a-NEXT: .LBB22_0:
|
||||
; GFX90a-NEXT: s_lshr_b32 s0, s13, 16
|
||||
; GFX90a-NEXT: s_and_b32 s1, s12, 0xffff
|
||||
; GFX90a-NEXT: v_mov_b32_e32 v3, 0
|
||||
|
||||
@@ -1,23 +1,52 @@
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=1 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,HSA,ASM %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=1 -filetype=obj < %s | llvm-objdump --arch=amdgcn --mcpu=gfx940 --disassemble - | FileCheck -check-prefixes=GCN,HSA,OBJ %s
|
||||
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -amdgpu-kernarg-preload-count=1 -filetype=obj < %s | llvm-objdump --arch=amdgcn --mcpu=gfx940 --disassemble - | FileCheck -check-prefixes=GCN,NON-HSA,OBJ %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=1 -asm-verbose=0 < %s | llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx940 -filetype=obj | llvm-objdump --arch=amdgcn --mcpu=gfx940 --disassemble - | FileCheck -check-prefixes=GCN,HSA,OBJ %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -asm-verbose=0 < %s | FileCheck -check-prefixes=ASM %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -filetype=obj < %s | llvm-objdump --arch=amdgcn --mcpu=gfx942 --disassemble - | FileCheck -check-prefixes=OBJ %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -amdgpu-kernarg-preload-count=1 -asm-verbose=0 < %s | llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx942 -filetype=obj | llvm-objdump --arch=amdgcn --mcpu=gfx942 --disassemble - | FileCheck -check-prefixes=OBJ %s
|
||||
|
||||
; GCN: preload_kernarg_header
|
||||
; HSA: s_trap 2
|
||||
; NON-HSA: s_endpgm
|
||||
; ASM: .fill 63, 4, 0xbf800000 ; s_nop 0
|
||||
; OBJ-COUNT-63: s_nop 0
|
||||
define amdgpu_kernel void @preload_kernarg_header(ptr inreg %arg) {
|
||||
; OBJ: preload_ptr_kernarg_header
|
||||
; OBJ-COUNT-60: s_nop 0
|
||||
define amdgpu_kernel void @preload_ptr_kernarg_header(ptr inreg %arg) {
|
||||
; ASM-LABEL: preload_ptr_kernarg_header:
|
||||
; ASM: s_load_dwordx2 s[8:9], s[4:5], 0x0
|
||||
; ASM-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; ASM-NEXT: s_branch .LBB0_0
|
||||
; ASM-NEXT: .p2align 8
|
||||
; ASM-NEXT: .LBB0_0:
|
||||
; ASM-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; ASM-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
||||
; ASM-NEXT: s_endpgm
|
||||
store ptr %arg, ptr %arg
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN: non_kernel_function
|
||||
; GCN-NOT: s_trap 2
|
||||
; GCN-NOT: s_nop 0
|
||||
; GCN: flat_store
|
||||
; OBJ: preload_i32_kernarg_header
|
||||
; OBJ-COUNT-58: s_nop 0
|
||||
define amdgpu_kernel void @preload_i32_kernarg_header(ptr inreg %arg, i32 inreg %arg1) {
|
||||
; ASM-LABEL: preload_i32_kernarg_header:
|
||||
; ASM: s_load_dwordx2 s[8:9], s[4:5], 0x0
|
||||
; ASM-NEXT: s_load_dword s10, s[4:5], 0x8
|
||||
; ASM-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; ASM-NEXT: s_branch .LBB1_0
|
||||
; ASM-NEXT: .p2align 8
|
||||
; ASM-NEXT: .LBB1_0:
|
||||
; ASM-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
|
||||
; ASM-NEXT: v_mov_b32_e32 v2, s10
|
||||
; ASM-NEXT: flat_store_dword v[0:1], v2
|
||||
; ASM-NEXT: s_endpgm
|
||||
store i32 %arg1, ptr %arg
|
||||
ret void
|
||||
}
|
||||
|
||||
; OBJ: non_kernel_function
|
||||
; ASM: non_kernel_function
|
||||
; OBJ-NOT: s_branch
|
||||
; ASM-NOT: s_branch
|
||||
define void @non_kernel_function(ptr %arg) {
|
||||
; ASM-LABEL: non_kernel_function:
|
||||
; ASM: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; ASM-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
||||
; ASM-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; ASM-NEXT: s_setpc_b64 s[30:31]
|
||||
store ptr %arg, ptr %arg
|
||||
ret void
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user