[RISCV] Add Andes AX45MPV processor definition (#145267)

Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is
developed by Andes Technology https://www.andestech.com, a RISC-V IP
provider.

The overviews for AX45MPV:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mpv/

Scheduling model for RVV extension will be implemented a follow-up PR.

llvm/docs/ReleaseNotes.md

@@ -211,6 +211,7 @@ Changes to the RISC-V Backend
 * `-mcpu=sifive-x390` was added.
 * `-mtune=andes-45-series` was added.
 * Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension).
+* `-mcpu=andes-ax45mpv` was added.
 
 Changes to the WebAssembly Backend
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