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[InlineAsm] wrap Kind in enum class NFC

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Should add some minor type safety to the use of this information, since
there's quite a bit of metadata being laundered through an `unsigned`.

I'm looking to potentially add more bitfields to that `unsigned`, but I
find InlineAsm's big ol' bag of enum values and usage of `unsigned`
confusing, type-unsafe, and un-ergonomic. These can probably be better
abstracted.

I think the lack of static_cast outside of InlineAsm indicates the prior
code smell fixed here.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D159242
This commit is contained in:
Nick Desaulniers
2023-08-31 08:39:52 -07:00
parent cdd5b1629a
commit 2fad6e6985
16 changed files with 135 additions and 135 deletions
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76
llvm/include/llvm/IR/InlineAsm.h
View File

@@ -200,14 +200,14 @@ public:
// in the backend.
//
// The encoding of the flag word is currently:
// Bits 2-0 - A Kind_* value indicating the kind of the operand.
// Bits 2-0 - A Kind::* value indicating the kind of the operand.
// Bits 15-3 - The number of SDNode operands associated with this inline
// assembly operand.
// If bit 31 is set:
// Bit 30-16 - The operand number that this operand must match.
// When bits 2-0 are Kind_Mem, the Constraint_* value must be
// When bits 2-0 are Kind::Mem, the Constraint_* value must be
// obtained from the flags for this operand number.
// Else if bits 2-0 are Kind_Mem:
// Else if bits 2-0 are Kind::Mem:
// Bit 30-16 - A Constraint_* value indicating the original constraint
// code.
// Else:
@@ -218,12 +218,12 @@ public:
Op_InputChain = 0,
Op_AsmString = 1,
Op_MDNode = 2,
Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
Op_FirstOperand = 4,
// Fixed operands on an INLINEASM MachineInstr.
MIOp_AsmString = 0,
MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
MIOp_FirstOperand = 2,
// Interpretation of the MIOp_ExtraInfo bit field.
@@ -234,17 +234,6 @@ public:
Extra_MayStore = 16,
Extra_IsConvergent = 32,
// Inline asm operands map to multiple SDNode / MachineInstr operands.
// The first operand is an immediate describing the asm operand, the low
// bits is the kind:
Kind_RegUse = 1, // Input register, "r".
Kind_RegDef = 2, // Output register, "=r".
Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
Kind_Clobber = 4, // Clobbered register, "~r".
Kind_Imm = 5, // Immediate.
Kind_Mem = 6, // Memory operand, "m", or an address, "p".
Kind_Func = 7, // Address operand of function call
// Memory constraint codes.
// These could be tablegenerated but there's little need to do that since
// there's plenty of space in the encoding to support the union of all
@@ -290,21 +279,35 @@ public:
Flag_MatchingOperand = 0x80000000
};
static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
// Inline asm operands map to multiple SDNode / MachineInstr operands.
// The first operand is an immediate describing the asm operand, the low
// bits is the kind:
enum class Kind {
RegUse = 1, // Input register, "r".
RegDef = 2, // Output register, "=r".
RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
Clobber = 4, // Clobbered register, "~r".
Imm = 5, // Immediate.
Mem = 6, // Memory operand, "m", or an address, "p".
Func = 7, // Address operand of function call
};
static unsigned getFlagWord(Kind Kind, unsigned NumOps) {
assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
assert(Kind >= Kind_RegUse && Kind <= Kind_Func && "Invalid Kind");
return Kind | (NumOps << 3);
return static_cast<unsigned>(Kind) | (NumOps << 3);
}
static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
static bool isFuncKind(unsigned Flag) { return getKind(Flag) == Kind_Func; }
static bool isRegDefKind(unsigned Flag) {
return getKind(Flag) == Kind::RegDef;
}
static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind::Imm; }
static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind::Mem; }
static bool isFuncKind(unsigned Flag) { return getKind(Flag) == Kind::Func; }
static bool isRegDefEarlyClobberKind(unsigned Flag) {
return getKind(Flag) == Kind_RegDefEarlyClobber;
return getKind(Flag) == Kind::RegDefEarlyClobber;
}
static bool isClobberKind(unsigned Flag) {
return getKind(Flag) == Kind_Clobber;
return getKind(Flag) == Kind::Clobber;
}
/// getFlagWordForMatchingOp - Augment an existing flag word returned by
@@ -348,9 +351,7 @@ public:
return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
}
static unsigned getKind(unsigned Flags) {
return Flags & 7;
}
static Kind getKind(unsigned Flags) { return static_cast<Kind>(Flags & 7); }
static unsigned getMemoryConstraintID(unsigned Flag) {
assert((isMemKind(Flag) || isFuncKind(Flag)) &&
@@ -411,24 +412,23 @@ public:
return Result;
}
static StringRef getKindName(unsigned Kind) {
static StringRef getKindName(Kind Kind) {
switch (Kind) {
case InlineAsm::Kind_RegUse:
case Kind::RegUse:
return "reguse";
case InlineAsm::Kind_RegDef:
case Kind::RegDef:
return "regdef";
case InlineAsm::Kind_RegDefEarlyClobber:
case Kind::RegDefEarlyClobber:
return "regdef-ec";
case InlineAsm::Kind_Clobber:
case Kind::Clobber:
return "clobber";
case InlineAsm::Kind_Imm:
case Kind::Imm:
return "imm";
case InlineAsm::Kind_Mem:
case InlineAsm::Kind_Func:
case Kind::Mem:
case Kind::Func:
return "mem";
default:
llvm_unreachable("Unknown operand kind");
}
llvm_unreachable("Unknown operand kind");
}
static StringRef getMemConstraintName(unsigned Constraint) {

2
llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
View File

@@ -380,7 +380,7 @@ void AsmPrinter::emitInlineAsm(const MachineInstr *MI) const {
if (!MO.isImm())
continue;
unsigned Flags = MO.getImm();
if (InlineAsm::getKind(Flags) == InlineAsm::Kind_Clobber) {
if (InlineAsm::getKind(Flags) == InlineAsm::Kind::Clobber) {
Register Reg = MI->getOperand(I + 1).getReg();
if (!TRI->isAsmClobberable(*MF, Reg))
RestrRegs.push_back(Reg);

16
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
View File

@@ -380,7 +380,7 @@ bool InlineAsmLowering::lowerInlineAsm(
// Add information to the INLINEASM instruction to know about this
// output.
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
Inst.addImm(OpFlags);
ArrayRef<Register> SourceRegs =
@@ -406,8 +406,8 @@ bool InlineAsmLowering::lowerInlineAsm(
// Add information to the INLINEASM instruction to know that this
// register is set.
unsigned Flag = InlineAsm::getFlagWord(
OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
: InlineAsm::Kind_RegDef,
OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
: InlineAsm::Kind::RegDef,
OpInfo.Regs.size());
if (OpInfo.Regs.front().isVirtual()) {
// Put the register class of the virtual registers in the flag word.
@@ -470,7 +470,7 @@ bool InlineAsmLowering::lowerInlineAsm(
}
// Add Flag and input register operand (In) to Inst. Tie In to Def.
unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, 1);
unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx);
Inst.addImm(Flag);
Inst.addReg(In);
@@ -502,7 +502,7 @@ bool InlineAsmLowering::lowerInlineAsm(
// Add information to the INLINEASM node to know about this input.
unsigned OpFlags =
InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
InlineAsm::getFlagWord(InlineAsm::Kind::Imm, Ops.size());
Inst.addImm(OpFlags);
Inst.add(Ops);
break;
@@ -520,7 +520,7 @@ bool InlineAsmLowering::lowerInlineAsm(
unsigned ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
Inst.addImm(OpFlags);
ArrayRef<Register> SourceRegs =
@@ -563,7 +563,7 @@ bool InlineAsmLowering::lowerInlineAsm(
return false;
}
unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs);
unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, NumRegs);
if (OpInfo.Regs.front().isVirtual()) {
// Put the register class of the virtual registers in the flag word.
const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
@@ -581,7 +581,7 @@ bool InlineAsmLowering::lowerInlineAsm(
unsigned NumRegs = OpInfo.Regs.size();
if (NumRegs > 0) {
unsigned Flag =
InlineAsm::getFlagWord(InlineAsm::Kind_Clobber, NumRegs);
InlineAsm::getFlagWord(InlineAsm::Kind::Clobber, NumRegs);
Inst.addImm(Flag);
for (Register Reg : OpInfo.Regs) {

8
llvm/lib/CodeGen/MachineInstr.cpp
View File

@@ -924,14 +924,14 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx,
unsigned Flag = getOperand(FlagIdx).getImm();
unsigned RCID;
if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
if ((InlineAsm::getKind(Flag) == InlineAsm::Kind::RegUse ||
InlineAsm::getKind(Flag) == InlineAsm::Kind::RegDef ||
InlineAsm::getKind(Flag) == InlineAsm::Kind::RegDefEarlyClobber) &&
InlineAsm::hasRegClassConstraint(Flag, RCID))
return TRI->getRegClass(RCID);
// Assume that all registers in a memory operand are pointers.
if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
if (InlineAsm::getKind(Flag) == InlineAsm::Kind::Mem)
return TRI->getPointerRegClass(MF);
return nullptr;

17
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@@ -1318,8 +1318,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
++i; // Skip the ID value.
switch (InlineAsm::getKind(Flags)) {
default: llvm_unreachable("Bad flags!");
case InlineAsm::Kind_RegDef:
case InlineAsm::Kind::RegDef:
for (unsigned j = 0; j != NumVals; ++j, ++i) {
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
// FIXME: Add dead flags for physical and virtual registers defined.
@@ -1328,8 +1327,8 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
MIB.addReg(Reg, RegState::Define | getImplRegState(Reg.isPhysical()));
}
break;
case InlineAsm::Kind_RegDefEarlyClobber:
case InlineAsm::Kind_Clobber:
case InlineAsm::Kind::RegDefEarlyClobber:
case InlineAsm::Kind::Clobber:
for (unsigned j = 0; j != NumVals; ++j, ++i) {
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
@@ -1337,9 +1336,9 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
ECRegs.push_back(Reg);
}
break;
case InlineAsm::Kind_RegUse: // Use of register.
case InlineAsm::Kind_Imm: // Immediate.
case InlineAsm::Kind_Mem: // Non-function addressing mode.
case InlineAsm::Kind::RegUse: // Use of register.
case InlineAsm::Kind::Imm: // Immediate.
case InlineAsm::Kind::Mem: // Non-function addressing mode.
// The addressing mode has been selected, just add all of the
// operands to the machine instruction.
for (unsigned j = 0; j != NumVals; ++j, ++i)
@@ -1347,7 +1346,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
/*IsDebug=*/false, IsClone, IsCloned);
// Manually set isTied bits.
if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
if (InlineAsm::getKind(Flags) == InlineAsm::Kind::RegUse) {
unsigned DefGroup = 0;
if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
unsigned DefIdx = GroupIdx[DefGroup] + 1;
@@ -1357,7 +1356,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
}
}
break;
case InlineAsm::Kind_Func: // Function addressing mode.
case InlineAsm::Kind::Func: // Function addressing mode.
for (unsigned j = 0; j != NumVals; ++j, ++i) {
SDValue Op = Node->getOperand(i);
AddOperand(MIB, Op, 0, nullptr, VRBaseMap,

30
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@@ -989,7 +989,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
}
void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
unsigned MatchingIdx, const SDLoc &dl,
SelectionDAG &DAG,
std::vector<SDValue> &Ops) const {
@@ -1012,7 +1012,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
Ops.push_back(Res);
if (Code == InlineAsm::Kind_Clobber) {
if (Code == InlineAsm::Kind::Clobber) {
// Clobbers should always have a 1:1 mapping with registers, and may
// reference registers that have illegal (e.g. vector) types. Hence, we
// shouldn't try to apply any sort of splitting logic to them.
@@ -9279,7 +9279,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
MVT::i32));
@@ -9301,8 +9301,8 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
// Add information to the INLINEASM node to know that this register is
// set.
OpInfo.AssignedRegs.AddInlineAsmOperands(
OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
: InlineAsm::Kind_RegDef,
OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
: InlineAsm::Kind::RegDef,
false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
}
break;
@@ -9349,9 +9349,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
SDLoc dl = getCurSDLoc();
// Use the produced MatchedRegs object to
MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue, &Call);
MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
true, OpInfo.getMatchedOperand(), dl,
DAG, AsmNodeOperands);
MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, true,
OpInfo.getMatchedOperand(), dl, DAG,
AsmNodeOperands);
break;
}
@@ -9395,7 +9395,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
// Add information to the INLINEASM node to know about this input.
unsigned ResOpType =
InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
InlineAsm::getFlagWord(InlineAsm::Kind::Imm, Ops.size());
AsmNodeOperands.push_back(DAG.getTargetConstant(
ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
llvm::append_range(AsmNodeOperands, Ops);
@@ -9416,7 +9416,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
getCurSDLoc(),
@@ -9431,12 +9431,12 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
"Failed to convert memory constraint code to constraint id.");
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Mem, 1);
SDValue AsmOp = InOperandVal;
if (isFunction(InOperandVal)) {
auto *GA = cast<GlobalAddressSDNode>(InOperandVal);
ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Func, 1);
ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind::Func, 1);
AsmOp = DAG.getTargetGlobalAddress(GA->getGlobal(), getCurSDLoc(),
InOperandVal.getValueType(),
GA->getOffset());
@@ -9481,15 +9481,15 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Glue,
&Call);
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
dl, DAG, AsmNodeOperands);
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::RegUse, false,
0, dl, DAG, AsmNodeOperands);
break;
}
case InlineAsm::isClobber:
// Add the clobbered value to the operand list, so that the register
// allocator is aware that the physreg got clobbered.
if (!OpInfo.AssignedRegs.Regs.empty())
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind::Clobber,
false, 0, getCurSDLoc(), DAG,
AsmNodeOperands);
break;

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@@ -787,7 +787,7 @@ struct RegsForValue {
/// Add this value to the specified inlineasm node operand list. This adds the
/// code marker, matching input operand index (if applicable), and includes
/// the number of values added into it.
void AddInlineAsmOperands(unsigned Code, bool HasMatching,
void AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
unsigned MatchingIdx, const SDLoc &dl,
SelectionDAG &DAG, std::vector<SDValue> &Ops) const;

4
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@@ -2107,8 +2107,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
// Add this to the output node.
unsigned NewFlags =
InlineAsm::isMemKind(Flags)
? InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size())
: InlineAsm::getFlagWord(InlineAsm::Kind_Func, SelOps.size());
? InlineAsm::getFlagWord(InlineAsm::Kind::Mem, SelOps.size())
: InlineAsm::getFlagWord(InlineAsm::Kind::Func, SelOps.size());
NewFlags = InlineAsm::getFlagWordForMem(NewFlags, ConstraintID);
Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
llvm::append_range(Ops, SelOps);

2
llvm/lib/CodeGen/TargetInstrInfo.cpp
View File

@@ -1610,7 +1610,7 @@ std::string TargetInstrInfo::createMIROperandComment(
assert(Op.isImm() && "Expected flag operand to be an immediate");
// Pretty print the inline asm operand descriptor.
unsigned Flag = Op.getImm();
unsigned Kind = InlineAsm::getKind(Flag);
InlineAsm::Kind Kind = InlineAsm::getKind(Flag);
OS << InlineAsm::getKindName(Kind);
unsigned RCID = 0;

30
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@@ -5707,7 +5707,8 @@ bool ARMDAGToDAGISel::tryWriteRegister(SDNode *N){
bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
std::vector<SDValue> AsmNodeOperands;
unsigned Flag, Kind;
unsigned Flag;
InlineAsm::Kind Kind;
bool Changed = false;
unsigned NumOps = N->getNumOperands();
@@ -5739,10 +5740,10 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
continue;
// Immediate operands to inline asm in the SelectionDAG are modeled with
// two operands. The first is a constant of value InlineAsm::Kind_Imm, and
// two operands. The first is a constant of value InlineAsm::Kind::Imm, and
// the second is a constant with the value of the immediate. If we get here
// and we have a Kind_Imm, skip the next operand, and continue.
if (Kind == InlineAsm::Kind_Imm) {
// and we have a Kind::Imm, skip the next operand, and continue.
if (Kind == InlineAsm::Kind::Imm) {
SDValue op = N->getOperand(++i);
AsmNodeOperands.push_back(op);
continue;
@@ -5760,18 +5761,18 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
IsTiedToChangedOp = OpChanged[DefIdx];
// Memory operands to inline asm in the SelectionDAG are modeled with two
// operands: a constant of value InlineAsm::Kind_Mem followed by the input
// operand. If we get here and we have a Kind_Mem, skip the next operand (so
// it doesn't get misinterpreted), and continue. We do this here because
// operands: a constant of value InlineAsm::Kind::Mem followed by the input
// operand. If we get here and we have a Kind::Mem, skip the next operand
// (so it doesn't get misinterpreted), and continue. We do this here because
// it's important to update the OpChanged array correctly before moving on.
if (Kind == InlineAsm::Kind_Mem) {
if (Kind == InlineAsm::Kind::Mem) {
SDValue op = N->getOperand(++i);
AsmNodeOperands.push_back(op);
continue;
}
if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
&& Kind != InlineAsm::Kind_RegDefEarlyClobber)
if (Kind != InlineAsm::Kind::RegUse && Kind != InlineAsm::Kind::RegDef &&
Kind != InlineAsm::Kind::RegDefEarlyClobber)
continue;
unsigned RC;
@@ -5788,8 +5789,8 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
SDValue PairedReg;
MachineRegisterInfo &MRI = MF->getRegInfo();
if (Kind == InlineAsm::Kind_RegDef ||
Kind == InlineAsm::Kind_RegDefEarlyClobber) {
if (Kind == InlineAsm::Kind::RegDef ||
Kind == InlineAsm::Kind::RegDefEarlyClobber) {
// Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
// the original GPRs.
@@ -5814,9 +5815,8 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
Ops.push_back(T1.getValue(1));
CurDAG->UpdateNodeOperands(GU, Ops);
}
else {
// For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
} else {
// For Kind == InlineAsm::Kind::RegUse, we first copy two GPRs into a
// GPRPair and then pass the GPRPair to the inline asm.
SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];

2
llvm/lib/Target/AVR/AVRISelLowering.cpp
View File

@@ -976,7 +976,7 @@ SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
Ops.push_back(Operand);
}
}
unsigned Flags = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
unsigned Flags = InlineAsm::getFlagWord(InlineAsm::Kind::RegUse, 1);
Ops.push_back(DAG.getTargetConstant(Flags, dl, MVT::i32));
Ops.push_back(ZeroReg);
if (Glue) {

27
llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
View File

@@ -116,7 +116,8 @@ void CSKYDAGToDAGISel::Select(SDNode *N) {
bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
std::vector<SDValue> AsmNodeOperands;
unsigned Flag, Kind;
unsigned Flag;
InlineAsm::Kind Kind;
bool Changed = false;
unsigned NumOps = N->getNumOperands();
@@ -146,10 +147,10 @@ bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
continue;
// Immediate operands to inline asm in the SelectionDAG are modeled with
// two operands. The first is a constant of value InlineAsm::Kind_Imm, and
// two operands. The first is a constant of value InlineAsm::Kind::Imm, and
// the second is a constant with the value of the immediate. If we get here
// and we have a Kind_Imm, skip the next operand, and continue.
if (Kind == InlineAsm::Kind_Imm) {
// and we have a Kind::Imm, skip the next operand, and continue.
if (Kind == InlineAsm::Kind::Imm) {
SDValue op = N->getOperand(++i);
AsmNodeOperands.push_back(op);
continue;
@@ -167,18 +168,18 @@ bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
IsTiedToChangedOp = OpChanged[DefIdx];
// Memory operands to inline asm in the SelectionDAG are modeled with two
// operands: a constant of value InlineAsm::Kind_Mem followed by the input
// operand. If we get here and we have a Kind_Mem, skip the next operand (so
// it doesn't get misinterpreted), and continue. We do this here because
// operands: a constant of value InlineAsm::Kind::Mem followed by the input
// operand. If we get here and we have a Kind::Mem, skip the next operand
// (so it doesn't get misinterpreted), and continue. We do this here because
// it's important to update the OpChanged array correctly before moving on.
if (Kind == InlineAsm::Kind_Mem) {
if (Kind == InlineAsm::Kind::Mem) {
SDValue op = N->getOperand(++i);
AsmNodeOperands.push_back(op);
continue;
}
if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef &&
Kind != InlineAsm::Kind_RegDefEarlyClobber)
if (Kind != InlineAsm::Kind::RegUse && Kind != InlineAsm::Kind::RegDef &&
Kind != InlineAsm::Kind::RegDefEarlyClobber)
continue;
unsigned RC;
@@ -195,8 +196,8 @@ bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
SDValue PairedReg;
MachineRegisterInfo &MRI = MF->getRegInfo();
if (Kind == InlineAsm::Kind_RegDef ||
Kind == InlineAsm::Kind_RegDefEarlyClobber) {
if (Kind == InlineAsm::Kind::RegDef ||
Kind == InlineAsm::Kind::RegDefEarlyClobber) {
// Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
// the original GPRs.
@@ -222,7 +223,7 @@ bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
Ops.push_back(T1.getValue(1));
CurDAG->UpdateNodeOperands(GU, Ops);
} else {
// For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
// For Kind == InlineAsm::Kind::RegUse, we first copy two GPRs into a
// GPRPair and then pass the GPRPair to the inline asm.
SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];

12
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@@ -676,14 +676,14 @@ HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
switch (InlineAsm::getKind(Flags)) {
default:
llvm_unreachable("Bad flags!");
case InlineAsm::Kind_RegUse:
case InlineAsm::Kind_Imm:
case InlineAsm::Kind_Mem:
case InlineAsm::Kind::RegUse:
case InlineAsm::Kind::Imm:
case InlineAsm::Kind::Mem:
i += NumVals;
break;
case InlineAsm::Kind_Clobber:
case InlineAsm::Kind_RegDef:
case InlineAsm::Kind_RegDefEarlyClobber: {
case InlineAsm::Kind::Clobber:
case InlineAsm::Kind::RegDef:
case InlineAsm::Kind::RegDefEarlyClobber: {
for (; NumVals; --NumVals, ++i) {
Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
if (Reg != LR)

12
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@@ -3779,14 +3779,14 @@ SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
switch (InlineAsm::getKind(Flags)) {
default:
llvm_unreachable("Bad flags!");
case InlineAsm::Kind_RegUse:
case InlineAsm::Kind_Imm:
case InlineAsm::Kind_Mem:
case InlineAsm::Kind::RegUse:
case InlineAsm::Kind::Imm:
case InlineAsm::Kind::Mem:
i += NumVals;
break;
case InlineAsm::Kind_Clobber:
case InlineAsm::Kind_RegDef:
case InlineAsm::Kind_RegDefEarlyClobber: {
case InlineAsm::Kind::Clobber:
case InlineAsm::Kind::RegDef:
case InlineAsm::Kind::RegDefEarlyClobber: {
for (; NumVals; --NumVals, ++i) {
Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
if (Reg != PPC::LR && Reg != PPC::LR8)

22
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@@ -162,7 +162,8 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
// and have that work. Then, delete this function.
bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
std::vector<SDValue> AsmNodeOperands;
unsigned Flag, Kind;
unsigned Flag;
InlineAsm::Kind Kind;
bool Changed = false;
unsigned NumOps = N->getNumOperands();
@@ -194,10 +195,10 @@ bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
continue;
// Immediate operands to inline asm in the SelectionDAG are modeled with
// two operands. The first is a constant of value InlineAsm::Kind_Imm, and
// two operands. The first is a constant of value InlineAsm::Kind::Imm, and
// the second is a constant with the value of the immediate. If we get here
// and we have a Kind_Imm, skip the next operand, and continue.
if (Kind == InlineAsm::Kind_Imm) {
// and we have a Kind::Imm, skip the next operand, and continue.
if (Kind == InlineAsm::Kind::Imm) {
SDValue op = N->getOperand(++i);
AsmNodeOperands.push_back(op);
continue;
@@ -214,8 +215,8 @@ bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
IsTiedToChangedOp = OpChanged[DefIdx];
if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
&& Kind != InlineAsm::Kind_RegDefEarlyClobber)
if (Kind != InlineAsm::Kind::RegUse && Kind != InlineAsm::Kind::RegDef &&
Kind != InlineAsm::Kind::RegDefEarlyClobber)
continue;
unsigned RC;
@@ -232,8 +233,8 @@ bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
SDValue PairedReg;
MachineRegisterInfo &MRI = MF->getRegInfo();
if (Kind == InlineAsm::Kind_RegDef ||
Kind == InlineAsm::Kind_RegDefEarlyClobber) {
if (Kind == InlineAsm::Kind::RegDef ||
Kind == InlineAsm::Kind::RegDefEarlyClobber) {
// Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
// the original GPRs.
@@ -258,9 +259,8 @@ bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){
std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
Ops.push_back(T1.getValue(1));
CurDAG->UpdateNodeOperands(GU, Ops);
}
else {
// For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
} else {
// For Kind == InlineAsm::Kind::RegUse, we first copy two GPRs into a
// GPRPair and then pass the GPRPair to the inline asm.
SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];

8
llvm/lib/Target/X86/X86FloatingPoint.cpp
View File

@@ -1617,14 +1617,14 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
}
switch (InlineAsm::getKind(Flags)) {
case InlineAsm::Kind_RegUse:
case InlineAsm::Kind::RegUse:
STUses |= (1u << STReg);
break;
case InlineAsm::Kind_RegDef:
case InlineAsm::Kind_RegDefEarlyClobber:
case InlineAsm::Kind::RegDef:
case InlineAsm::Kind::RegDefEarlyClobber:
STDefs |= (1u << STReg);
break;
case InlineAsm::Kind_Clobber:
case InlineAsm::Kind::Clobber:
STClobbers |= (1u << STReg);
break;
default: