[llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics.
This change renames the intrinsics to not have "experimental" in the name. The autoupgrader will handle legacy intrinsics. Relevant ML thread: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140729.html Differential Revision: https://reviews.llvm.org/D88787
This commit is contained in:
Amara Emerson
@@ -15543,8 +15543,8 @@ should exit, this ``SUB`` is not allowed to wrap. The result is a condition
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that is used by the conditional branch controlling the loop.
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Experimental Vector Reduction Intrinsics
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----------------------------------------
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Vector Reduction Intrinsics
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---------------------------
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Horizontal reductions of vectors can be expressed using the following
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intrinsics. Each one takes a vector operand as an input and applies its
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@@ -15552,21 +15552,21 @@ respective operation across all elements of the vector, returning a single
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scalar result of the same element type.
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'``llvm.experimental.vector.reduce.add.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.add.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %a)
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
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declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.add.*``' intrinsics do an integer ``ADD``
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The '``llvm.vector.reduce.add.*``' intrinsics do an integer ``ADD``
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reduction of a vector, returning the result as a scalar. The return type matches
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the element-type of the vector input.
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@@ -15574,34 +15574,34 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.v2.fadd.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.fadd.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %start_value, <4 x float> %a)
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declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double %start_value, <2 x double> %a)
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declare float @llvm.vector.reduce.fadd.v4f32(float %start_value, <4 x float> %a)
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declare double @llvm.vector.reduce.fadd.v2f64(double %start_value, <2 x double> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.v2.fadd.*``' intrinsics do a floating-point
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The '``llvm.vector.reduce.fadd.*``' intrinsics do a floating-point
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``ADD`` reduction of a vector, returning the result as a scalar. The return type
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matches the element-type of the vector input.
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If the intrinsic call has the 'reassoc' or 'fast' flags set, then the
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reduction will not preserve the associativity of an equivalent scalarized
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counterpart. Otherwise the reduction will be *ordered*, thus implying that
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the operation respects the associativity of a scalarized reduction. That is, the
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reduction begins with the start value and performs an fadd operation with consecutively
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increasing vector element indices. See the following pseudocode:
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If the intrinsic call has the 'reassoc' flag set, then the reduction will not
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preserve the associativity of an equivalent scalarized counterpart. Otherwise
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the reduction will be *sequential*, thus implying that the operation respects
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the associativity of a scalarized reduction. That is, the reduction begins with
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the start value and performs an fadd operation with consecutively increasing
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vector element indices. See the following pseudocode:
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::
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float ordered_fadd(start_value, input_vector)
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float sequential_fadd(start_value, input_vector)
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result = start_value
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for i = 0 to length(input_vector)
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result = result + input_vector[i]
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@@ -15619,25 +15619,25 @@ Examples:
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::
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%unord = call reassoc float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.0, <4 x float> %input) ; unordered reduction
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%ord = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %start_value, <4 x float> %input) ; ordered reduction
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%unord = call reassoc float @llvm.vector.reduce.fadd.v4f32(float 0.0, <4 x float> %input) ; relaxed reduction
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%ord = call float @llvm.vector.reduce.fadd.v4f32(float %start_value, <4 x float> %input) ; sequential reduction
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'``llvm.experimental.vector.reduce.mul.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.mul.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> %a)
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declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)
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declare i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.mul.*``' intrinsics do an integer ``MUL``
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The '``llvm.vector.reduce.mul.*``' intrinsics do an integer ``MUL``
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reduction of a vector, returning the result as a scalar. The return type matches
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the element-type of the vector input.
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@@ -15645,34 +15645,34 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.v2.fmul.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.fmul.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %start_value, <4 x float> %a)
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declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v2f64(double %start_value, <2 x double> %a)
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declare float @llvm.vector.reduce.fmul.v4f32(float %start_value, <4 x float> %a)
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declare double @llvm.vector.reduce.fmul.v2f64(double %start_value, <2 x double> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.v2.fmul.*``' intrinsics do a floating-point
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The '``llvm.vector.reduce.fmul.*``' intrinsics do a floating-point
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``MUL`` reduction of a vector, returning the result as a scalar. The return type
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matches the element-type of the vector input.
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If the intrinsic call has the 'reassoc' or 'fast' flags set, then the
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reduction will not preserve the associativity of an equivalent scalarized
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counterpart. Otherwise the reduction will be *ordered*, thus implying that
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the operation respects the associativity of a scalarized reduction. That is, the
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reduction begins with the start value and performs an fmul operation with consecutively
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increasing vector element indices. See the following pseudocode:
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If the intrinsic call has the 'reassoc' flag set, then the reduction will not
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preserve the associativity of an equivalent scalarized counterpart. Otherwise
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the reduction will be *sequential*, thus implying that the operation respects
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the associativity of a scalarized reduction. That is, the reduction begins with
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the start value and performs an fmul operation with consecutively increasing
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vector element indices. See the following pseudocode:
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::
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float ordered_fmul(start_value, input_vector)
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float sequential_fmul(start_value, input_vector)
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result = start_value
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for i = 0 to length(input_vector)
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result = result * input_vector[i]
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@@ -15690,23 +15690,23 @@ Examples:
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::
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%unord = call reassoc float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float 1.0, <4 x float> %input) ; unordered reduction
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%ord = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %start_value, <4 x float> %input) ; ordered reduction
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%unord = call reassoc float @llvm.vector.reduce.fmul.v4f32(float 1.0, <4 x float> %input) ; relaxed reduction
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%ord = call float @llvm.vector.reduce.fmul.v4f32(float %start_value, <4 x float> %input) ; sequential reduction
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'``llvm.experimental.vector.reduce.and.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.and.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %a)
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declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.and.*``' intrinsics do a bitwise ``AND``
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The '``llvm.vector.reduce.and.*``' intrinsics do a bitwise ``AND``
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reduction of a vector, returning the result as a scalar. The return type matches
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the element-type of the vector input.
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@@ -15714,20 +15714,20 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.or.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.or.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a)
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declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.or.*``' intrinsics do a bitwise ``OR`` reduction
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The '``llvm.vector.reduce.or.*``' intrinsics do a bitwise ``OR`` reduction
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of a vector, returning the result as a scalar. The return type matches the
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element-type of the vector input.
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@@ -15735,20 +15735,20 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.xor.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.xor.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %a)
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declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.xor.*``' intrinsics do a bitwise ``XOR``
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The '``llvm.vector.reduce.xor.*``' intrinsics do a bitwise ``XOR``
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reduction of a vector, returning the result as a scalar. The return type matches
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the element-type of the vector input.
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@@ -15756,20 +15756,20 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.smax.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.smax.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %a)
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declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.smax.*``' intrinsics do a signed integer
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The '``llvm.vector.reduce.smax.*``' intrinsics do a signed integer
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``MAX`` reduction of a vector, returning the result as a scalar. The return type
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matches the element-type of the vector input.
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@@ -15777,20 +15777,20 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.smin.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.smin.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %a)
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declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.smin.*``' intrinsics do a signed integer
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The '``llvm.vector.reduce.smin.*``' intrinsics do a signed integer
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``MIN`` reduction of a vector, returning the result as a scalar. The return type
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matches the element-type of the vector input.
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@@ -15798,20 +15798,20 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.umax.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.umax.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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::
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declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %a)
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declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.umax.*``' intrinsics do an unsigned
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The '``llvm.vector.reduce.umax.*``' intrinsics do an unsigned
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integer ``MAX`` reduction of a vector, returning the result as a scalar. The
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return type matches the element-type of the vector input.
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@@ -15819,20 +15819,20 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.umin.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.umin.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
|
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::
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declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %a)
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declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reduce.umin.*``' intrinsics do an unsigned
|
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The '``llvm.vector.reduce.umin.*``' intrinsics do an unsigned
|
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integer ``MIN`` reduction of a vector, returning the result as a scalar. The
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return type matches the element-type of the vector input.
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@@ -15840,21 +15840,21 @@ Arguments:
|
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""""""""""
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The argument to this intrinsic must be a vector of integer values.
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'``llvm.experimental.vector.reduce.fmax.*``' Intrinsic
|
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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'``llvm.vector.reduce.fmax.*``' Intrinsic
|
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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|
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Syntax:
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"""""""
|
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::
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declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %a)
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declare float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
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declare double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
|
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|
||||
Overview:
|
||||
"""""""""
|
||||
|
||||
The '``llvm.experimental.vector.reduce.fmax.*``' intrinsics do a floating-point
|
||||
The '``llvm.vector.reduce.fmax.*``' intrinsics do a floating-point
|
||||
``MAX`` reduction of a vector, returning the result as a scalar. The return type
|
||||
matches the element-type of the vector input.
|
||||
|
||||
@@ -15870,8 +15870,8 @@ Arguments:
|
||||
""""""""""
|
||||
The argument to this intrinsic must be a vector of floating-point values.
|
||||
|
||||
'``llvm.experimental.vector.reduce.fmin.*``' Intrinsic
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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||||
'``llvm.vector.reduce.fmin.*``' Intrinsic
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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||||
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||||
Syntax:
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||||
"""""""
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@@ -15879,13 +15879,13 @@ This is an overloaded intrinsic.
|
||||
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||||
::
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declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %a)
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declare float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
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declare double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
|
||||
|
||||
Overview:
|
||||
"""""""""
|
||||
|
||||
The '``llvm.experimental.vector.reduce.fmin.*``' intrinsics do a floating-point
|
||||
The '``llvm.vector.reduce.fmin.*``' intrinsics do a floating-point
|
||||
``MIN`` reduction of a vector, returning the result as a scalar. The return type
|
||||
matches the element-type of the vector input.
|
||||
|
||||
|
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@@ -63,6 +63,10 @@ Changes to the LLVM IR
|
||||
* Added the ``byref`` attribute to better represent argument passing
|
||||
for the `amdgpu_kernel` calling convention.
|
||||
|
||||
* The ``llvm.experimental.vector.reduce`` family of intrinsics have been renamed
|
||||
to drop the "experimental" from the name, reflecting their now fully supported
|
||||
status in the IR.
|
||||
|
||||
Changes to building LLVM
|
||||
------------------------
|
||||
|
||||
|
||||
@@ -1180,19 +1180,19 @@ public:
|
||||
return thisT()->getGatherScatterOpCost(Instruction::Load, RetTy, Args[0],
|
||||
VarMask, Alignment, CostKind, I);
|
||||
}
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::experimental_vector_reduce_fmin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::experimental_vector_reduce_umin: {
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umin: {
|
||||
IntrinsicCostAttributes Attrs(IID, RetTy, Args[0]->getType(), FMF, 1, I);
|
||||
return getIntrinsicInstrCost(Attrs, CostKind);
|
||||
}
|
||||
@@ -1407,46 +1407,46 @@ public:
|
||||
return thisT()->getMaskedMemoryOpCost(Instruction::Load, Ty, TyAlign, 0,
|
||||
CostKind);
|
||||
}
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
return thisT()->getArithmeticReductionCost(Instruction::Add, VecOpTy,
|
||||
/*IsPairwiseForm=*/false,
|
||||
CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
return thisT()->getArithmeticReductionCost(Instruction::Mul, VecOpTy,
|
||||
/*IsPairwiseForm=*/false,
|
||||
CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
return thisT()->getArithmeticReductionCost(Instruction::And, VecOpTy,
|
||||
/*IsPairwiseForm=*/false,
|
||||
CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
return thisT()->getArithmeticReductionCost(Instruction::Or, VecOpTy,
|
||||
/*IsPairwiseForm=*/false,
|
||||
CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
return thisT()->getArithmeticReductionCost(Instruction::Xor, VecOpTy,
|
||||
/*IsPairwiseForm=*/false,
|
||||
CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
// FIXME: Add new flag for cost of strict reductions.
|
||||
return thisT()->getArithmeticReductionCost(Instruction::FAdd, VecOpTy,
|
||||
/*IsPairwiseForm=*/false,
|
||||
CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
// FIXME: Add new flag for cost of strict reductions.
|
||||
return thisT()->getArithmeticReductionCost(Instruction::FMul, VecOpTy,
|
||||
/*IsPairwiseForm=*/false,
|
||||
CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::experimental_vector_reduce_fmin:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmin:
|
||||
return thisT()->getMinMaxReductionCost(
|
||||
VecOpTy, cast<VectorType>(CmpInst::makeCmpResultType(VecOpTy)),
|
||||
/*IsPairwiseForm=*/false,
|
||||
/*IsUnsigned=*/false, CostKind);
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
return thisT()->getMinMaxReductionCost(
|
||||
VecOpTy, cast<VectorType>(CmpInst::makeCmpResultType(VecOpTy)),
|
||||
/*IsPairwiseForm=*/false,
|
||||
|
||||
@@ -1452,34 +1452,35 @@ def int_memset_element_unordered_atomic
|
||||
//===------------------------ Reduction Intrinsics ------------------------===//
|
||||
//
|
||||
let IntrProperties = [IntrNoMem, IntrWillReturn] in {
|
||||
def int_experimental_vector_reduce_v2_fadd : Intrinsic<[llvm_anyfloat_ty],
|
||||
[LLVMMatchType<0>,
|
||||
llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_v2_fmul : Intrinsic<[llvm_anyfloat_ty],
|
||||
[LLVMMatchType<0>,
|
||||
llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_add : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_mul : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_and : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_or : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_xor : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_smax : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_smin : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_umax : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_umin : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_fmax : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_experimental_vector_reduce_fmin : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
|
||||
def int_vector_reduce_fadd : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[LLVMVectorElementType<0>,
|
||||
llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_fmul : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[LLVMVectorElementType<0>,
|
||||
llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_add : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_mul : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_and : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_or : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_xor : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_smax : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_smin : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_umax : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_umin : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_fmax : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
def int_vector_reduce_fmin : Intrinsic<[LLVMVectorElementType<0>],
|
||||
[llvm_anyvector_ty]>;
|
||||
}
|
||||
|
||||
//===----- Matrix intrinsics ---------------------------------------------===//
|
||||
|
||||
@@ -1457,15 +1457,15 @@ bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
|
||||
case Intrinsic::smul_fix_sat:
|
||||
case Intrinsic::bitreverse:
|
||||
case Intrinsic::is_constant:
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
// Target intrinsics
|
||||
case Intrinsic::arm_mve_vctp8:
|
||||
case Intrinsic::arm_mve_vctp16:
|
||||
@@ -1711,31 +1711,31 @@ Constant *ConstantFoldVectorReduce(Intrinsic::ID IID, Constant *Op) {
|
||||
return nullptr;
|
||||
const APInt &X = CI->getValue();
|
||||
switch (IID) {
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
Acc = Acc + X;
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
Acc = Acc * X;
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
Acc = Acc & X;
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
Acc = Acc | X;
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
Acc = Acc ^ X;
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
Acc = APIntOps::smin(Acc, X);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
Acc = APIntOps::smax(Acc, X);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
Acc = APIntOps::umin(Acc, X);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
Acc = APIntOps::umax(Acc, X);
|
||||
break;
|
||||
}
|
||||
@@ -2240,15 +2240,15 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
|
||||
if (isa<ConstantAggregateZero>(Operands[0])) {
|
||||
switch (IntrinsicID) {
|
||||
default: break;
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
return ConstantInt::get(Ty, 0);
|
||||
}
|
||||
}
|
||||
@@ -2259,15 +2259,15 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
|
||||
auto *Op = cast<Constant>(Operands[0]);
|
||||
switch (IntrinsicID) {
|
||||
default: break;
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
if (Constant *C = ConstantFoldVectorReduce(IntrinsicID, Op))
|
||||
return C;
|
||||
break;
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This pass implements IR expansion for reduction intrinsics, allowing targets
|
||||
// to enable the experimental intrinsics until just before codegen.
|
||||
// to enable the intrinsics until just before codegen.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@@ -30,27 +30,27 @@ namespace {
|
||||
|
||||
unsigned getOpcode(Intrinsic::ID ID) {
|
||||
switch (ID) {
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
return Instruction::FAdd;
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
return Instruction::FMul;
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
return Instruction::Add;
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
return Instruction::Mul;
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
return Instruction::And;
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
return Instruction::Or;
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
return Instruction::Xor;
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
return Instruction::ICmp;
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::experimental_vector_reduce_fmin:
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmin:
|
||||
return Instruction::FCmp;
|
||||
default:
|
||||
llvm_unreachable("Unexpected ID");
|
||||
@@ -59,17 +59,17 @@ unsigned getOpcode(Intrinsic::ID ID) {
|
||||
|
||||
RecurrenceDescriptor::MinMaxRecurrenceKind getMRK(Intrinsic::ID ID) {
|
||||
switch (ID) {
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
return RecurrenceDescriptor::MRK_SIntMax;
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
return RecurrenceDescriptor::MRK_SIntMin;
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
return RecurrenceDescriptor::MRK_UIntMax;
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
return RecurrenceDescriptor::MRK_UIntMin;
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
return RecurrenceDescriptor::MRK_FloatMax;
|
||||
case Intrinsic::experimental_vector_reduce_fmin:
|
||||
case Intrinsic::vector_reduce_fmin:
|
||||
return RecurrenceDescriptor::MRK_FloatMin;
|
||||
default:
|
||||
return RecurrenceDescriptor::MRK_Invalid;
|
||||
@@ -83,19 +83,19 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
|
||||
if (auto *II = dyn_cast<IntrinsicInst>(&I)) {
|
||||
switch (II->getIntrinsicID()) {
|
||||
default: break;
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::experimental_vector_reduce_fmin:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmin:
|
||||
if (TTI->shouldExpandReduction(II))
|
||||
Worklist.push_back(II);
|
||||
|
||||
@@ -116,8 +116,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
|
||||
Builder.setFastMathFlags(FMF);
|
||||
switch (ID) {
|
||||
default: llvm_unreachable("Unexpected intrinsic!");
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul: {
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
case Intrinsic::vector_reduce_fmul: {
|
||||
// FMFs must be attached to the call, otherwise it's an ordered reduction
|
||||
// and it can't be handled by generating a shuffle sequence.
|
||||
Value *Acc = II->getArgOperand(0);
|
||||
@@ -135,15 +135,15 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
|
||||
}
|
||||
break;
|
||||
}
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::experimental_vector_reduce_umin: {
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umin: {
|
||||
Value *Vec = II->getArgOperand(0);
|
||||
if (!isPowerOf2_32(
|
||||
cast<FixedVectorType>(Vec->getType())->getNumElements()))
|
||||
@@ -152,8 +152,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
|
||||
Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), MRK);
|
||||
break;
|
||||
}
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::experimental_vector_reduce_fmin: {
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmin: {
|
||||
// FIXME: We only expand 'fast' reductions here because the underlying
|
||||
// code in createMinMaxOp() assumes that comparisons use 'fast'
|
||||
// semantics.
|
||||
|
||||
@@ -6762,19 +6762,19 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
|
||||
LowerDeoptimizeCall(&I);
|
||||
return;
|
||||
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::experimental_vector_reduce_fmin:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmin:
|
||||
visitVectorReduce(I, Intrinsic);
|
||||
return;
|
||||
|
||||
@@ -8937,7 +8937,7 @@ void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
|
||||
SDFlags.copyFMF(*FPMO);
|
||||
|
||||
switch (Intrinsic) {
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
if (SDFlags.hasAllowReassociation())
|
||||
Res = DAG.getNode(ISD::FADD, dl, VT, Op1,
|
||||
DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags),
|
||||
@@ -8945,7 +8945,7 @@ void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
|
||||
else
|
||||
Res = DAG.getNode(ISD::VECREDUCE_STRICT_FADD, dl, VT, Op1, Op2, SDFlags);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
if (SDFlags.hasAllowReassociation())
|
||||
Res = DAG.getNode(ISD::FMUL, dl, VT, Op1,
|
||||
DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2, SDFlags),
|
||||
@@ -8953,37 +8953,37 @@ void SelectionDAGBuilder::visitVectorReduce(const CallInst &I,
|
||||
else
|
||||
Res = DAG.getNode(ISD::VECREDUCE_STRICT_FMUL, dl, VT, Op1, Op2, SDFlags);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_MUL, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_smax:
|
||||
case Intrinsic::vector_reduce_smax:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_smin:
|
||||
case Intrinsic::vector_reduce_smin:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_umax:
|
||||
case Intrinsic::vector_reduce_umax:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_umin:
|
||||
case Intrinsic::vector_reduce_umin:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_fmax:
|
||||
case Intrinsic::vector_reduce_fmax:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_fmin:
|
||||
case Intrinsic::vector_reduce_fmin:
|
||||
Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags);
|
||||
break;
|
||||
default:
|
||||
|
||||
@@ -23,6 +23,7 @@
|
||||
#include "llvm/IR/Instruction.h"
|
||||
#include "llvm/IR/InstVisitor.h"
|
||||
#include "llvm/IR/IntrinsicInst.h"
|
||||
#include "llvm/IR/Intrinsics.h"
|
||||
#include "llvm/IR/IntrinsicsAArch64.h"
|
||||
#include "llvm/IR/IntrinsicsARM.h"
|
||||
#include "llvm/IR/IntrinsicsX86.h"
|
||||
@@ -717,18 +718,42 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
|
||||
}
|
||||
case 'e': {
|
||||
SmallVector<StringRef, 2> Groups;
|
||||
static const Regex R("^experimental.vector.reduce.([a-z]+)\\.[fi][0-9]+");
|
||||
static const Regex R("^experimental.vector.reduce.([a-z]+)\\.[a-z][0-9]+");
|
||||
if (R.match(Name, &Groups)) {
|
||||
Intrinsic::ID ID = Intrinsic::not_intrinsic;
|
||||
if (Groups[1] == "fadd")
|
||||
ID = Intrinsic::experimental_vector_reduce_v2_fadd;
|
||||
if (Groups[1] == "fmul")
|
||||
ID = Intrinsic::experimental_vector_reduce_v2_fmul;
|
||||
|
||||
Intrinsic::ID ID;
|
||||
ID = StringSwitch<Intrinsic::ID>(Groups[1])
|
||||
.Case("add", Intrinsic::vector_reduce_add)
|
||||
.Case("mul", Intrinsic::vector_reduce_mul)
|
||||
.Case("and", Intrinsic::vector_reduce_and)
|
||||
.Case("or", Intrinsic::vector_reduce_or)
|
||||
.Case("xor", Intrinsic::vector_reduce_xor)
|
||||
.Case("smax", Intrinsic::vector_reduce_smax)
|
||||
.Case("smin", Intrinsic::vector_reduce_smin)
|
||||
.Case("umax", Intrinsic::vector_reduce_umax)
|
||||
.Case("umin", Intrinsic::vector_reduce_umin)
|
||||
.Case("fmax", Intrinsic::vector_reduce_fmax)
|
||||
.Case("fmin", Intrinsic::vector_reduce_fmin)
|
||||
.Default(Intrinsic::not_intrinsic);
|
||||
if (ID != Intrinsic::not_intrinsic) {
|
||||
rename(F);
|
||||
auto Args = F->getFunctionType()->params();
|
||||
Type *Tys[] = {F->getFunctionType()->getReturnType(), Args[1]};
|
||||
NewFn = Intrinsic::getDeclaration(F->getParent(), ID, {Args[0]});
|
||||
return true;
|
||||
}
|
||||
}
|
||||
static const Regex R2(
|
||||
"^experimental.vector.reduce.v2.([a-z]+)\\.[fi][0-9]+");
|
||||
Groups.clear();
|
||||
if (R2.match(Name, &Groups)) {
|
||||
Intrinsic::ID ID = Intrinsic::not_intrinsic;
|
||||
if (Groups[1] == "fadd")
|
||||
ID = Intrinsic::vector_reduce_fadd;
|
||||
if (Groups[1] == "fmul")
|
||||
ID = Intrinsic::vector_reduce_fmul;
|
||||
if (ID != Intrinsic::not_intrinsic) {
|
||||
rename(F);
|
||||
auto Args = F->getFunctionType()->params();
|
||||
Type *Tys[] = {Args[1]};
|
||||
NewFn = Intrinsic::getDeclaration(F->getParent(), ID, Tys);
|
||||
return true;
|
||||
}
|
||||
@@ -3620,28 +3645,6 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
|
||||
DefaultCase();
|
||||
return;
|
||||
}
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul: {
|
||||
SmallVector<Value *, 2> Args;
|
||||
if (CI->isFast())
|
||||
Args.push_back(ConstantFP::get(CI->getOperand(0)->getType(), 1.0));
|
||||
else
|
||||
Args.push_back(CI->getOperand(0));
|
||||
Args.push_back(CI->getOperand(1));
|
||||
NewCall = Builder.CreateCall(NewFn, Args);
|
||||
cast<Instruction>(NewCall)->copyFastMathFlags(CI);
|
||||
break;
|
||||
}
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd: {
|
||||
SmallVector<Value *, 2> Args;
|
||||
if (CI->isFast())
|
||||
Args.push_back(Constant::getNullValue(CI->getOperand(0)->getType()));
|
||||
else
|
||||
Args.push_back(CI->getOperand(0));
|
||||
Args.push_back(CI->getOperand(1));
|
||||
NewCall = Builder.CreateCall(NewFn, Args);
|
||||
cast<Instruction>(NewCall)->copyFastMathFlags(CI);
|
||||
break;
|
||||
}
|
||||
case Intrinsic::arm_neon_vld1:
|
||||
case Intrinsic::arm_neon_vld2:
|
||||
case Intrinsic::arm_neon_vld3:
|
||||
|
||||
@@ -325,61 +325,53 @@ static CallInst *getReductionIntrinsic(IRBuilderBase *Builder, Intrinsic::ID ID,
|
||||
CallInst *IRBuilderBase::CreateFAddReduce(Value *Acc, Value *Src) {
|
||||
Module *M = GetInsertBlock()->getParent()->getParent();
|
||||
Value *Ops[] = {Acc, Src};
|
||||
Type *Tys[] = {Acc->getType(), Src->getType()};
|
||||
auto Decl = Intrinsic::getDeclaration(
|
||||
M, Intrinsic::experimental_vector_reduce_v2_fadd, Tys);
|
||||
auto Decl = Intrinsic::getDeclaration(M, Intrinsic::vector_reduce_fadd,
|
||||
{Src->getType()});
|
||||
return createCallHelper(Decl, Ops, this);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateFMulReduce(Value *Acc, Value *Src) {
|
||||
Module *M = GetInsertBlock()->getParent()->getParent();
|
||||
Value *Ops[] = {Acc, Src};
|
||||
Type *Tys[] = {Acc->getType(), Src->getType()};
|
||||
auto Decl = Intrinsic::getDeclaration(
|
||||
M, Intrinsic::experimental_vector_reduce_v2_fmul, Tys);
|
||||
auto Decl = Intrinsic::getDeclaration(M, Intrinsic::vector_reduce_fmul,
|
||||
{Src->getType()});
|
||||
return createCallHelper(Decl, Ops, this);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateAddReduce(Value *Src) {
|
||||
return getReductionIntrinsic(this, Intrinsic::experimental_vector_reduce_add,
|
||||
Src);
|
||||
return getReductionIntrinsic(this, Intrinsic::vector_reduce_add, Src);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateMulReduce(Value *Src) {
|
||||
return getReductionIntrinsic(this, Intrinsic::experimental_vector_reduce_mul,
|
||||
Src);
|
||||
return getReductionIntrinsic(this, Intrinsic::vector_reduce_mul, Src);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateAndReduce(Value *Src) {
|
||||
return getReductionIntrinsic(this, Intrinsic::experimental_vector_reduce_and,
|
||||
Src);
|
||||
return getReductionIntrinsic(this, Intrinsic::vector_reduce_and, Src);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateOrReduce(Value *Src) {
|
||||
return getReductionIntrinsic(this, Intrinsic::experimental_vector_reduce_or,
|
||||
Src);
|
||||
return getReductionIntrinsic(this, Intrinsic::vector_reduce_or, Src);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateXorReduce(Value *Src) {
|
||||
return getReductionIntrinsic(this, Intrinsic::experimental_vector_reduce_xor,
|
||||
Src);
|
||||
return getReductionIntrinsic(this, Intrinsic::vector_reduce_xor, Src);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateIntMaxReduce(Value *Src, bool IsSigned) {
|
||||
auto ID = IsSigned ? Intrinsic::experimental_vector_reduce_smax
|
||||
: Intrinsic::experimental_vector_reduce_umax;
|
||||
auto ID =
|
||||
IsSigned ? Intrinsic::vector_reduce_smax : Intrinsic::vector_reduce_umax;
|
||||
return getReductionIntrinsic(this, ID, Src);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateIntMinReduce(Value *Src, bool IsSigned) {
|
||||
auto ID = IsSigned ? Intrinsic::experimental_vector_reduce_smin
|
||||
: Intrinsic::experimental_vector_reduce_umin;
|
||||
auto ID =
|
||||
IsSigned ? Intrinsic::vector_reduce_smin : Intrinsic::vector_reduce_umin;
|
||||
return getReductionIntrinsic(this, ID, Src);
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateFPMaxReduce(Value *Src, bool NoNaN) {
|
||||
auto Rdx = getReductionIntrinsic(
|
||||
this, Intrinsic::experimental_vector_reduce_fmax, Src);
|
||||
auto Rdx = getReductionIntrinsic(this, Intrinsic::vector_reduce_fmax, Src);
|
||||
if (NoNaN) {
|
||||
FastMathFlags FMF;
|
||||
FMF.setNoNaNs();
|
||||
@@ -389,8 +381,7 @@ CallInst *IRBuilderBase::CreateFPMaxReduce(Value *Src, bool NoNaN) {
|
||||
}
|
||||
|
||||
CallInst *IRBuilderBase::CreateFPMinReduce(Value *Src, bool NoNaN) {
|
||||
auto Rdx = getReductionIntrinsic(
|
||||
this, Intrinsic::experimental_vector_reduce_fmin, Src);
|
||||
auto Rdx = getReductionIntrinsic(this, Intrinsic::vector_reduce_fmin, Src);
|
||||
if (NoNaN) {
|
||||
FastMathFlags FMF;
|
||||
FMF.setNoNaNs();
|
||||
|
||||
@@ -219,8 +219,8 @@ public:
|
||||
|
||||
bool shouldExpandReduction(const IntrinsicInst *II) const {
|
||||
switch (II->getIntrinsicID()) {
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
// We don't have legalization support for ordered FP reductions.
|
||||
return !II->getFastMathFlags().allowReassoc();
|
||||
|
||||
|
||||
@@ -195,8 +195,8 @@ public:
|
||||
|
||||
bool shouldExpandReduction(const IntrinsicInst *II) const {
|
||||
switch (II->getIntrinsicID()) {
|
||||
case Intrinsic::experimental_vector_reduce_v2_fadd:
|
||||
case Intrinsic::experimental_vector_reduce_v2_fmul:
|
||||
case Intrinsic::vector_reduce_fadd:
|
||||
case Intrinsic::vector_reduce_fmul:
|
||||
// We don't have legalization support for ordered FP reductions.
|
||||
return !II->getFastMathFlags().allowReassoc();
|
||||
default:
|
||||
|
||||
@@ -270,7 +270,7 @@ bool MVETailPredication::IsPredicatedVectorLoop() {
|
||||
case Intrinsic::uadd_sat:
|
||||
case Intrinsic::ssub_sat:
|
||||
case Intrinsic::usub_sat:
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
continue;
|
||||
case Intrinsic::fma:
|
||||
case Intrinsic::trunc:
|
||||
|
||||
@@ -1824,8 +1824,7 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
|
||||
}
|
||||
|
||||
auto m_AddRdx = [](Value *&Vec) {
|
||||
return m_OneUse(
|
||||
m_Intrinsic<Intrinsic::experimental_vector_reduce_add>(m_Value(Vec)));
|
||||
return m_OneUse(m_Intrinsic<Intrinsic::vector_reduce_add>(m_Value(Vec)));
|
||||
};
|
||||
Value *V0, *V1;
|
||||
if (match(Op0, m_AddRdx(V0)) && match(Op1, m_AddRdx(V1)) &&
|
||||
@@ -1833,8 +1832,8 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
|
||||
// Difference of sums is sum of differences:
|
||||
// add_rdx(V0) - add_rdx(V1) --> add_rdx(V0 - V1)
|
||||
Value *Sub = Builder.CreateSub(V0, V1);
|
||||
Value *Rdx = Builder.CreateIntrinsic(
|
||||
Intrinsic::experimental_vector_reduce_add, {Sub->getType()}, {Sub});
|
||||
Value *Rdx = Builder.CreateIntrinsic(Intrinsic::vector_reduce_add,
|
||||
{Sub->getType()}, {Sub});
|
||||
return replaceInstUsesWith(I, Rdx);
|
||||
}
|
||||
|
||||
@@ -2280,9 +2279,8 @@ Instruction *InstCombinerImpl::visitFSub(BinaryOperator &I) {
|
||||
}
|
||||
|
||||
auto m_FaddRdx = [](Value *&Sum, Value *&Vec) {
|
||||
return m_OneUse(
|
||||
m_Intrinsic<Intrinsic::experimental_vector_reduce_v2_fadd>(
|
||||
m_Value(Sum), m_Value(Vec)));
|
||||
return m_OneUse(m_Intrinsic<Intrinsic::vector_reduce_fadd>(m_Value(Sum),
|
||||
m_Value(Vec)));
|
||||
};
|
||||
Value *A0, *A1, *V0, *V1;
|
||||
if (match(Op0, m_FaddRdx(A0, V0)) && match(Op1, m_FaddRdx(A1, V1)) &&
|
||||
@@ -2290,9 +2288,8 @@ Instruction *InstCombinerImpl::visitFSub(BinaryOperator &I) {
|
||||
// Difference of sums is sum of differences:
|
||||
// add_rdx(A0, V0) - add_rdx(A1, V1) --> add_rdx(A0, V0 - V1) - A1
|
||||
Value *Sub = Builder.CreateFSubFMF(V0, V1, &I);
|
||||
Value *Rdx = Builder.CreateIntrinsic(
|
||||
Intrinsic::experimental_vector_reduce_v2_fadd,
|
||||
{A0->getType(), Sub->getType()}, {A0, Sub}, &I);
|
||||
Value *Rdx = Builder.CreateIntrinsic(Intrinsic::vector_reduce_fadd,
|
||||
{Sub->getType()}, {A0, Sub}, &I);
|
||||
return BinaryOperator::CreateFSubFMF(Rdx, A1, &I);
|
||||
}
|
||||
|
||||
|
||||
@@ -2995,7 +2995,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
|
||||
setOrigin(&I, getOrigin(&I, 0));
|
||||
}
|
||||
|
||||
// Instrument experimental.vector.reduce.or intrinsic.
|
||||
// Instrument vector.reduce.or intrinsic.
|
||||
// Valid (non-poisoned) set bits in the operand pull low the
|
||||
// corresponding shadow bits.
|
||||
void handleVectorReduceOrIntrinsic(IntrinsicInst &I) {
|
||||
@@ -3013,7 +3013,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
|
||||
setOrigin(&I, getOrigin(&I, 0));
|
||||
}
|
||||
|
||||
// Instrument experimental.vector.reduce.or intrinsic.
|
||||
// Instrument vector.reduce.and intrinsic.
|
||||
// Valid (non-poisoned) unset bits in the operand pull down the
|
||||
// corresponding shadow bits.
|
||||
void handleVectorReduceAndIntrinsic(IntrinsicInst &I) {
|
||||
@@ -3264,15 +3264,15 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
|
||||
case Intrinsic::masked_load:
|
||||
handleMaskedLoad(I);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_and:
|
||||
case Intrinsic::vector_reduce_and:
|
||||
handleVectorReduceAndIntrinsic(I);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_or:
|
||||
case Intrinsic::vector_reduce_or:
|
||||
handleVectorReduceOrIntrinsic(I);
|
||||
break;
|
||||
case Intrinsic::experimental_vector_reduce_add:
|
||||
case Intrinsic::experimental_vector_reduce_xor:
|
||||
case Intrinsic::experimental_vector_reduce_mul:
|
||||
case Intrinsic::vector_reduce_add:
|
||||
case Intrinsic::vector_reduce_xor:
|
||||
case Intrinsic::vector_reduce_mul:
|
||||
handleVectorReduceIntrinsic(I);
|
||||
break;
|
||||
case Intrinsic::x86_sse_stmxcsr:
|
||||
|
||||
@@ -2,278 +2,278 @@
|
||||
; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s --check-prefix=CODE
|
||||
|
||||
; COST-LABEL: add.i8.v8i8
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> %v)
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v)
|
||||
; CODE-LABEL: add.i8.v8i8
|
||||
; CODE: addv b0, v0.8b
|
||||
define i8 @add.i8.v8i8(<8 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: add.i8.v16i8
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %v)
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v)
|
||||
; CODE-LABEL: add.i8.v16i8
|
||||
; CODE: addv b0, v0.16b
|
||||
define i8 @add.i8.v16i8(<16 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: add.i16.v4i16
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> %v)
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v)
|
||||
; CODE-LABEL: add.i16.v4i16
|
||||
; CODE: addv h0, v0.4h
|
||||
define i16 @add.i16.v4i16(<4 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: add.i16.v8i16
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %v)
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v)
|
||||
; CODE-LABEL: add.i16.v8i16
|
||||
; CODE: addv h0, v0.8h
|
||||
define i16 @add.i16.v8i16(<8 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: add.i32.v4i32
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %v)
|
||||
; COST: Found an estimated cost of 1 for instruction: %r = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v)
|
||||
; CODE-LABEL: add.i32.v4i32
|
||||
; CODE: addv s0, v0.4s
|
||||
define i32 @add.i32.v4i32(<4 x i32> %v) {
|
||||
%r = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %v)
|
||||
%r = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umin.i8.v8i8
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)
|
||||
; CODE-LABEL: umin.i8.v8i8
|
||||
; CODE: uminv b0, v0.8b
|
||||
define i8 @umin.i8.v8i8(<8 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umin.i8.v16i8
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> %v)
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v)
|
||||
; CODE-LABEL: umin.i8.v16i8
|
||||
; CODE: uminv b0, v0.16b
|
||||
define i8 @umin.i8.v16i8(<16 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umin.i16.v4i16
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> %v)
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v)
|
||||
; CODE-LABEL: umin.i16.v4i16
|
||||
; CODE: uminv h0, v0.4h
|
||||
define i16 @umin.i16.v4i16(<4 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umin.i16.v8i16
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %v)
|
||||
; CODE-LABEL: umin.i16.v8i16
|
||||
; CODE: uminv h0, v0.8h
|
||||
define i16 @umin.i16.v8i16(<8 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umin.i32.v4i32
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %v)
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v)
|
||||
; CODE-LABEL: umin.i32.v4i32
|
||||
; CODE: uminv s0, v0.4s
|
||||
define i32 @umin.i32.v4i32(<4 x i32> %v) {
|
||||
%r = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %v)
|
||||
%r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umax.i8.v8i8
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v)
|
||||
; CODE-LABEL: umax.i8.v8i8
|
||||
; CODE: umaxv b0, v0.8b
|
||||
define i8 @umax.i8.v8i8(<8 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umax.i8.v16i8
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %v)
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %v)
|
||||
; CODE-LABEL: umax.i8.v16i8
|
||||
; CODE: umaxv b0, v0.16b
|
||||
define i8 @umax.i8.v16i8(<16 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umax.i16.v4i16
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> %v)
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v)
|
||||
; CODE-LABEL: umax.i16.v4i16
|
||||
; CODE: umaxv h0, v0.4h
|
||||
define i16 @umax.i16.v4i16(<4 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umax.i16.v8i16
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %v)
|
||||
; CODE-LABEL: umax.i16.v8i16
|
||||
; CODE: umaxv h0, v0.8h
|
||||
define i16 @umax.i16.v8i16(<8 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: umax.i32.v4i32
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %v)
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v)
|
||||
; CODE-LABEL: umax.i32.v4i32
|
||||
; CODE: umaxv s0, v0.4s
|
||||
define i32 @umax.i32.v4i32(<4 x i32> %v) {
|
||||
%r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %v)
|
||||
%r = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smin.i8.v8i8
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)
|
||||
; CODE-LABEL: smin.i8.v8i8
|
||||
; CODE: sminv b0, v0.8b
|
||||
define i8 @smin.i8.v8i8(<8 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smin.i8.v16i8
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> %v)
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v)
|
||||
; CODE-LABEL: smin.i8.v16i8
|
||||
; CODE: sminv b0, v0.16b
|
||||
define i8 @smin.i8.v16i8(<16 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smin.i16.v4i16
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> %v)
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)
|
||||
; CODE-LABEL: smin.i16.v4i16
|
||||
; CODE: sminv h0, v0.4h
|
||||
define i16 @smin.i16.v4i16(<4 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smin.i16.v8i16
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v)
|
||||
; CODE-LABEL: smin.i16.v8i16
|
||||
; CODE: sminv h0, v0.8h
|
||||
define i16 @smin.i16.v8i16(<8 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smin.i32.v4i32
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %v)
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v)
|
||||
; CODE-LABEL: smin.i32.v4i32
|
||||
; CODE: sminv s0, v0.4s
|
||||
define i32 @smin.i32.v4i32(<4 x i32> %v) {
|
||||
%r = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %v)
|
||||
%r = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smax.i8.v8i8
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)
|
||||
; CODE-LABEL: smax.i8.v8i8
|
||||
; CODE: smaxv b0, v0.8b
|
||||
define i8 @smax.i8.v8i8(<8 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smax.i8.v16i8
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %v)
|
||||
; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v)
|
||||
; CODE-LABEL: smax.i8.v16i8
|
||||
; CODE: smaxv b0, v0.16b
|
||||
define i8 @smax.i8.v16i8(<16 x i8> %v) {
|
||||
%r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %v)
|
||||
%r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smax.i16.v4i16
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> %v)
|
||||
; COST: Found an estimated cost of 64 for instruction: %r = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)
|
||||
; CODE-LABEL: smax.i16.v4i16
|
||||
; CODE: smaxv h0, v0.4h
|
||||
define i16 @smax.i16.v4i16(<4 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smax.i16.v8i16
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %v)
|
||||
; COST: Found an estimated cost of 216 for instruction: %r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v)
|
||||
; CODE-LABEL: smax.i16.v8i16
|
||||
; CODE: smaxv h0, v0.8h
|
||||
define i16 @smax.i16.v8i16(<8 x i16> %v) {
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %v)
|
||||
%r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: smax.i32.v4i32
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %v)
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v)
|
||||
; CODE-LABEL: smax.i32.v4i32
|
||||
; CODE: smaxv s0, v0.4s
|
||||
define i32 @smax.i32.v4i32(<4 x i32> %v) {
|
||||
%r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %v)
|
||||
%r = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; COST-LABEL: fmin.f32.v4f32
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call nnan float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %v)
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
||||
; CODE-LABEL: fmin.f32.v4f32
|
||||
; CODE: fminnmv s0, v0.4s
|
||||
define float @fmin.f32.v4f32(<4 x float> %v) {
|
||||
%r = call nnan float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %v)
|
||||
%r = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
; COST-LABEL: fmax.f32.v4f32
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call nnan float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %v)
|
||||
; COST: Found an estimated cost of 34 for instruction: %r = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
|
||||
; CODE-LABEL: fmax.f32.v4f32
|
||||
; CODE: fmaxnmv s0, v0.4s
|
||||
define float @fmax.f32.v4f32(<4 x float> %v) {
|
||||
%r = call nnan float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %v)
|
||||
%r = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
|
||||
@@ -8,155 +8,155 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; V8M-RECIP-LABEL: 'reduce_i64'
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-RECIP-LABEL: 'reduce_i64'
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 107 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 107 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-RECIP-LABEL: 'reduce_i64'
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 202 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 730 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 202 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 730 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; V8M-SIZE-LABEL: 'reduce_i64'
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-SIZE-LABEL: 'reduce_i64'
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-SIZE-LABEL: 'reduce_i64'
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; V8M-RECIP-LABEL: 'reduce_i32'
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 190 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 190 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; V8M-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-RECIP-LABEL: 'reduce_i32'
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 150 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 391 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 488 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 682 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1070 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 150 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 391 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 488 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 682 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1070 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-RECIP-LABEL: 'reduce_i32'
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 782 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 4120 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 5658 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 11806 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 36390 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 782 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 4120 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 5658 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 11806 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 36390 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; V8M-SIZE-LABEL: 'reduce_i32'
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-SIZE-LABEL: 'reduce_i32'
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-SIZE-LABEL: 'reduce_i32'
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v128i8(<128 x i8>)
|
||||
|
||||
@@ -5,171 +5,171 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i64'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i64'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i64'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i32'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i32'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i32'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i16'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i16'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i16'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i8'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i8'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i8'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v128i8(<128 x i8>)
|
||||
|
||||
@@ -5,171 +5,171 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i64'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i64'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i64'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i32'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i32'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i32'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i16'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i16'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i16'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i8'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i8'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i8'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v128i8(<128 x i8>)
|
||||
|
||||
@@ -5,171 +5,171 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i64'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i64'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i64'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i32'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i32'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i32'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i16'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i16'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i16'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i8'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i8'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i8'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v128i8(<128 x i8>)
|
||||
|
||||
@@ -5,171 +5,171 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i64'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 167 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i64'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 178 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i64'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 98 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 282 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 970 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i32'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i32'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i32'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 632 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i16'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i16'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 203 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 303 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i16'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 1176 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 2720 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; V8M-LABEL: 'reduce_i8'
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 91 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 187 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 379 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 763 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; V8M-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
||||
;
|
||||
; NEON-LABEL: 'reduce_i8'
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 395 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 493 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 689 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 1081 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; MVE-LABEL: 'reduce_i8'
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 788 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 4128 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 5668 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 11820 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 36412 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v128i8(<128 x i8>)
|
||||
|
||||
@@ -12,279 +12,279 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i64'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i64'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i64'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SLM-LABEL: 'reduce_i64'
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i32'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i32'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V32 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i32'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SLM-LABEL: 'reduce_i32'
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i16'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i16'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i16'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i16'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i16'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i16'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SLM-LABEL: 'reduce_i16'
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i8'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i8'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i8'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i8'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i8'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i8'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SLM-LABEL: 'reduce_i8'
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
; SLM-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v128i8(<128 x i8>)
|
||||
|
||||
@@ -10,258 +10,258 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i64'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i64'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i32'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i32'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i16'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i16'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i16'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i8'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i8'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i8'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i1(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i1'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i1'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i1'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i1'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i1'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i1'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
%V2 = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
%V4 = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
%V8 = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
%V16 = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
%V32 = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
%V64 = call i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
%V128 = call i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
%V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
|
||||
%V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
|
||||
%V4 = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> undef)
|
||||
%V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
|
||||
%V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
|
||||
%V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
|
||||
%V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
|
||||
%V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v128i8(<128 x i8>)
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v64i1(<64 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v128i1(<128 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v64i1(<64 x i1>)
|
||||
declare i1 @llvm.vector.reduce.and.v128i1(<128 x i1>)
|
||||
|
||||
@@ -11,83 +11,83 @@
|
||||
|
||||
define i32 @reduce_f64(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_f64'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.experimental.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call double @llvm.experimental.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call double @llvm.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_f64'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.experimental.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.experimental.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_f64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call double @llvm.experimental.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.experimental.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call double @llvm.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
%V2 = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
%V4 = call double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
%V8 = call double @llvm.experimental.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
%V16 = call double @llvm.experimental.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
%V1 = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> undef)
|
||||
%V2 = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> undef)
|
||||
%V4 = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> undef)
|
||||
%V8 = call double @llvm.vector.reduce.fmax.v8f64(<8 x double> undef)
|
||||
%V16 = call double @llvm.vector.reduce.fmax.v16f64(<16 x double> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_f32(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_f32'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call float @llvm.experimental.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_f32'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.experimental.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_f32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.experimental.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
%V2 = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
%V4 = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
%V8 = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
%V16 = call float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
%V32 = call float @llvm.experimental.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
%V1 = call float @llvm.vector.reduce.fmax.v1f32(<1 x float> undef)
|
||||
%V2 = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> undef)
|
||||
%V4 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> undef)
|
||||
%V8 = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> undef)
|
||||
%V16 = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> undef)
|
||||
%V32 = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v8f64(<8 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v16f64(<16 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v8f64(<8 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v16f64(<16 x double>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v32f32(<32 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v16f32(<16 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v32f32(<32 x float>)
|
||||
|
||||
@@ -11,83 +11,83 @@
|
||||
|
||||
define i32 @reduce_f64(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_f64'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.experimental.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call double @llvm.experimental.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call double @llvm.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_f64'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.experimental.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.experimental.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_f64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call double @llvm.experimental.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.experimental.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call double @llvm.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call double @llvm.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
%V2 = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
%V4 = call double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
%V8 = call double @llvm.experimental.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
%V16 = call double @llvm.experimental.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
%V1 = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> undef)
|
||||
%V2 = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> undef)
|
||||
%V4 = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> undef)
|
||||
%V8 = call double @llvm.vector.reduce.fmin.v8f64(<8 x double> undef)
|
||||
%V16 = call double @llvm.vector.reduce.fmin.v16f64(<16 x double> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_f32(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_f32'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call float @llvm.experimental.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_f32'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.experimental.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16 = call float @llvm.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_f32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.experimental.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call float @llvm.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call float @llvm.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
%V2 = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
%V4 = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
%V8 = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
%V16 = call float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
%V32 = call float @llvm.experimental.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
%V1 = call float @llvm.vector.reduce.fmin.v1f32(<1 x float> undef)
|
||||
%V2 = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> undef)
|
||||
%V4 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> undef)
|
||||
%V8 = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> undef)
|
||||
%V16 = call float @llvm.vector.reduce.fmin.v16f32(<16 x float> undef)
|
||||
%V32 = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v8f64(<8 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v16f64(<16 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v1f64(<1 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v8f64(<8 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v16f64(<16 x double>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v32f32(<32 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v1f32(<1 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v16f32(<16 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v32f32(<32 x float>)
|
||||
|
||||
@@ -10,276 +10,276 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i64'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8 = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V16 = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i64'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8 = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 73 for instruction: %V16 = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i64'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V8 = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V16 = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i64'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V16 = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i64'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %V8 = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V16 = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i64'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.mul.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i32'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 57 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 57 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i32'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 57 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 57 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE42-LABEL: 'reduce_i32'
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i32'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V16 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i32'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i16'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i16'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V32 = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i16'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i16'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i16'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i16'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.mul.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i8'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 89 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 137 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V4 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V16 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V32 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 89 for instruction: %V64 = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 137 for instruction: %V128 = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i8'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 144 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V4 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V16 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V32 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V64 = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 144 for instruction: %V128 = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i8'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 58 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V8 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V16 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V32 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 58 for instruction: %V64 = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V128 = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i8'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V16 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V32 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V64 = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V128 = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i8'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V32 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V128 = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i8'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V16 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V32 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V64 = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V128 = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.mul.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.mul.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.mul.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.mul.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.mul.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.mul.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.mul.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.mul.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.mul.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.mul.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.mul.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.mul.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.mul.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.mul.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.mul.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.mul.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.mul.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.mul.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.mul.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.mul.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.mul.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.mul.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.mul.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.mul.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.mul.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.mul.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.mul.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.mul.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.mul.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.mul.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.mul.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.mul.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.mul.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.mul.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.mul.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.mul.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.mul.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.mul.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.mul.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.mul.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.mul.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.mul.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.mul.v128i8(<128 x i8>)
|
||||
|
||||
@@ -10,258 +10,258 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i64'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i64'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i32'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i32'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i16'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i16'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i16'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i8'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i8'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i8'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i1(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i1'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i1'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i1'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i1'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i1'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i1'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
%V2 = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
%V4 = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
%V8 = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
%V16 = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
%V32 = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
%V64 = call i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
%V128 = call i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
%V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
|
||||
%V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
|
||||
%V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef)
|
||||
%V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
|
||||
%V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
|
||||
%V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
|
||||
%V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
|
||||
%V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v128i8(<128 x i8>)
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v64i1(<64 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v128i1(<128 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
|
||||
declare i1 @llvm.vector.reduce.or.v128i1(<128 x i1>)
|
||||
|
||||
@@ -11,322 +11,322 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i64'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i64'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE41-LABEL: 'reduce_i64'
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE42-LABEL: 'reduce_i64'
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i64'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i64'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i32'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i32'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i32'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i32'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i32'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i16'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i16'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i16'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i16'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i16'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i16'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i16'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i16'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i8'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i8'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i8'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i8'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i8'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i8'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i8'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i8'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smax.v128i8(<128 x i8>)
|
||||
|
||||
@@ -11,322 +11,322 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i64'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i64'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE41-LABEL: 'reduce_i64'
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE42-LABEL: 'reduce_i64'
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i64'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i64'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i32'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i32'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i32'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i32'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i32'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i16'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i16'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i16'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i16'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i16'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i16'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i16'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i16'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i8'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i8'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i8'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i8'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i8'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i8'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i8'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i8'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.smin.v128i8(<128 x i8>)
|
||||
|
||||
@@ -11,322 +11,322 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i64'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i64'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE41-LABEL: 'reduce_i64'
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE42-LABEL: 'reduce_i64'
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i64'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i64'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i32'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i32'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i32'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i32'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i32'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i16'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i16'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i16'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i16'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i16'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i16'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i16'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i16'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i8'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i8'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i8'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i8'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i8'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i8'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i8'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i8'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umax.v128i8(<128 x i8>)
|
||||
|
||||
@@ -11,322 +11,322 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i64'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i64'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE41-LABEL: 'reduce_i64'
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 74 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE42-LABEL: 'reduce_i64'
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i64'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i64'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i32'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i32'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i32'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i32'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i32'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i16'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i16'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i16'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i16'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i16'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i16'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i16'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i16'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i8'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i8'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE4-LABEL: 'reduce_i8'
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; SSE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i8'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i8'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i8'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i8'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i8'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.umin.v128i8(<128 x i8>)
|
||||
|
||||
@@ -10,280 +10,280 @@
|
||||
|
||||
define i32 @reduce_i64(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i64'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i64'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i64'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
%V1 = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> undef)
|
||||
%V2 = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> undef)
|
||||
%V4 = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> undef)
|
||||
%V8 = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> undef)
|
||||
%V16 = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i32(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i32'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i32'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i32'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
%V2 = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> undef)
|
||||
%V4 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> undef)
|
||||
%V8 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> undef)
|
||||
%V16 = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> undef)
|
||||
%V32 = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i16(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i16'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i16'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i16'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.experimental.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i16 @llvm.experimental.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
%V2 = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> undef)
|
||||
%V4 = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> undef)
|
||||
%V8 = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> undef)
|
||||
%V16 = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> undef)
|
||||
%V32 = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> undef)
|
||||
%V64 = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i8(i32 %arg) {
|
||||
; SSE-LABEL: 'reduce_i8'
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX-LABEL: 'reduce_i8'
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512-LABEL: 'reduce_i8'
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.experimental.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.experimental.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V2 = call i8 @llvm.experimental.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.experimental.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
%V2 = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> undef)
|
||||
%V4 = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> undef)
|
||||
%V8 = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> undef)
|
||||
%V16 = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> undef)
|
||||
%V32 = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> undef)
|
||||
%V64 = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> undef)
|
||||
%V128 = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define i32 @reduce_i1(i32 %arg) {
|
||||
; SSE2-LABEL: 'reduce_i1'
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSSE3-LABEL: 'reduce_i1'
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; SSE42-LABEL: 'reduce_i1'
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX1-LABEL: 'reduce_i1'
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX2-LABEL: 'reduce_i1'
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512F-LABEL: 'reduce_i1'
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 134 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 134 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512BW-LABEL: 'reduce_i1'
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 326 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 775 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 776 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 326 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 775 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 776 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
; AVX512DQ-LABEL: 'reduce_i1'
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 134 for instruction: %V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 134 for instruction: %V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
|
||||
;
|
||||
%V1 = call i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
%V2 = call i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
%V4 = call i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
%V8 = call i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
%V16 = call i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
%V32 = call i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
%V64 = call i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
%V128 = call i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
%V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
|
||||
%V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
|
||||
%V4 = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> undef)
|
||||
%V8 = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> undef)
|
||||
%V16 = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> undef)
|
||||
%V32 = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> undef)
|
||||
%V64 = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> undef)
|
||||
%V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v32i32(<32 x i32>)
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v2i16(<2 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v32i16(<32 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v64i16(<64 x i16>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v2i8(<2 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v64i8(<64 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v128i8(<128 x i8>)
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v1i1(<1 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v2i1(<2 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v4i1(<4 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v8i1(<8 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v16i1(<16 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v32i1(<32 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v64i1(<64 x i1>)
|
||||
declare i1 @llvm.experimental.vector.reduce.xor.v128i1(<128 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v64i1(<64 x i1>)
|
||||
declare i1 @llvm.vector.reduce.xor.v128i1(<128 x i1>)
|
||||
|
||||
@@ -1,34 +1,34 @@
|
||||
; RUN: not opt -S < %s 2>&1 | FileCheck %s
|
||||
|
||||
; CHECK: Intrinsic has incorrect argument type!
|
||||
; CHECK-NEXT: float (double, <2 x double>)* @llvm.experimental.vector.reduce.v2.fadd.f32.f64.v2f64
|
||||
; CHECK: Intrinsic has incorrect return type!
|
||||
; CHECK-NEXT: float (double, <2 x double>)* @llvm.vector.reduce.fadd.f32.f64.v2f64
|
||||
define float @fadd_invalid_scalar_res(double %acc, <2 x double> %in) {
|
||||
%res = call float @llvm.experimental.vector.reduce.v2.fadd.f32.f64.v2f64(double %acc, <2 x double> %in)
|
||||
%res = call float @llvm.vector.reduce.fadd.f32.f64.v2f64(double %acc, <2 x double> %in)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
; CHECK: Intrinsic has incorrect argument type!
|
||||
; CHECK-NEXT: double (float, <2 x double>)* @llvm.experimental.vector.reduce.v2.fadd.f64.f32.v2f64
|
||||
; CHECK-NEXT: double (float, <2 x double>)* @llvm.vector.reduce.fadd.f64.f32.v2f64
|
||||
define double @fadd_invalid_scalar_start(float %acc, <2 x double> %in) {
|
||||
%res = call double @llvm.experimental.vector.reduce.v2.fadd.f64.f32.v2f64(float %acc, <2 x double> %in)
|
||||
%res = call double @llvm.vector.reduce.fadd.f64.f32.v2f64(float %acc, <2 x double> %in)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
; CHECK: Intrinsic has incorrect argument type!
|
||||
; CHECK-NEXT: <2 x double> (double, <2 x double>)* @llvm.experimental.vector.reduce.v2.fadd.v2f64.f64.v2f64
|
||||
; CHECK: Intrinsic has incorrect return type!
|
||||
; CHECK-NEXT: <2 x double> (double, <2 x double>)* @llvm.vector.reduce.fadd.v2f64.f64.v2f64
|
||||
define <2 x double> @fadd_invalid_vector_res(double %acc, <2 x double> %in) {
|
||||
%res = call <2 x double> @llvm.experimental.vector.reduce.v2.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in)
|
||||
%res = call <2 x double> @llvm.vector.reduce.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
; CHECK: Intrinsic has incorrect argument type!
|
||||
; CHECK-NEXT: double (<2 x double>, <2 x double>)* @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64.v2f64
|
||||
; CHECK-NEXT: double (<2 x double>, <2 x double>)* @llvm.vector.reduce.fadd.f64.v2f64.v2f64
|
||||
define double @fadd_invalid_vector_start(<2 x double> %in, <2 x double> %acc) {
|
||||
%res = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in)
|
||||
%res = call double @llvm.vector.reduce.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.f64.v2f64(double %acc, <2 x double> %in)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.f32.v2f64(float %acc, <2 x double> %in)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in)
|
||||
declare <2 x double> @llvm.experimental.vector.reduce.v2.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in)
|
||||
declare float @llvm.vector.reduce.fadd.f32.f64.v2f64(double %acc, <2 x double> %in)
|
||||
declare double @llvm.vector.reduce.fadd.f64.f32.v2f64(float %acc, <2 x double> %in)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v2f64.v2f64(<2 x double> %acc, <2 x double> %in)
|
||||
declare <2 x double> @llvm.vector.reduce.fadd.v2f64.f64.v2f64(double %acc, <2 x double> %in)
|
||||
|
||||
@@ -1,64 +1,130 @@
|
||||
; RUN: opt -S < %s | FileCheck %s
|
||||
; RUN: llvm-dis < %s.bc | FileCheck %s
|
||||
|
||||
define float @fadd_acc(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fadd_acc
|
||||
; CHECK: %res = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %acc, <4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.fadd.f32.v4f32(float %acc, <4 x float> %in)
|
||||
|
||||
define float @fadd_v2(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fadd_v2
|
||||
; CHECK: %res = call float @llvm.vector.reduce.fadd.v4f32(float %acc, <4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %acc, <4 x float> %in)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
define float @fadd_undef(<4 x float> %in) {
|
||||
; CHECK-LABEL: @fadd_undef
|
||||
; CHECK: %res = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float undef, <4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.fadd.f32.v4f32(float undef, <4 x float> %in)
|
||||
define float @fadd_v2_fast(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fadd_v2_fast
|
||||
; CHECK: %res = call fast float @llvm.vector.reduce.fadd.v4f32(float %acc, <4 x float> %in)
|
||||
%res = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %acc, <4 x float> %in)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
define float @fadd_fast_acc(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fadd_fast_acc
|
||||
; CHECK: %res = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %in)
|
||||
%res = call fast float @llvm.experimental.vector.reduce.fadd.f32.v4f32(float %acc, <4 x float> %in)
|
||||
define float @fmul_v2(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fmul_v2
|
||||
; CHECK: %res = call float @llvm.vector.reduce.fmul.v4f32(float %acc, <4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %acc, <4 x float> %in)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
define float @fadd_fast_undef(<4 x float> %in) {
|
||||
; CHECK-LABEL: @fadd_fast_undef
|
||||
; CHECK: %res = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %in)
|
||||
%res = call fast float @llvm.experimental.vector.reduce.fadd.f32.v4f32(float undef, <4 x float> %in)
|
||||
define float @fmul_v2_fast(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fmul_v2_fast
|
||||
; CHECK: %res = call fast float @llvm.vector.reduce.fmul.v4f32(float %acc, <4 x float> %in)
|
||||
%res = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %acc, <4 x float> %in)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
define float @fmul_acc(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fmul_acc
|
||||
; CHECK: %res = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %acc, <4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.fmul.f32.v4f32(float %acc, <4 x float> %in)
|
||||
define float @fmin(<4 x float> %in) {
|
||||
; CHECK-LABEL: @fmin
|
||||
; CHECK: %res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %in)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
define float @fmul_undef(<4 x float> %in) {
|
||||
; CHECK-LABEL: @fmul_undef
|
||||
; CHECK: %res = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float undef, <4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.fmul.f32.v4f32(float undef, <4 x float> %in)
|
||||
define float @fmax(<4 x float> %in) {
|
||||
; CHECK-LABEL: @fmax
|
||||
; CHECK: %res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %in)
|
||||
%res = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %in)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
define float @fmul_fast_acc(<4 x float> %in, float %acc) {
|
||||
; CHECK-LABEL: @fmul_fast_acc
|
||||
; CHECK: %res = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float 1.000000e+00, <4 x float> %in)
|
||||
%res = call fast float @llvm.experimental.vector.reduce.fmul.f32.v4f32(float %acc, <4 x float> %in)
|
||||
ret float %res
|
||||
define i32 @and(<4 x i32> %in) {
|
||||
; CHECK-LABEL: @and
|
||||
; CHECK: %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %in)
|
||||
%res = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %in)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define float @fmul_fast_undef(<4 x float> %in) {
|
||||
; CHECK-LABEL: @fmul_fast_undef
|
||||
; CHECK: %res = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float 1.000000e+00, <4 x float> %in)
|
||||
%res = call fast float @llvm.experimental.vector.reduce.fmul.f32.v4f32(float undef, <4 x float> %in)
|
||||
ret float %res
|
||||
define i32 @or(<4 x i32> %in) {
|
||||
; CHECK-LABEL: @or
|
||||
; CHECK: %res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %in)
|
||||
%res = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %in)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
|
||||
; CHECK: declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
define i32 @xor(<4 x i32> %in) {
|
||||
; CHECK-LABEL: @xor
|
||||
; CHECK: %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %in)
|
||||
%res = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %in)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @smin(<4 x i32> %in) {
|
||||
; CHECK-LABEL: @smin
|
||||
; CHECK: %res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %in)
|
||||
%res = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %in)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @smax(<4 x i32> %in) {
|
||||
; CHECK-LABEL: @smax
|
||||
; CHECK: %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %in)
|
||||
%res = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %in)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @umin(<4 x i32> %in) {
|
||||
; CHECK-LABEL: @umin
|
||||
; CHECK: %res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %in)
|
||||
%res = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %in)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define i32 @umax(<4 x i32> %in) {
|
||||
; CHECK-LABEL: @umax
|
||||
; CHECK: %res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %in)
|
||||
%res = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %in)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float, <4 x float>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
; CHECK: declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
; CHECK: declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32>)
|
||||
; CHECK: declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
|
||||
; CHECK: declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
; CHECK: declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
; CHECK: declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
; CHECK: declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
; CHECK: declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
; CHECK: declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmul.f32.v4f32(float, <4 x float>)
|
||||
; CHECK: declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float, <4 x float>)
|
||||
|
||||
Binary file not shown.
@@ -1,16 +1,16 @@
|
||||
; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic | FileCheck %s
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
|
||||
define i8 @add_B(<16 x i8>* %arr) {
|
||||
; CHECK-LABEL: add_B
|
||||
; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b
|
||||
%bin.rdx = load <16 x i8>, <16 x i8>* %arr
|
||||
%r = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %bin.rdx)
|
||||
%r = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %bin.rdx)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -18,7 +18,7 @@ define i16 @add_H(<8 x i16>* %arr) {
|
||||
; CHECK-LABEL: add_H
|
||||
; CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h
|
||||
%bin.rdx = load <8 x i16>, <8 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %bin.rdx)
|
||||
%r = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %bin.rdx)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
@@ -26,7 +26,7 @@ define i32 @add_S( <4 x i32>* %arr) {
|
||||
; CHECK-LABEL: add_S
|
||||
; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
||||
%bin.rdx = load <4 x i32>, <4 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)
|
||||
%r = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -35,11 +35,11 @@ define i64 @add_D(<2 x i64>* %arr) {
|
||||
; CHECK-NOT: addv
|
||||
; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
|
||||
%bin.rdx = load <2 x i64>, <2 x i64>* %arr
|
||||
%r = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %bin.rdx)
|
||||
%r = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %bin.rdx)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
|
||||
define i32 @oversized_ADDV_256(i8* noalias nocapture readonly %arg1, i8* noalias nocapture readonly %arg2) {
|
||||
; CHECK-LABEL: oversized_ADDV_256
|
||||
@@ -55,16 +55,16 @@ entry:
|
||||
%7 = icmp slt <8 x i32> %6, zeroinitializer
|
||||
%8 = sub nsw <8 x i32> zeroinitializer, %6
|
||||
%9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
|
||||
%r = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %9)
|
||||
%r = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %9)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
|
||||
define i32 @oversized_ADDV_512(<16 x i32>* %arr) {
|
||||
; CHECK-LABEL: oversized_ADDV_512
|
||||
; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
||||
%bin.rdx = load <16 x i32>, <16 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %bin.rdx)
|
||||
%r = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %bin.rdx)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -2,28 +2,28 @@
|
||||
|
||||
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
|
||||
; CHECK-LABEL: smax_B
|
||||
; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
|
||||
define i8 @smax_B(<16 x i8>* nocapture readonly %arr) {
|
||||
%arr.load = load <16 x i8>, <16 x i8>* %arr
|
||||
%r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %arr.load)
|
||||
%r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %arr.load)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -31,7 +31,7 @@ define i8 @smax_B(<16 x i8>* nocapture readonly %arr) {
|
||||
; CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
|
||||
define i16 @smax_H(<8 x i16>* nocapture readonly %arr) {
|
||||
%arr.load = load <8 x i16>, <8 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
@@ -39,7 +39,7 @@ define i16 @smax_H(<8 x i16>* nocapture readonly %arr) {
|
||||
; CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
||||
define i32 @smax_S(<4 x i32> * nocapture readonly %arr) {
|
||||
%arr.load = load <4 x i32>, <4 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -47,7 +47,7 @@ define i32 @smax_S(<4 x i32> * nocapture readonly %arr) {
|
||||
; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
|
||||
define i8 @umax_B(<16 x i8>* nocapture readonly %arr) {
|
||||
%arr.load = load <16 x i8>, <16 x i8>* %arr
|
||||
%r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %arr.load)
|
||||
%r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %arr.load)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -55,7 +55,7 @@ define i8 @umax_B(<16 x i8>* nocapture readonly %arr) {
|
||||
; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
|
||||
define i16 @umax_H(<8 x i16>* nocapture readonly %arr) {
|
||||
%arr.load = load <8 x i16>, <8 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
@@ -63,7 +63,7 @@ define i16 @umax_H(<8 x i16>* nocapture readonly %arr) {
|
||||
; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
||||
define i32 @umax_S(<4 x i32>* nocapture readonly %arr) {
|
||||
%arr.load = load <4 x i32>, <4 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -71,7 +71,7 @@ define i32 @umax_S(<4 x i32>* nocapture readonly %arr) {
|
||||
; CHECK: sminv {{b[0-9]+}}, {{v[0-9]+}}.16b
|
||||
define i8 @smin_B(<16 x i8>* nocapture readonly %arr) {
|
||||
%arr.load = load <16 x i8>, <16 x i8>* %arr
|
||||
%r = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> %arr.load)
|
||||
%r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %arr.load)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -79,7 +79,7 @@ define i8 @smin_B(<16 x i8>* nocapture readonly %arr) {
|
||||
; CHECK: sminv {{h[0-9]+}}, {{v[0-9]+}}.8h
|
||||
define i16 @smin_H(<8 x i16>* nocapture readonly %arr) {
|
||||
%arr.load = load <8 x i16>, <8 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
@@ -87,7 +87,7 @@ define i16 @smin_H(<8 x i16>* nocapture readonly %arr) {
|
||||
; CHECK: sminv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
||||
define i32 @smin_S(<4 x i32>* nocapture readonly %arr) {
|
||||
%arr.load = load <4 x i32>, <4 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -95,7 +95,7 @@ define i32 @smin_S(<4 x i32>* nocapture readonly %arr) {
|
||||
; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
|
||||
define i8 @umin_B(<16 x i8>* nocapture readonly %arr) {
|
||||
%arr.load = load <16 x i8>, <16 x i8>* %arr
|
||||
%r = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> %arr.load)
|
||||
%r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %arr.load)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -103,7 +103,7 @@ define i8 @umin_B(<16 x i8>* nocapture readonly %arr) {
|
||||
; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
|
||||
define i16 @umin_H(<8 x i16>* nocapture readonly %arr) {
|
||||
%arr.load = load <8 x i16>, <8 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
@@ -111,7 +111,7 @@ define i16 @umin_H(<8 x i16>* nocapture readonly %arr) {
|
||||
; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
||||
define i32 @umin_S(<4 x i32>* nocapture readonly %arr) {
|
||||
%arr.load = load <4 x i32>, <4 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -119,7 +119,7 @@ define i32 @umin_S(<4 x i32>* nocapture readonly %arr) {
|
||||
; CHECK: fmaxnmv
|
||||
define float @fmaxnm_S(<4 x float>* nocapture readonly %arr) {
|
||||
%arr.load = load <4 x float>, <4 x float>* %arr
|
||||
%r = call nnan float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %arr.load)
|
||||
%r = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %arr.load)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -127,22 +127,22 @@ define float @fmaxnm_S(<4 x float>* nocapture readonly %arr) {
|
||||
; CHECK: fminnmv
|
||||
define float @fminnm_S(<4 x float>* nocapture readonly %arr) {
|
||||
%arr.load = load <4 x float>, <4 x float>* %arr
|
||||
%r = call nnan float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %arr.load)
|
||||
%r = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %arr.load)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>)
|
||||
|
||||
define i16 @oversized_umax_256(<16 x i16>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_umax_256
|
||||
; CHECK: umax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
|
||||
; CHECK: umaxv {{h[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i16>, <16 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umax.v16i16(<16 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)
|
||||
|
||||
define i32 @oversized_umax_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_umax_512
|
||||
@@ -151,22 +151,22 @@ define i32 @oversized_umax_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-NEXT: umax [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i32>, <16 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)
|
||||
|
||||
define i16 @oversized_umin_256(<16 x i16>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_umin_256
|
||||
; CHECK: umin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
|
||||
; CHECK: uminv {{h[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i16>, <16 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.umin.v16i16(<16 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
|
||||
|
||||
define i32 @oversized_umin_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_umin_512
|
||||
@@ -175,22 +175,22 @@ define i32 @oversized_umin_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-NEXT: umin [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i32>, <16 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.umin.v16i32(<16 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>)
|
||||
|
||||
define i16 @oversized_smax_256(<16 x i16>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_smax_256
|
||||
; CHECK: smax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
|
||||
; CHECK: smaxv {{h[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i16>, <16 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smax.v16i16(<16 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
|
||||
|
||||
define i32 @oversized_smax_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_smax_512
|
||||
@@ -199,22 +199,22 @@ define i32 @oversized_smax_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-NEXT: smax [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i32>, <16 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.smax.v16i32(<16 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)
|
||||
|
||||
define i16 @oversized_smin_256(<16 x i16>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_smin_256
|
||||
; CHECK: smin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
|
||||
; CHECK: sminv {{h[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i16>, <16 x i16>* %arr
|
||||
%r = call i16 @llvm.experimental.vector.reduce.smin.v16i16(<16 x i16> %arr.load)
|
||||
%r = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %arr.load)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)
|
||||
|
||||
define i32 @oversized_smin_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-LABEL: oversized_smin_512
|
||||
@@ -223,6 +223,6 @@ define i32 @oversized_smin_512(<16 x i32>* nocapture readonly %arr) {
|
||||
; CHECK-NEXT: smin [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
; CHECK-NEXT: sminv {{s[0-9]+}}, [[V0]]
|
||||
%arr.load = load <16 x i32>, <16 x i32>* %arr
|
||||
%r = call i32 @llvm.experimental.vector.reduce.smin.v16i32(<16 x i32> %arr.load)
|
||||
%r = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %arr.load)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -141,7 +141,7 @@ define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
|
||||
|
||||
define i16 @uabdl8h_rdx(<16 x i8>* %a, <16 x i8>* %b) {
|
||||
; CHECK-LABEL: uabdl8h_rdx
|
||||
@@ -155,11 +155,11 @@ define i16 @uabdl8h_rdx(<16 x i8>* %a, <16 x i8>* %b) {
|
||||
%abcmp = icmp slt <16 x i16> %abdiff, zeroinitializer
|
||||
%ababs = sub nsw <16 x i16> zeroinitializer, %abdiff
|
||||
%absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
|
||||
%reduced_v = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %absel)
|
||||
%reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
|
||||
ret i16 %reduced_v
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
|
||||
define i32 @uabdl4s_rdx(<8 x i16>* %a, <8 x i16>* %b) {
|
||||
; CHECK-LABEL: uabdl4s_rdx
|
||||
@@ -173,11 +173,11 @@ define i32 @uabdl4s_rdx(<8 x i16>* %a, <8 x i16>* %b) {
|
||||
%abcmp = icmp slt <8 x i32> %abdiff, zeroinitializer
|
||||
%ababs = sub nsw <8 x i32> zeroinitializer, %abdiff
|
||||
%absel = select <8 x i1> %abcmp, <8 x i32> %ababs, <8 x i32> %abdiff
|
||||
%reduced_v = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %absel)
|
||||
%reduced_v = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %absel)
|
||||
ret i32 %reduced_v
|
||||
}
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
|
||||
define i64 @uabdl2d_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {
|
||||
; CHECK: uabdl2d_rdx
|
||||
@@ -191,7 +191,7 @@ define i64 @uabdl2d_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {
|
||||
%abcmp = icmp slt <4 x i64> %abdiff, zeroinitializer
|
||||
%ababs = sub nsw <4 x i64> zeroinitializer, %abdiff
|
||||
%absel = select <4 x i1> %abcmp, <4 x i64> %ababs, <4 x i64> %abdiff
|
||||
%reduced_v = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %absel)
|
||||
%reduced_v = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %absel)
|
||||
ret i64 %reduced_v
|
||||
}
|
||||
|
||||
|
||||
@@ -205,7 +205,7 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
|
||||
define i32 @test_udot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
|
||||
entry:
|
||||
@@ -218,7 +218,7 @@ entry:
|
||||
%4 = load <8 x i8>, <8 x i8>* %3
|
||||
%5 = zext <8 x i8> %4 to <8 x i32>
|
||||
%6 = mul nuw nsw <8 x i32> %5, %2
|
||||
%7 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %6)
|
||||
%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
|
||||
ret i32 %7
|
||||
}
|
||||
|
||||
@@ -233,11 +233,11 @@ entry:
|
||||
%4 = load <8 x i8>, <8 x i8>* %3
|
||||
%5 = sext <8 x i8> %4 to <8 x i32>
|
||||
%6 = mul nsw <8 x i32> %5, %2
|
||||
%7 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %6)
|
||||
%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
|
||||
ret i32 %7
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
|
||||
define i32 @test_udot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
|
||||
entry:
|
||||
@@ -250,7 +250,7 @@ entry:
|
||||
%4 = load <16 x i8>, <16 x i8>* %3
|
||||
%5 = zext <16 x i8> %4 to <16 x i32>
|
||||
%6 = mul nuw nsw <16 x i32> %5, %2
|
||||
%7 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %6)
|
||||
%7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
|
||||
%op.extra = add i32 %7, %sum
|
||||
ret i32 %op.extra
|
||||
}
|
||||
@@ -265,7 +265,7 @@ entry:
|
||||
%0 = bitcast i8* %a1 to <16 x i8>*
|
||||
%1 = load <16 x i8>, <16 x i8>* %0
|
||||
%2 = zext <16 x i8> %1 to <16 x i32>
|
||||
%3 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %2)
|
||||
%3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
@@ -280,7 +280,7 @@ entry:
|
||||
%4 = load <16 x i8>, <16 x i8>* %3
|
||||
%5 = sext <16 x i8> %4 to <16 x i32>
|
||||
%6 = mul nsw <16 x i32> %5, %2
|
||||
%7 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %6)
|
||||
%7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
|
||||
%op.extra = add nsw i32 %7, %sum
|
||||
ret i32 %op.extra
|
||||
}
|
||||
@@ -295,6 +295,6 @@ entry:
|
||||
%0 = bitcast i8* %a1 to <16 x i8>*
|
||||
%1 = load <16 x i8>, <16 x i8>* %0
|
||||
%2 = sext <16 x i8> %1 to <16 x i32>
|
||||
%3 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %2)
|
||||
%3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
@@ -29,7 +29,7 @@ define half @fmaxv_v4f16(<4 x half> %a) #0 {
|
||||
; CHECK-LABEL: fmaxv_v4f16:
|
||||
; CHECK: fmaxnmv h0, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %a)
|
||||
%res = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -38,7 +38,7 @@ define half @fmaxv_v8f16(<8 x half> %a) #0 {
|
||||
; CHECK-LABEL: fmaxv_v8f16:
|
||||
; CHECK: fmaxnmv h0, v0.8h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call half @llvm.experimental.vector.reduce.fmax.v8f16(<8 x half> %a)
|
||||
%res = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -49,7 +49,7 @@ define half @fmaxv_v16f16(<16 x half>* %a) #0 {
|
||||
; VBITS_GE_256-NEXT: fmaxnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_256-NEXT: ret
|
||||
%op = load <16 x half>, <16 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmax.v16f16(<16 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -60,7 +60,7 @@ define half @fmaxv_v32f16(<32 x half>* %a) #0 {
|
||||
; VBITS_GE_512-NEXT: fmaxnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op = load <32 x half>, <32 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmax.v32f16(<32 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmax.v32f16(<32 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -71,7 +71,7 @@ define half @fmaxv_v64f16(<64 x half>* %a) #0 {
|
||||
; VBITS_GE_1024-NEXT: fmaxnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op = load <64 x half>, <64 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmax.v64f16(<64 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmax.v64f16(<64 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -82,7 +82,7 @@ define half @fmaxv_v128f16(<128 x half>* %a) #0 {
|
||||
; VBITS_GE_2048-NEXT: fmaxnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op = load <128 x half>, <128 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmax.v128f16(<128 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -91,7 +91,7 @@ define float @fmaxv_v2f32(<2 x float> %a) #0 {
|
||||
; CHECK-LABEL: fmaxv_v2f32:
|
||||
; CHECK: fmaxnmp s0, v0.2s
|
||||
; CHECK: ret
|
||||
%res = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %a)
|
||||
%res = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -100,7 +100,7 @@ define float @fmaxv_v4f32(<4 x float> %a) #0 {
|
||||
; CHECK-LABEL: fmaxv_v4f32:
|
||||
; CHECK: fmaxnmv s0, v0.4s
|
||||
; CHECK: ret
|
||||
%res = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %a)
|
||||
%res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -111,7 +111,7 @@ define float @fmaxv_v8f32(<8 x float>* %a) #0 {
|
||||
; VBITS_GE_256-NEXT: fmaxnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_256-NEXT: ret
|
||||
%op = load <8 x float>, <8 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -122,7 +122,7 @@ define float @fmaxv_v16f32(<16 x float>* %a) #0 {
|
||||
; VBITS_GE_512-NEXT: fmaxnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op = load <16 x float>, <16 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -133,7 +133,7 @@ define float @fmaxv_v32f32(<32 x float>* %a) #0 {
|
||||
; VBITS_GE_1024-NEXT: fmaxnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op = load <32 x float>, <32 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmax.v32f32(<32 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmax.v32f32(<32 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -144,7 +144,7 @@ define float @fmaxv_v64f32(<64 x float>* %a) #0 {
|
||||
; VBITS_GE_2048-NEXT: fmaxnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op = load <64 x float>, <64 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmax.v64f32(<64 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmax.v64f32(<64 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -153,7 +153,7 @@ define double @fmaxv_v1f64(<1 x double> %a) #0 {
|
||||
; CHECK-LABEL: fmaxv_v1f64:
|
||||
; CHECK-NOT: fmax
|
||||
; CHECK: ret
|
||||
%res = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
%res = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -162,7 +162,7 @@ define double @fmaxv_v2f64(<2 x double> %a) #0 {
|
||||
; CHECK-LABEL: fmaxv_v2f64:
|
||||
; CHECK: fmaxnmp d0, v0.2d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %a)
|
||||
%res = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -173,7 +173,7 @@ define double @fmaxv_v4f64(<4 x double>* %a) #0 {
|
||||
; VBITS_GE_256-NEXT: fmaxnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_256-NEXT: ret
|
||||
%op = load <4 x double>, <4 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -184,7 +184,7 @@ define double @fmaxv_v8f64(<8 x double>* %a) #0 {
|
||||
; VBITS_GE_512-NEXT: fmaxnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op = load <8 x double>, <8 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmax.v8f64(<8 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmax.v8f64(<8 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -195,7 +195,7 @@ define double @fmaxv_v16f64(<16 x double>* %a) #0 {
|
||||
; VBITS_GE_1024-NEXT: fmaxnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op = load <16 x double>, <16 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmax.v16f64(<16 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmax.v16f64(<16 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -206,7 +206,7 @@ define double @fmaxv_v32f64(<32 x double>* %a) #0 {
|
||||
; VBITS_GE_2048-NEXT: fmaxnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op = load <32 x double>, <32 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmax.v32f64(<32 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -219,7 +219,7 @@ define half @fminv_v4f16(<4 x half> %a) #0 {
|
||||
; CHECK-LABEL: fminv_v4f16:
|
||||
; CHECK: fminnmv h0, v0.4h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %a)
|
||||
%res = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -228,7 +228,7 @@ define half @fminv_v8f16(<8 x half> %a) #0 {
|
||||
; CHECK-LABEL: fminv_v8f16:
|
||||
; CHECK: fminnmv h0, v0.8h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %a)
|
||||
%res = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -239,7 +239,7 @@ define half @fminv_v16f16(<16 x half>* %a) #0 {
|
||||
; VBITS_GE_256-NEXT: fminnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_256-NEXT: ret
|
||||
%op = load <16 x half>, <16 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -250,7 +250,7 @@ define half @fminv_v32f16(<32 x half>* %a) #0 {
|
||||
; VBITS_GE_512-NEXT: fminnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op = load <32 x half>, <32 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmin.v32f16(<32 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmin.v32f16(<32 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -261,7 +261,7 @@ define half @fminv_v64f16(<64 x half>* %a) #0 {
|
||||
; VBITS_GE_1024-NEXT: fminnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op = load <64 x half>, <64 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmin.v64f16(<64 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmin.v64f16(<64 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -272,7 +272,7 @@ define half @fminv_v128f16(<128 x half>* %a) #0 {
|
||||
; VBITS_GE_2048-NEXT: fminnmv h0, [[PG]], [[OP]].h
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op = load <128 x half>, <128 x half>* %a
|
||||
%res = call half @llvm.experimental.vector.reduce.fmin.v128f16(<128 x half> %op)
|
||||
%res = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %op)
|
||||
ret half %res
|
||||
}
|
||||
|
||||
@@ -281,7 +281,7 @@ define float @fminv_v2f32(<2 x float> %a) #0 {
|
||||
; CHECK-LABEL: fminv_v2f32:
|
||||
; CHECK: fminnmp s0, v0.2s
|
||||
; CHECK: ret
|
||||
%res = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %a)
|
||||
%res = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -290,7 +290,7 @@ define float @fminv_v4f32(<4 x float> %a) #0 {
|
||||
; CHECK-LABEL: fminv_v4f32:
|
||||
; CHECK: fminnmv s0, v0.4s
|
||||
; CHECK: ret
|
||||
%res = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %a)
|
||||
%res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -301,7 +301,7 @@ define float @fminv_v8f32(<8 x float>* %a) #0 {
|
||||
; VBITS_GE_256-NEXT: fminnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_256-NEXT: ret
|
||||
%op = load <8 x float>, <8 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -312,7 +312,7 @@ define float @fminv_v16f32(<16 x float>* %a) #0 {
|
||||
; VBITS_GE_512-NEXT: fminnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op = load <16 x float>, <16 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmin.v16f32(<16 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -323,7 +323,7 @@ define float @fminv_v32f32(<32 x float>* %a) #0 {
|
||||
; VBITS_GE_1024-NEXT: fminnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op = load <32 x float>, <32 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmin.v32f32(<32 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmin.v32f32(<32 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -334,7 +334,7 @@ define float @fminv_v64f32(<64 x float>* %a) #0 {
|
||||
; VBITS_GE_2048-NEXT: fminnmv s0, [[PG]], [[OP]].s
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op = load <64 x float>, <64 x float>* %a
|
||||
%res = call float @llvm.experimental.vector.reduce.fmin.v64f32(<64 x float> %op)
|
||||
%res = call float @llvm.vector.reduce.fmin.v64f32(<64 x float> %op)
|
||||
ret float %res
|
||||
}
|
||||
|
||||
@@ -343,7 +343,7 @@ define double @fminv_v1f64(<1 x double> %a) #0 {
|
||||
; CHECK-LABEL: fminv_v1f64:
|
||||
; CHECK-NOT: fmin
|
||||
; CHECK: ret
|
||||
%res = call double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %a)
|
||||
%res = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -352,7 +352,7 @@ define double @fminv_v2f64(<2 x double> %a) #0 {
|
||||
; CHECK-LABEL: fminv_v2f64:
|
||||
; CHECK: fminnmp d0, v0.2d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %a)
|
||||
%res = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -363,7 +363,7 @@ define double @fminv_v4f64(<4 x double>* %a) #0 {
|
||||
; VBITS_GE_256-NEXT: fminnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_256-NEXT: ret
|
||||
%op = load <4 x double>, <4 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -374,7 +374,7 @@ define double @fminv_v8f64(<8 x double>* %a) #0 {
|
||||
; VBITS_GE_512-NEXT: fminnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op = load <8 x double>, <8 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmin.v8f64(<8 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmin.v8f64(<8 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -385,7 +385,7 @@ define double @fminv_v16f64(<16 x double>* %a) #0 {
|
||||
; VBITS_GE_1024-NEXT: fminnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op = load <16 x double>, <16 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmin.v16f64(<16 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmin.v16f64(<16 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
@@ -396,50 +396,50 @@ define double @fminv_v32f64(<32 x double>* %a) #0 {
|
||||
; VBITS_GE_2048-NEXT: fminnmv d0, [[PG]], [[OP]].d
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op = load <32 x double>, <32 x double>* %a
|
||||
%res = call double @llvm.experimental.vector.reduce.fmin.v32f64(<32 x double> %op)
|
||||
%res = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %op)
|
||||
ret double %res
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v8f16(<8 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v16f16(<16 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v32f16(<32 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v64f16(<64 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v128f16(<128 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v8f16(<8 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v16f16(<16 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v32f16(<32 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v64f16(<64 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v128f16(<128 x half>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v32f32(<32 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v64f32(<64 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v16f32(<16 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v32f32(<32 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v64f32(<64 x float>)
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v8f64(<8 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v16f64(<16 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v32f64(<32 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v8f64(<8 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v16f64(<16 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v32f64(<32 x double>)
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v32f16(<32 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v64f16(<64 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v128f16(<128 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v8f16(<8 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v16f16(<16 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v32f16(<32 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v64f16(<64 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v128f16(<128 x half>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v32f32(<32 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v64f32(<64 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v16f32(<16 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v32f32(<32 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v64f32(<64 x float>)
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v8f64(<8 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v16f64(<16 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v32f64(<32 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v1f64(<1 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v8f64(<8 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v16f64(<16 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v32f64(<32 x double>)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,28 +1,28 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.add.v1i1(<1 x i1> %a)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v1i8(<1 x i8> %a)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v1i16(<1 x i16> %a)
|
||||
declare i24 @llvm.experimental.vector.reduce.add.v1i24(<1 x i24> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v1i32(<1 x i32> %a)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> %a)
|
||||
declare i128 @llvm.experimental.vector.reduce.add.v1i128(<1 x i128> %a)
|
||||
declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)
|
||||
declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)
|
||||
declare i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)
|
||||
declare i24 @llvm.vector.reduce.add.v1i24(<1 x i24> %a)
|
||||
declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)
|
||||
declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)
|
||||
declare i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v3i8(<3 x i8> %a)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v9i8(<9 x i8> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v3i32(<3 x i32> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.add.v4i1(<4 x i1> %a)
|
||||
declare i24 @llvm.experimental.vector.reduce.add.v4i24(<4 x i24> %a)
|
||||
declare i128 @llvm.experimental.vector.reduce.add.v2i128(<2 x i128> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %a)
|
||||
declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)
|
||||
declare i8 @llvm.vector.reduce.add.v9i8(<9 x i8> %a)
|
||||
declare i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)
|
||||
declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %a)
|
||||
declare i24 @llvm.vector.reduce.add.v4i24(<4 x i24> %a)
|
||||
declare i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
|
||||
|
||||
define i1 @test_v1i1(<1 x i1> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: and w0, w0, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i1 @llvm.experimental.vector.reduce.add.v1i1(<1 x i1> %a)
|
||||
%b = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)
|
||||
ret i1 %b
|
||||
}
|
||||
|
||||
@@ -32,7 +32,7 @@ define i8 @test_v1i8(<1 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: umov w0, v0.b[0]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.add.v1i8(<1 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -42,7 +42,7 @@ define i16 @test_v1i16(<1 x i16> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: umov w0, v0.h[0]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i16 @llvm.experimental.vector.reduce.add.v1i16(<1 x i16> %a)
|
||||
%b = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)
|
||||
ret i16 %b
|
||||
}
|
||||
|
||||
@@ -50,7 +50,7 @@ define i24 @test_v1i24(<1 x i24> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i24:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i24 @llvm.experimental.vector.reduce.add.v1i24(<1 x i24> %a)
|
||||
%b = call i24 @llvm.vector.reduce.add.v1i24(<1 x i24> %a)
|
||||
ret i24 %b
|
||||
}
|
||||
|
||||
@@ -60,7 +60,7 @@ define i32 @test_v1i32(<1 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.add.v1i32(<1 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -70,7 +70,7 @@ define i64 @test_v1i64(<1 x i64> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i64 @llvm.experimental.vector.reduce.add.v1i64(<1 x i64> %a)
|
||||
%b = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)
|
||||
ret i64 %b
|
||||
}
|
||||
|
||||
@@ -78,7 +78,7 @@ define i128 @test_v1i128(<1 x i128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i128 @llvm.experimental.vector.reduce.add.v1i128(<1 x i128> %a)
|
||||
%b = call i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)
|
||||
ret i128 %b
|
||||
}
|
||||
|
||||
@@ -92,7 +92,7 @@ define i8 @test_v3i8(<3 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: addv h0, v0.4h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.add.v3i8(<3 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -109,7 +109,7 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: addv b0, v0.16b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.add.v9i8(<9 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.add.v9i8(<9 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -120,7 +120,7 @@ define i32 @test_v3i32(<3 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: addv s0, v0.4s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.add.v3i32(<3 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -131,7 +131,7 @@ define i1 @test_v4i1(<4 x i1> %a) nounwind {
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: and w0, w8, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i1 @llvm.experimental.vector.reduce.add.v4i1(<4 x i1> %a)
|
||||
%b = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %a)
|
||||
ret i1 %b
|
||||
}
|
||||
|
||||
@@ -141,7 +141,7 @@ define i24 @test_v4i24(<4 x i24> %a) nounwind {
|
||||
; CHECK-NEXT: addv s0, v0.4s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i24 @llvm.experimental.vector.reduce.add.v4i24(<4 x i24> %a)
|
||||
%b = call i24 @llvm.vector.reduce.add.v4i24(<4 x i24> %a)
|
||||
ret i24 %b
|
||||
}
|
||||
|
||||
@@ -151,7 +151,7 @@ define i128 @test_v2i128(<2 x i128> %a) nounwind {
|
||||
; CHECK-NEXT: adds x0, x0, x2
|
||||
; CHECK-NEXT: adcs x1, x1, x3
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i128 @llvm.experimental.vector.reduce.add.v2i128(<2 x i128> %a)
|
||||
%b = call i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)
|
||||
ret i128 %b
|
||||
}
|
||||
|
||||
@@ -164,6 +164,6 @@ define i32 @test_v16i32(<16 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: addv s0, v0.4s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -1,28 +1,28 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v1i8(<1 x i8> %a)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v1i16(<1 x i16> %a)
|
||||
declare i24 @llvm.experimental.vector.reduce.and.v1i24(<1 x i24> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v1i32(<1 x i32> %a)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %a)
|
||||
declare i128 @llvm.experimental.vector.reduce.and.v1i128(<1 x i128> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
|
||||
declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
|
||||
declare i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
|
||||
declare i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)
|
||||
declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
|
||||
declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)
|
||||
declare i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v9i8(<9 x i8> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a)
|
||||
declare i24 @llvm.experimental.vector.reduce.and.v4i24(<4 x i24> %a)
|
||||
declare i128 @llvm.experimental.vector.reduce.and.v2i128(<2 x i128> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> %a)
|
||||
declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
|
||||
declare i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
|
||||
declare i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
|
||||
declare i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)
|
||||
declare i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)
|
||||
declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
|
||||
|
||||
define i1 @test_v1i1(<1 x i1> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: and w0, w0, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a)
|
||||
%b = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
|
||||
ret i1 %b
|
||||
}
|
||||
|
||||
@@ -32,7 +32,7 @@ define i8 @test_v1i8(<1 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: umov w0, v0.b[0]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.and.v1i8(<1 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -42,7 +42,7 @@ define i16 @test_v1i16(<1 x i16> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: umov w0, v0.h[0]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i16 @llvm.experimental.vector.reduce.and.v1i16(<1 x i16> %a)
|
||||
%b = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
|
||||
ret i16 %b
|
||||
}
|
||||
|
||||
@@ -50,7 +50,7 @@ define i24 @test_v1i24(<1 x i24> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i24:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i24 @llvm.experimental.vector.reduce.and.v1i24(<1 x i24> %a)
|
||||
%b = call i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)
|
||||
ret i24 %b
|
||||
}
|
||||
|
||||
@@ -60,7 +60,7 @@ define i32 @test_v1i32(<1 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.and.v1i32(<1 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -70,7 +70,7 @@ define i64 @test_v1i64(<1 x i64> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %a)
|
||||
%b = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)
|
||||
ret i64 %b
|
||||
}
|
||||
|
||||
@@ -78,7 +78,7 @@ define i128 @test_v1i128(<1 x i128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i128 @llvm.experimental.vector.reduce.and.v1i128(<1 x i128> %a)
|
||||
%b = call i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
|
||||
ret i128 %b
|
||||
}
|
||||
|
||||
@@ -89,7 +89,7 @@ define i8 @test_v3i8(<3 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: and w8, w8, w2
|
||||
; CHECK-NEXT: and w0, w8, #0xff
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -120,7 +120,7 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: umov w9, v0.b[7]
|
||||
; CHECK-NEXT: and w0, w8, w9
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.and.v9i8(<9 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -133,7 +133,7 @@ define i32 @test_v3i32(<3 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: fmov w9, s1
|
||||
; CHECK-NEXT: and w0, w9, w8
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -150,7 +150,7 @@ define i1 @test_v4i1(<4 x i1> %a) nounwind {
|
||||
; CHECK-NEXT: and w8, w9, w8
|
||||
; CHECK-NEXT: and w0, w8, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a)
|
||||
%b = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
|
||||
ret i1 %b
|
||||
}
|
||||
|
||||
@@ -163,7 +163,7 @@ define i24 @test_v4i24(<4 x i24> %a) nounwind {
|
||||
; CHECK-NEXT: fmov w9, s0
|
||||
; CHECK-NEXT: and w0, w9, w8
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i24 @llvm.experimental.vector.reduce.and.v4i24(<4 x i24> %a)
|
||||
%b = call i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)
|
||||
ret i24 %b
|
||||
}
|
||||
|
||||
@@ -173,7 +173,7 @@ define i128 @test_v2i128(<2 x i128> %a) nounwind {
|
||||
; CHECK-NEXT: and x0, x0, x2
|
||||
; CHECK-NEXT: and x1, x1, x3
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i128 @llvm.experimental.vector.reduce.and.v2i128(<2 x i128> %a)
|
||||
%b = call i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)
|
||||
ret i128 %b
|
||||
}
|
||||
|
||||
@@ -189,6 +189,6 @@ define i32 @test_v16i32(<16 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: fmov w9, s0
|
||||
; CHECK-NEXT: and w0, w9, w8
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -1,19 +1,19 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %a)
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)
|
||||
declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)
|
||||
|
||||
define i32 @reduce_and_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-LABEL: reduce_and_v1:
|
||||
@@ -24,7 +24,7 @@ define i32 @reduce_and_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, lt
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <1 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -41,7 +41,7 @@ define i32 @reduce_and_v2(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <2 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -58,7 +58,7 @@ define i32 @reduce_and_v4(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <4 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -73,7 +73,7 @@ define i32 @reduce_and_v8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <8 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -88,7 +88,7 @@ define i32 @reduce_and_v16(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <16 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -105,7 +105,7 @@ define i32 @reduce_and_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <32 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -119,7 +119,7 @@ define i32 @reduce_or_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, lt
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <1 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -136,7 +136,7 @@ define i32 @reduce_or_v2(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <2 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -153,7 +153,7 @@ define i32 @reduce_or_v4(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <4 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -168,7 +168,7 @@ define i32 @reduce_or_v8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <8 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -183,7 +183,7 @@ define i32 @reduce_or_v16(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <16 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
@@ -200,7 +200,7 @@ define i32 @reduce_or_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
|
||||
; CHECK-NEXT: csel w0, w0, w1, ne
|
||||
; CHECK-NEXT: ret
|
||||
%x = icmp slt <32 x i8> %a0, zeroinitializer
|
||||
%y = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> %x)
|
||||
%y = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %x)
|
||||
%z = select i1 %y, i32 %a1, i32 %a2
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -3,14 +3,14 @@
|
||||
|
||||
; Same as vecreduce-fadd-legalization.ll, but without fmf.
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128, <1 x fp128>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float, <16 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
@@ -20,7 +20,7 @@ define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-NEXT: fadd s0, s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
%b = call half @llvm.vector.reduce.fadd.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -31,7 +31,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fmov s1, wzr
|
||||
; CHECK-NEXT: fadd s0, s0, s1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fadd.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -41,7 +41,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-NEXT: fmov d1, xzr
|
||||
; CHECK-NEXT: fadd d0, d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
%b = call double @llvm.vector.reduce.fadd.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -54,7 +54,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: bl __addtf3
|
||||
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -68,7 +68,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: mov s0, v0.s[2]
|
||||
; CHECK-NEXT: fadd s0, s1, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fadd.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -86,7 +86,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: add sp, sp, #32 // =32
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -123,6 +123,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: mov s1, v3.s[3]
|
||||
; CHECK-NEXT: fadd s0, s0, s1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fadd.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -1,20 +1,20 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128, <1 x fp128>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float, <16 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fast nnan half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
%b = call fast nnan half @llvm.vector.reduce.fadd.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -24,7 +24,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fast nnan float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
%b = call fast nnan float @llvm.vector.reduce.fadd.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -32,7 +32,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fast nnan double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
%b = call fast nnan double @llvm.vector.reduce.fadd.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -40,7 +40,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fast nnan fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
%b = call fast nnan fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -53,7 +53,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fadd v0.2s, v0.2s, v1.2s
|
||||
; CHECK-NEXT: faddp s0, v0.2s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fast nnan float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
%b = call fast nnan float @llvm.vector.reduce.fadd.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -64,7 +64,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: bl __addtf3
|
||||
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fast nnan fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
%b = call fast nnan fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -78,6 +78,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fadd v0.2s, v0.2s, v1.2s
|
||||
; CHECK-NEXT: faddp s0, v0.2s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fast nnan float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
%b = call fast nnan float @llvm.vector.reduce.fadd.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -14,7 +14,7 @@ define float @add_HalfS(<2 x float> %bin.rdx) {
|
||||
; CHECKNOFP16-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECKNOFP16-NEXT: faddp s0, v0.2s
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float 0.0, <2 x float> %bin.rdx)
|
||||
%r = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float 0.0, <2 x float> %bin.rdx)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -48,7 +48,7 @@ define half @add_HalfH(<4 x half> %bin.rdx) {
|
||||
; CHECKNOFP16-NEXT: fadd s0, s0, s1
|
||||
; CHECKNOFP16-NEXT: fcvt h0, s0
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half 0.0, <4 x half> %bin.rdx)
|
||||
%r = call fast half @llvm.vector.reduce.fadd.f16.v4f16(half 0.0, <4 x half> %bin.rdx)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
@@ -103,7 +103,7 @@ define half @add_H(<8 x half> %bin.rdx) {
|
||||
; CHECKNOFP16-NEXT: fadd s0, s0, s1
|
||||
; CHECKNOFP16-NEXT: fcvt h0, s0
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v8f16(half 0.0, <8 x half> %bin.rdx)
|
||||
%r = call fast half @llvm.vector.reduce.fadd.f16.v8f16(half 0.0, <8 x half> %bin.rdx)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
@@ -121,7 +121,7 @@ define float @add_S(<4 x float> %bin.rdx) {
|
||||
; CHECKNOFP16-NEXT: fadd v0.2s, v0.2s, v1.2s
|
||||
; CHECKNOFP16-NEXT: faddp s0, v0.2s
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.0, <4 x float> %bin.rdx)
|
||||
%r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %bin.rdx)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -135,7 +135,7 @@ define double @add_D(<2 x double> %bin.rdx) {
|
||||
; CHECKNOFP16: // %bb.0:
|
||||
; CHECKNOFP16-NEXT: faddp d0, v0.2d
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double 0.0, <2 x double> %bin.rdx)
|
||||
%r = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double 0.0, <2 x double> %bin.rdx)
|
||||
ret double %r
|
||||
}
|
||||
|
||||
@@ -229,7 +229,7 @@ define half @add_2H(<16 x half> %bin.rdx) {
|
||||
; CHECKNOFP16-NEXT: fadd s0, s1, s0
|
||||
; CHECKNOFP16-NEXT: fcvt h0, s0
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v16f16(half 0.0, <16 x half> %bin.rdx)
|
||||
%r = call fast half @llvm.vector.reduce.fadd.f16.v16f16(half 0.0, <16 x half> %bin.rdx)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
@@ -249,7 +249,7 @@ define float @add_2S(<8 x float> %bin.rdx) {
|
||||
; CHECKNOFP16-NEXT: fadd v0.2s, v0.2s, v1.2s
|
||||
; CHECKNOFP16-NEXT: faddp s0, v0.2s
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v8f32(float 0.0, <8 x float> %bin.rdx)
|
||||
%r = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float 0.0, <8 x float> %bin.rdx)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -265,16 +265,16 @@ define double @add_2D(<4 x double> %bin.rdx) {
|
||||
; CHECKNOFP16-NEXT: fadd v0.2d, v0.2d, v1.2d
|
||||
; CHECKNOFP16-NEXT: faddp d0, v0.2d
|
||||
; CHECKNOFP16-NEXT: ret
|
||||
%r = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v4f64(double 0.0, <4 x double> %bin.rdx)
|
||||
%r = call fast double @llvm.vector.reduce.fadd.f64.v4f64(double 0.0, <4 x double> %bin.rdx)
|
||||
ret double %r
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half, <4 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v8f16(half, <8 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v16f16(half, <16 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float, <2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v8f32(float, <8 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double, <2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v4f64(double, <4 x double>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v4f16(half, <4 x half>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v8f16(half, <8 x half>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v16f16(half, <16 x half>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v2f32(float, <2 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v2f64(double, <2 x double>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v4f64(double, <4 x double>)
|
||||
|
||||
@@ -1,20 +1,20 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
declare fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
%b = call half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -24,7 +24,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -32,7 +32,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
%b = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -40,14 +40,14 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
; TODO: This doesn't work, because ExpandReductions only supports power of two
|
||||
; unordered reductions.
|
||||
;define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; %b = call float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
; %b = call float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
; ret float %b
|
||||
;}
|
||||
|
||||
@@ -55,7 +55,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v2f128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: b fmaxl
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -67,6 +67,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: fmaxnmv s0, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -1,20 +1,20 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
declare fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan half @llvm.experimental.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
%b = call nnan half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -24,7 +24,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan float @llvm.experimental.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
%b = call nnan float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -32,7 +32,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
%b = call nnan double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -40,7 +40,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan fp128 @llvm.experimental.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
%b = call nnan fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -52,7 +52,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: mov v0.s[3], v1.s[0]
|
||||
; CHECK-NEXT: fmaxnmv s0, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
%b = call nnan float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -64,7 +64,7 @@ define float @test_v3f32_ninf(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: mov v0.s[3], v1.s[0]
|
||||
; CHECK-NEXT: fmaxnmv s0, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan ninf float @llvm.experimental.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
%b = call nnan ninf float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -72,7 +72,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v2f128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: b fmaxl
|
||||
%b = call nnan fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
%b = call nnan fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -84,6 +84,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: fmaxnmv s0, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan float @llvm.experimental.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
%b = call nnan float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -1,20 +1,20 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v1f16(<1 x half> %a)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> %a)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %a)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmin.v1f128(<1 x fp128> %a)
|
||||
declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
|
||||
declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
|
||||
declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
|
||||
declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v3f32(<3 x float> %a)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmin.v2f128(<2 x fp128> %a)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> %a)
|
||||
declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
|
||||
declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
|
||||
declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan half @llvm.experimental.vector.reduce.fmin.v1f16(<1 x half> %a)
|
||||
%b = call nnan half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -24,7 +24,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan float @llvm.experimental.vector.reduce.fmin.v1f32(<1 x float> %a)
|
||||
%b = call nnan float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -32,7 +32,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %a)
|
||||
%b = call nnan double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -40,7 +40,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan fp128 @llvm.experimental.vector.reduce.fmin.v1f128(<1 x fp128> %a)
|
||||
%b = call nnan fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -52,7 +52,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: mov v0.s[3], v1.s[0]
|
||||
; CHECK-NEXT: fminnmv s0, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan float @llvm.experimental.vector.reduce.fmin.v3f32(<3 x float> %a)
|
||||
%b = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -64,7 +64,7 @@ define float @test_v3f32_ninf(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: mov v0.s[3], v1.s[0]
|
||||
; CHECK-NEXT: fminnmv s0, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan ninf float @llvm.experimental.vector.reduce.fmin.v3f32(<3 x float> %a)
|
||||
%b = call nnan ninf float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -72,7 +72,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v2f128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: b fminl
|
||||
%b = call nnan fp128 @llvm.experimental.vector.reduce.fmin.v2f128(<2 x fp128> %a)
|
||||
%b = call nnan fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -84,6 +84,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: fminnmv s0, v0.4s
|
||||
; CHECK-NEXT: ret
|
||||
%b = call nnan float @llvm.experimental.vector.reduce.fmin.v16f32(<16 x float> %a)
|
||||
%b = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -3,14 +3,14 @@
|
||||
|
||||
; Same as vecreduce-fmul-legalization.ll, but without fmf.
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v1f128(fp128, <1 x fp128>)
|
||||
declare half @llvm.vector.reduce.fmul.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128, <1 x fp128>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float, <16 x float>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v16f32(float, <16 x float>)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
@@ -20,7 +20,7 @@ define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-NEXT: fmul s0, s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
%b = call half @llvm.vector.reduce.fmul.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -31,7 +31,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fmov s1, wzr
|
||||
; CHECK-NEXT: fmul s0, s1, v0.s[0]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmul.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -41,7 +41,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-NEXT: fmov d1, xzr
|
||||
; CHECK-NEXT: fmul d0, d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
%b = call double @llvm.vector.reduce.fmul.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -54,7 +54,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: bl __multf3
|
||||
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -66,7 +66,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fmul s1, s1, v0.s[1]
|
||||
; CHECK-NEXT: fmul s0, s1, v0.s[2]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -84,7 +84,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
|
||||
; CHECK-NEXT: add sp, sp, #32 // =32
|
||||
; CHECK-NEXT: ret
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -109,6 +109,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: fmul s0, s0, v3.s[2]
|
||||
; CHECK-NEXT: fmul s0, s0, v3.s[3]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmul.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -24,8 +24,8 @@ entry:
|
||||
%1 = insertelement <4 x double> %0, double 1.0, i32 1
|
||||
%2 = insertelement <4 x double> %1, double 1.0, i32 2
|
||||
%3 = insertelement <4 x double> %2, double 1.0, i32 3
|
||||
%4 = call nnan reassoc double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %3)
|
||||
%4 = call nnan reassoc double @llvm.vector.reduce.fmax.v4f64(<4 x double> %3)
|
||||
ret double %4
|
||||
}
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
|
||||
@@ -1,29 +1,29 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare i1 @llvm.experimental.vector.reduce.umax.v1i1(<1 x i1> %a)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v1i8(<1 x i8> %a)
|
||||
declare i16 @llvm.experimental.vector.reduce.umax.v1i16(<1 x i16> %a)
|
||||
declare i24 @llvm.experimental.vector.reduce.umax.v1i24(<1 x i24> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v1i32(<1 x i32> %a)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> %a)
|
||||
declare i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
|
||||
declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)
|
||||
declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)
|
||||
declare i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)
|
||||
declare i24 @llvm.vector.reduce.umax.v1i24(<1 x i24> %a)
|
||||
declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)
|
||||
declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %a)
|
||||
declare i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> %a)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v3i8(<3 x i8> %a)
|
||||
declare i8 @llvm.experimental.vector.reduce.umax.v9i8(<9 x i8> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v3i32(<3 x i32> %a)
|
||||
declare i1 @llvm.experimental.vector.reduce.umax.v4i1(<4 x i1> %a)
|
||||
declare i24 @llvm.experimental.vector.reduce.umax.v4i24(<4 x i24> %a)
|
||||
declare i128 @llvm.experimental.vector.reduce.umax.v2i128(<2 x i128> %a)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %a)
|
||||
declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)
|
||||
declare i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %a)
|
||||
declare i8 @llvm.vector.reduce.umax.v9i8(<9 x i8> %a)
|
||||
declare i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
|
||||
declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %a)
|
||||
declare i24 @llvm.vector.reduce.umax.v4i24(<4 x i24> %a)
|
||||
declare i128 @llvm.vector.reduce.umax.v2i128(<2 x i128> %a)
|
||||
declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)
|
||||
|
||||
define i1 @test_v1i1(<1 x i1> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: and w0, w0, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i1 @llvm.experimental.vector.reduce.umax.v1i1(<1 x i1> %a)
|
||||
%b = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)
|
||||
ret i1 %b
|
||||
}
|
||||
|
||||
@@ -33,7 +33,7 @@ define i8 @test_v1i8(<1 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: umov w0, v0.b[0]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.umax.v1i8(<1 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -43,7 +43,7 @@ define i16 @test_v1i16(<1 x i16> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: umov w0, v0.h[0]
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i16 @llvm.experimental.vector.reduce.umax.v1i16(<1 x i16> %a)
|
||||
%b = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)
|
||||
ret i16 %b
|
||||
}
|
||||
|
||||
@@ -51,7 +51,7 @@ define i24 @test_v1i24(<1 x i24> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i24:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i24 @llvm.experimental.vector.reduce.umax.v1i24(<1 x i24> %a)
|
||||
%b = call i24 @llvm.vector.reduce.umax.v1i24(<1 x i24> %a)
|
||||
ret i24 %b
|
||||
}
|
||||
|
||||
@@ -61,7 +61,7 @@ define i32 @test_v1i32(<1 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.umax.v1i32(<1 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -71,7 +71,7 @@ define i64 @test_v1i64(<1 x i64> %a) nounwind {
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> %a)
|
||||
%b = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %a)
|
||||
ret i64 %b
|
||||
}
|
||||
|
||||
@@ -79,7 +79,7 @@ define i128 @test_v1i128(<1 x i128> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1i128:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
|
||||
%b = call i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)
|
||||
ret i128 %b
|
||||
}
|
||||
|
||||
@@ -92,7 +92,7 @@ define i64 @test_v2i64(<2 x i64> %a) nounwind {
|
||||
; CHECK-NEXT: cmp x9, x8
|
||||
; CHECK-NEXT: csel x0, x9, x8, hi
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> %a)
|
||||
%b = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)
|
||||
ret i64 %b
|
||||
}
|
||||
|
||||
@@ -107,7 +107,7 @@ define i8 @test_v3i8(<3 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: umaxv h0, v0.4h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.umax.v3i8(<3 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -124,7 +124,7 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind {
|
||||
; CHECK-NEXT: umaxv b0, v0.16b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i8 @llvm.experimental.vector.reduce.umax.v9i8(<9 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.umax.v9i8(<9 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -135,7 +135,7 @@ define i32 @test_v3i32(<3 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: umaxv s0, v0.4s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.umax.v3i32(<3 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -148,7 +148,7 @@ define i1 @test_v4i1(<4 x i1> %a) nounwind {
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: and w0, w8, #0x1
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i1 @llvm.experimental.vector.reduce.umax.v4i1(<4 x i1> %a)
|
||||
%b = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %a)
|
||||
ret i1 %b
|
||||
}
|
||||
|
||||
@@ -159,7 +159,7 @@ define i24 @test_v4i24(<4 x i24> %a) nounwind {
|
||||
; CHECK-NEXT: umaxv s0, v0.4s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i24 @llvm.experimental.vector.reduce.umax.v4i24(<4 x i24> %a)
|
||||
%b = call i24 @llvm.vector.reduce.umax.v4i24(<4 x i24> %a)
|
||||
ret i24 %b
|
||||
}
|
||||
|
||||
@@ -173,7 +173,7 @@ define i128 @test_v2i128(<2 x i128> %a) nounwind {
|
||||
; CHECK-NEXT: csel x0, x8, x9, eq
|
||||
; CHECK-NEXT: csel x1, x1, x3, hi
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i128 @llvm.experimental.vector.reduce.umax.v2i128(<2 x i128> %a)
|
||||
%b = call i128 @llvm.vector.reduce.umax.v2i128(<2 x i128> %a)
|
||||
ret i128 %b
|
||||
}
|
||||
|
||||
@@ -186,6 +186,6 @@ define i32 @test_v16i32(<16 x i32> %a) nounwind {
|
||||
; CHECK-NEXT: umaxv s0, v0.4s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%b = call i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %a)
|
||||
%b = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half, <4 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double, <2 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v4f16(half, <4 x half>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v2f64(double, <2 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
|
||||
define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v4f16:
|
||||
@@ -37,7 +37,7 @@ define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_f2h
|
||||
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half 0.0, <4 x half> %a)
|
||||
%b = call fast half @llvm.vector.reduce.fadd.f16.v4f16(half 0.0, <4 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -55,7 +55,7 @@ define float @test_v4f32(<4 x float> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_fadd
|
||||
; CHECK-NEXT: pop {r4, r5, r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.0, <4 x float> %a)
|
||||
%b = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -67,7 +67,7 @@ define double @test_v2f64(<2 x double> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_dadd
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double zeroinitializer, <2 x double> %a)
|
||||
%b = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double zeroinitializer, <2 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -90,6 +90,6 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
%b = call fast fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128, <1 x fp128>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float, <16 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
@@ -28,7 +28,7 @@ define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI0_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
%b = call half @llvm.vector.reduce.fadd.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -44,7 +44,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI1_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fadd.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -56,7 +56,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-NEXT: vadd.f64 d16, d17, d16
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
%b = call double @llvm.vector.reduce.fadd.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -76,7 +76,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -95,7 +95,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI4_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fadd.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -124,7 +124,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r4, r5, r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -162,6 +162,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI6_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fadd.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128>)
|
||||
declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)
|
||||
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128>)
|
||||
|
||||
define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v4f16:
|
||||
@@ -37,7 +37,7 @@ define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_f2h
|
||||
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %a)
|
||||
%b = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -55,7 +55,7 @@ define float @test_v4f32(<4 x float> %a) nounwind {
|
||||
; CHECK-NEXT: bl fmaxf
|
||||
; CHECK-NEXT: pop {r4, r5, r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %a)
|
||||
%b = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -67,7 +67,7 @@ define double @test_v2f64(<2 x double> %a) nounwind {
|
||||
; CHECK-NEXT: bl fmax
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %a)
|
||||
%b = call fast double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -90,6 +90,6 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast fp128 @llvm.experimental.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
%b = call fast fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.fmin.v2f128(<2 x fp128>)
|
||||
declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
|
||||
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128>)
|
||||
|
||||
define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v4f16:
|
||||
@@ -37,7 +37,7 @@ define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_f2h
|
||||
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %a)
|
||||
%b = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -55,7 +55,7 @@ define float @test_v4f32(<4 x float> %a) nounwind {
|
||||
; CHECK-NEXT: bl fminf
|
||||
; CHECK-NEXT: pop {r4, r5, r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %a)
|
||||
%b = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -67,7 +67,7 @@ define double @test_v2f64(<2 x double> %a) nounwind {
|
||||
; CHECK-NEXT: bl fmin
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %a)
|
||||
%b = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -90,6 +90,6 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast fp128 @llvm.experimental.vector.reduce.fmin.v2f128(<2 x fp128> %a)
|
||||
%b = call fast fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v4f16(half, <4 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float, <4 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v2f64(double, <2 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare half @llvm.vector.reduce.fmul.f16.v4f16(half, <4 x half>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)
|
||||
declare double @llvm.vector.reduce.fmul.f64.v2f64(double, <2 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>)
|
||||
|
||||
define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v4f16:
|
||||
@@ -37,7 +37,7 @@ define half @test_v4f16(<4 x half> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_f2h
|
||||
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast half @llvm.experimental.vector.reduce.v2.fmul.f16.v4f16(half 1.0, <4 x half> %a)
|
||||
%b = call fast half @llvm.vector.reduce.fmul.f16.v4f16(half 1.0, <4 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -55,7 +55,7 @@ define float @test_v4f32(<4 x float> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_fmul
|
||||
; CHECK-NEXT: pop {r4, r5, r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float 1.0, <4 x float> %a)
|
||||
%b = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -67,7 +67,7 @@ define double @test_v2f64(<2 x double> %a) nounwind {
|
||||
; CHECK-NEXT: bl __aeabi_dmul
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast double @llvm.experimental.vector.reduce.v2.fmul.f64.v2f64(double 1.0, <2 x double> %a)
|
||||
%b = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -90,6 +90,6 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fast fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a)
|
||||
%b = call fast fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+neon | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v1f128(fp128, <1 x fp128>)
|
||||
declare half @llvm.vector.reduce.fmul.f16.v1f16(half, <1 x half>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v1f32(float, <1 x float>)
|
||||
declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>)
|
||||
declare fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128, <1 x fp128>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float, <16 x float>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v3f32(float, <3 x float>)
|
||||
declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v16f32(float, <16 x float>)
|
||||
|
||||
define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-LABEL: test_v1f16:
|
||||
@@ -28,7 +28,7 @@ define half @test_v1f16(<1 x half> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI0_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
%b = call half @llvm.vector.reduce.fmul.f16.v1f16(half 0.0, <1 x half> %a)
|
||||
ret half %b
|
||||
}
|
||||
|
||||
@@ -44,7 +44,7 @@ define float @test_v1f32(<1 x float> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI1_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmul.f32.v1f32(float 0.0, <1 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -56,7 +56,7 @@ define double @test_v1f64(<1 x double> %a) nounwind {
|
||||
; CHECK-NEXT: vmul.f64 d16, d17, d16
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
%b = call double @llvm.vector.reduce.fmul.f64.v1f64(double 0.0, <1 x double> %a)
|
||||
ret double %b
|
||||
}
|
||||
|
||||
@@ -76,7 +76,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -95,7 +95,7 @@ define float @test_v3f32(<3 x float> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI4_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 0.0, <3 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -124,7 +124,7 @@ define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
||||
; CHECK-NEXT: add sp, sp, #16
|
||||
; CHECK-NEXT: pop {r4, r5, r11, lr}
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%b = call fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
%b = call fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a)
|
||||
ret fp128 %b
|
||||
}
|
||||
|
||||
@@ -162,6 +162,6 @@ define float @test_v16f32(<16 x float> %a) nounwind {
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI6_0:
|
||||
; CHECK-NEXT: .long 0x00000000 @ float 0
|
||||
%b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
%b = call float @llvm.vector.reduce.fmul.f32.v16f32(float 0.0, <16 x float> %a)
|
||||
ret float %b
|
||||
}
|
||||
|
||||
@@ -1,24 +1,24 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
||||
; RUN: opt < %s -expand-reductions -S | FileCheck %s
|
||||
; Tests without a target which should expand all reductions
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.mul.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
|
||||
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
|
||||
declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8>)
|
||||
|
||||
define i64 @add_i64(<2 x i64> %vec) {
|
||||
; CHECK-LABEL: @add_i64(
|
||||
@@ -29,7 +29,7 @@ define i64 @add_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -42,7 +42,7 @@ define i64 @mul_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -55,7 +55,7 @@ define i64 @and_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -68,7 +68,7 @@ define i64 @or_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -81,7 +81,7 @@ define i64 @xor_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -97,7 +97,7 @@ define float @fadd_f32(<4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.0, <4 x float> %vec)
|
||||
%r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -113,7 +113,7 @@ define float @fadd_f32_accum(float %accum, <4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
%r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -131,7 +131,7 @@ define float @fadd_f32_strict(<4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float undef, <4 x float> %vec)
|
||||
%r = call float @llvm.vector.reduce.fadd.f32.v4f32(float undef, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -149,7 +149,7 @@ define float @fadd_f32_strict_accum(float %accum, <4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
%r = call float @llvm.vector.reduce.fadd.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -165,7 +165,7 @@ define float @fmul_f32(<4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float 1.0, <4 x float> %vec)
|
||||
%r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -181,7 +181,7 @@ define float @fmul_f32_accum(float %accum, <4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
%r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -199,7 +199,7 @@ define float @fmul_f32_strict(<4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float undef, <4 x float> %vec)
|
||||
%r = call float @llvm.vector.reduce.fmul.f32.v4f32(float undef, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -217,7 +217,7 @@ define float @fmul_f32_strict_accum(float %accum, <4 x float> %vec) {
|
||||
; CHECK-NEXT: ret float [[BIN_RDX3]]
|
||||
;
|
||||
entry:
|
||||
%r = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
%r = call float @llvm.vector.reduce.fmul.f32.v4f32(float %accum, <4 x float> %vec)
|
||||
ret float %r
|
||||
}
|
||||
|
||||
@@ -231,7 +231,7 @@ define i64 @smax_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.smax.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -245,7 +245,7 @@ define i64 @smin_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.smin.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -259,7 +259,7 @@ define i64 @umax_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -273,7 +273,7 @@ define i64 @umin_i64(<2 x i64> %vec) {
|
||||
; CHECK-NEXT: ret i64 [[TMP0]]
|
||||
;
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64> %vec)
|
||||
%r = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %vec)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -282,11 +282,11 @@ entry:
|
||||
define double @fmax_f64(<2 x double> %vec) {
|
||||
; CHECK-LABEL: @fmax_f64(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[R:%.*]] = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> [[VEC:%.*]])
|
||||
; CHECK-NEXT: [[R:%.*]] = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> [[VEC:%.*]])
|
||||
; CHECK-NEXT: ret double [[R]]
|
||||
;
|
||||
entry:
|
||||
%r = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %vec)
|
||||
%r = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %vec)
|
||||
ret double %r
|
||||
}
|
||||
|
||||
@@ -295,11 +295,11 @@ entry:
|
||||
define double @fmin_f64(<2 x double> %vec) {
|
||||
; CHECK-LABEL: @fmin_f64(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[R:%.*]] = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> [[VEC:%.*]])
|
||||
; CHECK-NEXT: [[R:%.*]] = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> [[VEC:%.*]])
|
||||
; CHECK-NEXT: ret double [[R]]
|
||||
;
|
||||
entry:
|
||||
%r = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %vec)
|
||||
%r = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %vec)
|
||||
ret double %r
|
||||
}
|
||||
|
||||
@@ -309,10 +309,10 @@ entry:
|
||||
define i8 @test_v3i8(<3 x i8> %a) nounwind {
|
||||
; CHECK-LABEL: @test_v3i8(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[B:%.*]] = call i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> [[A:%.*]])
|
||||
; CHECK-NEXT: [[B:%.*]] = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> [[A:%.*]])
|
||||
; CHECK-NEXT: ret i8 [[B]]
|
||||
;
|
||||
entry:
|
||||
%b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
|
||||
%b = call i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8> %a)
|
||||
ret i8 %b
|
||||
}
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
%add7 = add <4 x i32> %mul, %splat.output
|
||||
%max = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %add7, <4 x i32> %.splat.i42, i32 1, <4 x i1> %pred, <4 x i32> undef)
|
||||
%min = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %max, <4 x i32> %.splat.i, i32 1, <4 x i1> %pred, <4 x i32> undef)
|
||||
%reduce = tail call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %min)
|
||||
%reduce = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %min)
|
||||
store i32 %reduce, i32* %scevgep2
|
||||
%add.ptr = getelementptr inbounds i8, i8* %input_1_vect.addr.052, i32 4
|
||||
%add.ptr14 = getelementptr inbounds i8, i8* %input_2_vect.addr.051, i32 4
|
||||
@@ -62,7 +62,7 @@
|
||||
declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
|
||||
declare i1 @llvm.test.set.loop.iterations.i32(i32) #4
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #4
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #5
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #5
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
@@ -85,7 +85,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%tmp8 = select <4 x i1> %tmp1, <4 x i32> %add, <4 x i32> %vec.phi
|
||||
%tmp9 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp8)
|
||||
%tmp9 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp8)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -188,7 +188,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%acc = select <4 x i1> %tmp1, <4 x i32> %add, <4 x i32> %vec.phi
|
||||
%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %acc)
|
||||
%reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %acc)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -287,7 +287,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%acc = select <4 x i1> %tmp1, <4 x i32> %add, <4 x i32> %vec.phi
|
||||
%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %acc)
|
||||
%reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %acc)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -386,7 +386,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%acc = select <4 x i1> %tmp1, <4 x i32> %add, <4 x i32> %vec.phi
|
||||
%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %acc)
|
||||
%reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %acc)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -528,6 +528,6 @@ declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
|
||||
|
||||
; Function Attrs: nounwind readnone willreturn
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
|
||||
@@ -56,7 +56,7 @@
|
||||
br i1 %tmp16, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%tmp17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp14)
|
||||
%tmp17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp14)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -64,7 +64,7 @@
|
||||
ret i32 %res.0.lcssa
|
||||
}
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
|
||||
|
||||
@@ -58,7 +58,7 @@
|
||||
br i1 %tmp16, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%tmp17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp14)
|
||||
%tmp17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp14)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -66,7 +66,7 @@
|
||||
ret i32 %res.0.lcssa
|
||||
}
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
|
||||
|
||||
@@ -68,7 +68,7 @@
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%tmp12 = mul nsw <4 x i32> %pass, %tmp10
|
||||
%tmp13 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp12)
|
||||
%tmp13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp12)
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
%tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
|
||||
%tmp16 = icmp ne i32 %tmp15, 0
|
||||
@@ -105,7 +105,7 @@
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%tmp12 = add nsw <4 x i32> %pass, %tmp10
|
||||
%tmp13 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp12)
|
||||
%tmp13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp12)
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
%tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
|
||||
%tmp16 = icmp ne i32 %tmp15, 0
|
||||
@@ -117,7 +117,7 @@
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
br i1 %15, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%16 = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13)
|
||||
%16 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -88,7 +88,7 @@
|
||||
br i1 %15, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%16 = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13)
|
||||
%16 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -98,7 +98,7 @@
|
||||
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
|
||||
|
||||
@@ -91,7 +91,7 @@
|
||||
%22 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %10)
|
||||
%23 = bitcast i16* %lsr.iv7 to i1*
|
||||
%24 = select <4 x i1> %22, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa
|
||||
%25 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %24)
|
||||
%25 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %24)
|
||||
%sunkaddr = mul i32 %i.064.us, 4
|
||||
%26 = bitcast i32* %e to i8*
|
||||
%sunkaddr17 = getelementptr inbounds i8, i8* %26, i32 %sunkaddr
|
||||
@@ -141,7 +141,7 @@
|
||||
}
|
||||
declare dso_local arm_aapcs_vfpcc signext i16 @crc16(...) local_unnamed_addr #0
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
|
||||
|
||||
@@ -69,7 +69,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%7 = select <4 x i1> %1, <4 x i32> %5, <4 x i32> %vec.phi
|
||||
%8 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
%8 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -145,7 +145,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%7 = select <4 x i1> %1, <4 x i32> %5, <4 x i32> %vec.phi
|
||||
%8 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
%8 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -221,7 +221,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%7 = select <4 x i1> %1, <4 x i32> %5, <4 x i32> %vec.phi
|
||||
%8 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
%8 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -297,7 +297,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%7 = select <4 x i1> %1, <4 x i32> %5, <4 x i32> %vec.phi
|
||||
%8 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
%8 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %7)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -371,7 +371,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%6 = select <4 x i1> %1, <4 x i32> %4, <4 x i32> %vec.phi
|
||||
%7 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %6)
|
||||
%7 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %6)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -1273,6 +1273,6 @@ declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
|
||||
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
|
||||
|
||||
@@ -51,7 +51,7 @@ define void @mat_vec_sext_i16(i16** nocapture readonly %A, i16* nocapture readon
|
||||
; CHECK-NEXT: br i1 [[TMP16]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK]]
|
||||
; CHECK: middle.block:
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP14]], <4 x i32> [[VEC_PHI]]
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> [[TMP17]])
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP17]])
|
||||
; CHECK-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8_US]], align 4
|
||||
; CHECK-NEXT: [[INC10_US]] = add nuw i32 [[I_025_US]], 1
|
||||
; CHECK-NEXT: [[EXITCOND27:%.*]] = icmp eq i32 [[INC10_US]], [[N]]
|
||||
@@ -112,7 +112,7 @@ vector.body: ; preds = %vector.body, %for.c
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%tmp17 = select <4 x i1> %tmp7, <4 x i32> %tmp14, <4 x i32> %vec.phi
|
||||
%tmp18 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp17)
|
||||
%tmp18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp17)
|
||||
store i32 %tmp18, i32* %arrayidx8.us, align 4
|
||||
%inc10.us = add nuw i32 %i.025.us, 1
|
||||
%exitcond27 = icmp eq i32 %inc10.us, %N
|
||||
@@ -170,7 +170,7 @@ define void @mat_vec_i32(i32** nocapture readonly %A, i32* nocapture readonly %B
|
||||
; CHECK-NEXT: br i1 [[TMP14]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK]]
|
||||
; CHECK: middle.block:
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP12]], <4 x i32> [[VEC_PHI]]
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> [[TMP15]])
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP15]])
|
||||
; CHECK-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX7_US]], align 4
|
||||
; CHECK-NEXT: [[INC9_US]] = add nuw i32 [[I_024_US]], 1
|
||||
; CHECK-NEXT: [[EXITCOND26:%.*]] = icmp eq i32 [[INC9_US]], [[N]]
|
||||
@@ -229,7 +229,7 @@ vector.body: ; preds = %vector.body, %for.c
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%tmp15 = select <4 x i1> %tmp7, <4 x i32> %tmp12, <4 x i32> %vec.phi
|
||||
%tmp16 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp15)
|
||||
%tmp16 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp15)
|
||||
store i32 %tmp16, i32* %arrayidx7.us, align 4
|
||||
%inc9.us = add nuw i32 %i.024.us, 1
|
||||
%exitcond26 = icmp eq i32 %inc9.us, %N
|
||||
@@ -247,7 +247,7 @@ declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #0
|
||||
|
||||
; Function Attrs: nounwind readnone willreturn
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #1
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #1
|
||||
|
||||
; Function Attrs: noduplicate nounwind
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #2
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
br i1 %tmp15, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%tmp16 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp13)
|
||||
%tmp16 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp13)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -48,7 +48,7 @@
|
||||
ret i32 %res.0.lcssa
|
||||
}
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
%.lcssa = phi <16 x i8> [ %13, %vector.body ]
|
||||
%16 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)
|
||||
%17 = select <16 x i1> %16, <16 x i8> %.lcssa, <16 x i8> %vec.phi.lcssa
|
||||
%18 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %17)
|
||||
%18 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %17)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -53,7 +53,7 @@
|
||||
}
|
||||
|
||||
declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>) #1
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>) #2
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>) #2
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare <16 x i1> @llvm.arm.mve.vctp8(i32) #4
|
||||
|
||||
@@ -36,7 +36,7 @@
|
||||
br i1 %cmp, label %for.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %for.body
|
||||
%reduce = tail call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %acc.next)
|
||||
%reduce = tail call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %acc.next)
|
||||
ret i16 %reduce
|
||||
|
||||
for.cond.cleanup: ; preds = %entry
|
||||
@@ -47,7 +47,7 @@
|
||||
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>) #2
|
||||
declare i1 @llvm.test.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>) #4
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) #4
|
||||
declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
|
||||
|
||||
...
|
||||
|
||||
@@ -41,7 +41,7 @@
|
||||
br i1 %16, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
%17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -88,7 +88,7 @@
|
||||
br i1 %16, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
%17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -135,7 +135,7 @@
|
||||
br i1 %16, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
%17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -182,7 +182,7 @@
|
||||
br i1 %16, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
%17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -228,7 +228,7 @@
|
||||
br i1 %14, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%15 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %12)
|
||||
%15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -274,7 +274,7 @@
|
||||
br i1 %14, label %vector.body, label %middle.block
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%15 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %12)
|
||||
%15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -285,7 +285,7 @@
|
||||
declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>)
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
|
||||
|
||||
@@ -45,7 +45,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load16 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %i3, i32 1, <16 x i1> %active.lane.mask, <16 x i8> undef)
|
||||
%i4 = add <16 x i8> %wide.masked.load, %wide.masked.load16
|
||||
%i5 = select <16 x i1> %active.lane.mask, <16 x i8> %i4, <16 x i8> %vec.phi
|
||||
%i6 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %i5)
|
||||
%i6 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %i5)
|
||||
%index.next = add i32 %index, 16
|
||||
%i7 = icmp eq i32 %index.next, %n.vec
|
||||
br i1 %i7, label %middle.block, label %vector.body
|
||||
@@ -123,7 +123,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i9 = select <8 x i1> %active.lane.mask, <8 x i16> %i7, <8 x i16> %vec.phi
|
||||
%i10 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %i9)
|
||||
%i10 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %i9)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -193,7 +193,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i7 = select <16 x i1> %active.lane.mask, <16 x i8> %i5, <16 x i8> %vec.phi
|
||||
%i8 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %i7)
|
||||
%i8 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %i7)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -265,7 +265,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i9 = select <8 x i1> %active.lane.mask, <8 x i16> %i7, <8 x i16> %vec.phi
|
||||
%i10 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %i9)
|
||||
%i10 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %i9)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -335,7 +335,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i7 = select <16 x i1> %active.lane.mask, <16 x i8> %i5, <16 x i8> %vec.phi
|
||||
%i8 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %i7)
|
||||
%i8 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %i7)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -407,7 +407,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i9 = select <8 x i1> %active.lane.mask, <8 x i16> %i7, <8 x i16> %vec.phi
|
||||
%i10 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %i9)
|
||||
%i10 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %i9)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -504,7 +504,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i9 = select <4 x i1> %active.lane.mask, <4 x i32> %i7, <4 x i32> %vec.phi
|
||||
%i10 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %i9)
|
||||
%i10 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %i9)
|
||||
br i1 %cmp35, label %for.cond.cleanup7, label %vector.ph47
|
||||
|
||||
vector.ph47: ; preds = %middle.block
|
||||
@@ -534,7 +534,7 @@ vector.body46: ; preds = %vector.body46, %vec
|
||||
|
||||
middle.block44: ; preds = %vector.body46
|
||||
%i21 = select <4 x i1> %active.lane.mask61, <4 x i32> %i19, <4 x i32> %vec.phi60
|
||||
%i22 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %i21)
|
||||
%i22 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %i21)
|
||||
br label %for.cond.cleanup7
|
||||
|
||||
for.cond.cleanup7: ; preds = %middle.block44, %middle.block, %entry
|
||||
@@ -620,9 +620,9 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i11 = select <8 x i1> %active.lane.mask, <8 x i16> %i8, <8 x i16> %vec.phi
|
||||
%i12 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %i11)
|
||||
%i12 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %i11)
|
||||
%i13 = select <8 x i1> %active.lane.mask, <8 x i16> %i9, <8 x i16> %vec.phi.1
|
||||
%i14 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %i13)
|
||||
%i14 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %i13)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -747,7 +747,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%10 = select <4 x i1> %active.lane.mask, <4 x i32> %8, <4 x i32> %vec.phi
|
||||
%11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %10)
|
||||
%11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %10)
|
||||
br label %for.end
|
||||
|
||||
for.end: ; preds = %middle.block, %lor.end
|
||||
@@ -758,10 +758,10 @@ for.end: ; preds = %middle.block, %lor.
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
|
||||
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
|
||||
declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
|
||||
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
|
||||
@@ -46,7 +46,7 @@
|
||||
%.lcssa = phi <4 x i32> [ %15, %vector.body ], !dbg !38
|
||||
%18 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %9), !dbg !34
|
||||
%19 = select <4 x i1> %18, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa, !dbg !38
|
||||
%20 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %19), !dbg !32
|
||||
%20 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %19), !dbg !32
|
||||
br label %for.cond.cleanup, !dbg !42
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -58,7 +58,7 @@
|
||||
|
||||
declare void @llvm.dbg.value(metadata, metadata, metadata)
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
|
||||
|
||||
@@ -258,7 +258,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%19 = select <4 x i1> %active.lane.mask, <4 x i32> %16, <4 x i32> %vec.phi
|
||||
%20 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %19)
|
||||
%20 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %19)
|
||||
br label %for.end
|
||||
|
||||
for.end: ; preds = %middle.block, %for.body
|
||||
@@ -282,6 +282,6 @@ declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
|
||||
|
||||
@@ -74,14 +74,14 @@ vector.body: ; preds = %vector.body, %entry
|
||||
br i1 %8, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%9 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %7)
|
||||
%10 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %5)
|
||||
%9 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %7)
|
||||
%10 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %5)
|
||||
store i32 %10, i32* %minp, align 4
|
||||
ret i32 %9
|
||||
}
|
||||
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #1
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>) #3
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>) #3
|
||||
declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>) #3
|
||||
declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>) #3
|
||||
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
%tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7)
|
||||
%tmp9 = sub i32 %tmp7, 8
|
||||
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef)
|
||||
%min = tail call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %wide.masked.load)
|
||||
%min = tail call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %wide.masked.load)
|
||||
store i16 %min, i16* %lsr.iv.2
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 8
|
||||
%scevgep.2 = getelementptr i16, i16* %lsr.iv.2, i32 1
|
||||
@@ -43,7 +43,7 @@
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <8 x i1> @llvm.arm.mve.vctp16(i32)
|
||||
declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 4
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp10)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10)
|
||||
store i32 %tmp11, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
@@ -64,7 +64,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 8
|
||||
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef)
|
||||
%sext = sext <8 x i16> %wide.masked.load to <8 x i32>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %sext)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sext)
|
||||
store i32 %tmp11, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 8
|
||||
@@ -102,7 +102,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 16
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)
|
||||
%sext = sext <16 x i8> %wide.masked.load to <16 x i32>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %sext)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %sext)
|
||||
store i32 %tmp11, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
%scevgep = getelementptr i8, i8* %lsr.iv, i32 16
|
||||
@@ -140,7 +140,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 4
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp10)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10)
|
||||
%acc.next = add i32 %tmp11, %acc
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
%tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
|
||||
@@ -179,7 +179,7 @@
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
store i32 %tmp11, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
@@ -218,7 +218,7 @@
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
%acc.next = add i32 %tmp11, %acc
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
%tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
|
||||
@@ -257,7 +257,7 @@
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
store i32 %tmp11, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
@@ -296,7 +296,7 @@
|
||||
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
|
||||
%tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32>
|
||||
%not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
%tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not)
|
||||
%acc.next = add i32 %tmp11, %acc
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
|
||||
%tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
|
||||
@@ -335,7 +335,7 @@
|
||||
%wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef)
|
||||
%sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16>
|
||||
%sub = sub <8 x i16> %sext.wide, %pass
|
||||
%reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%sext.reduce = sext i16 %reduce to i32
|
||||
store i32 %sext.reduce, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
@@ -375,7 +375,7 @@
|
||||
%wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef)
|
||||
%sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16>
|
||||
%sub = sub <8 x i16> %sext.wide, %pass
|
||||
%reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%sext.reduce = sext i16 %reduce to i32
|
||||
%acc.next = add i32 %sext.reduce, %acc
|
||||
%scevgep = getelementptr i8, i8* %lsr.iv, i32 8
|
||||
@@ -414,7 +414,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 8
|
||||
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef)
|
||||
%sub = sub <8 x i16> %wide.masked.load, %pass
|
||||
%reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%zext.reduce = zext i16 %reduce to i32
|
||||
store i32 %zext.reduce, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
@@ -453,7 +453,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 8
|
||||
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef)
|
||||
%sub = sub <8 x i16> %wide.masked.load, %pass
|
||||
%reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub)
|
||||
%zext.reduce = zext i16 %reduce to i32
|
||||
%acc.next = add i32 %zext.reduce, %acc
|
||||
%scevgep = getelementptr i16, i16* %lsr.iv, i32 8
|
||||
@@ -492,7 +492,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 16
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)
|
||||
%xor = xor <16 x i8> %wide.masked.load, %pass
|
||||
%reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%sext.reduce = sext i8 %reduce to i32
|
||||
store i32 %sext.reduce, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
@@ -531,7 +531,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 16
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)
|
||||
%xor = xor <16 x i8> %wide.masked.load, %pass
|
||||
%reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%sext.reduce = sext i8 %reduce to i32
|
||||
%acc.next = add i32 %sext.reduce, %acc
|
||||
%scevgep = getelementptr i8, i8* %lsr.iv, i32 16
|
||||
@@ -570,7 +570,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 16
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)
|
||||
%xor = xor <16 x i8> %wide.masked.load, %pass
|
||||
%reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%zext.reduce = zext i8 %reduce to i32
|
||||
store i32 %zext.reduce, i32* %store.addr
|
||||
%store.next = getelementptr i32, i32* %store.addr, i32 1
|
||||
@@ -609,7 +609,7 @@
|
||||
%tmp9 = sub i32 %tmp7, 16
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef)
|
||||
%xor = xor <16 x i8> %wide.masked.load, %pass
|
||||
%reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor)
|
||||
%zext.reduce = zext i8 %reduce to i32
|
||||
%acc.next = add i32 %zext.reduce, %acc
|
||||
%scevgep = getelementptr i8, i8* %lsr.iv, i32 16
|
||||
@@ -652,7 +652,7 @@
|
||||
%tmp4 = tail call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %tmp3, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer)
|
||||
%zext.wide.2 = zext <4 x i16> %tmp4 to <4 x i32>
|
||||
%or = or <4 x i32> %zext.wide.1, %zext.wide.2
|
||||
%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %or)
|
||||
%reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %or)
|
||||
%acc.next = add i32 %reduce, %acc
|
||||
%add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 4
|
||||
%add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 4
|
||||
@@ -693,7 +693,7 @@
|
||||
%tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
|
||||
%tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
|
||||
%or = or <8 x i16> %tmp2, %tmp4
|
||||
%reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %or)
|
||||
%reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %or)
|
||||
%zext.reduce = zext i16 %reduce to i32
|
||||
%acc.next = add i32 %zext.reduce, %acc
|
||||
%add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8
|
||||
@@ -737,7 +737,7 @@
|
||||
%tmp5 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1)
|
||||
%tmp6 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 0)
|
||||
%mul = add <4 x i32> %tmp5, %tmp6
|
||||
%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %mul)
|
||||
%reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul)
|
||||
%acc.next = add i32 %reduce, %acc
|
||||
%add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8
|
||||
%add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8
|
||||
@@ -778,7 +778,7 @@
|
||||
%tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
|
||||
%tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
|
||||
%mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1)
|
||||
%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %mul)
|
||||
%reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul)
|
||||
%acc.next = add i32 %reduce, %acc
|
||||
%add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8
|
||||
%add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8
|
||||
@@ -798,11 +798,11 @@
|
||||
declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
|
||||
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32)
|
||||
|
||||
@@ -214,7 +214,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%i19 = select <4 x i1> %active.lane.mask, <4 x i32> %i16, <4 x i32> %vec.phi
|
||||
%i20 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %i19)
|
||||
%i20 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %i19)
|
||||
br label %for.end
|
||||
|
||||
for.end: ; preds = %middle.block, %for.body
|
||||
@@ -235,6 +235,6 @@ for.end17: ; preds = %for.end, %entry
|
||||
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
|
||||
@@ -47,7 +47,7 @@
|
||||
%15 = add i32 %8, 4
|
||||
%16 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %15)
|
||||
%17 = select <4 x i1> %16, <4 x i32> %12, <4 x i32> %vec.phi
|
||||
%18 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %17)
|
||||
%18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %17)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -55,7 +55,7 @@
|
||||
ret i32 %res.0.lcssa
|
||||
}
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
|
||||
|
||||
@@ -46,7 +46,7 @@
|
||||
%.lcssa = phi <8 x i16> [ %15, %vector.body ]
|
||||
%18 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %7)
|
||||
%19 = select <8 x i1> %18, <8 x i16> %.lcssa, <8 x i16> %vec.phi.lcssa
|
||||
%20 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %19)
|
||||
%20 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %19)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -54,7 +54,7 @@
|
||||
ret i16 %a.0.lcssa
|
||||
}
|
||||
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <8 x i1> @llvm.arm.mve.vctp16(i32)
|
||||
|
||||
@@ -70,7 +70,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%8 = select <4 x i1> %1, <4 x i32> %6, <4 x i32> %vec.phi
|
||||
%9 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %8)
|
||||
%9 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %8)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -141,7 +141,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = select <4 x i1> %1, <4 x i32> %3, <4 x i32> %vec.phi
|
||||
%6 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %5)
|
||||
%6 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %5)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -212,7 +212,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = select <4 x i1> %1, <4 x i32> %3, <4 x i32> %vec.phi
|
||||
%6 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %5)
|
||||
%6 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %5)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -459,7 +459,7 @@ declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i
|
||||
declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>)
|
||||
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
|
||||
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
|
||||
; CHECK: middle.block:
|
||||
; CHECK: [[VPSEL:%[^ ]+]] = select <4 x i1> [[VCTP]],
|
||||
; CHECK: call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> [[VPSEL]])
|
||||
; CHECK: call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VPSEL]])
|
||||
|
||||
define i32 @vec_mul_reduce_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32 %N) {
|
||||
entry:
|
||||
@@ -64,7 +64,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%12 = select <4 x i1> %7, <4 x i32> %9, <4 x i32> %vec.phi
|
||||
%13 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %12)
|
||||
%13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -73,7 +73,7 @@ for.cond.cleanup: ; preds = %middle.block, %entr
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
|
||||
@@ -118,7 +118,7 @@
|
||||
middle.block: ; preds = %vector.body
|
||||
%8 = call <4 x i1> @llvm.arm.vctp32(i32 %5)
|
||||
%tmp8 = select <4 x i1> %8, <4 x i32> %tmp6, <4 x i32> %vec.phi
|
||||
%tmp9 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp8)
|
||||
%tmp9 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp8)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -134,7 +134,7 @@
|
||||
declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>)
|
||||
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare <16 x i1> @llvm.arm.vctp8(i32)
|
||||
declare void @llvm.stackprotector(i8*, i8**)
|
||||
declare <8 x i1> @llvm.arm.vctp16(i32)
|
||||
|
||||
@@ -46,7 +46,7 @@
|
||||
%.lcssa = phi <8 x i16> [ %15, %vector.body ]
|
||||
%18 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %7)
|
||||
%19 = select <8 x i1> %18, <8 x i16> %.lcssa, <8 x i16> %vec.phi.lcssa
|
||||
%20 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %19)
|
||||
%20 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %19)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -54,7 +54,7 @@
|
||||
ret i16 %a.0.lcssa
|
||||
}
|
||||
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare void @llvm.set.loop.iterations.i32(i32)
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
|
||||
declare <8 x i1> @llvm.arm.mve.vctp16(i32)
|
||||
|
||||
@@ -52,7 +52,7 @@
|
||||
%n.splat = shufflevector <4 x i32> %insert.n, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%tmp16 = icmp ult <4 x i32> %idx.splat, %n.splat
|
||||
%tmp17 = select <4 x i1> %tmp16, <4 x i32> %tmp13, <4 x i32> %vec.phi
|
||||
%tmp18 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp17)
|
||||
%tmp18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp17)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -60,7 +60,7 @@
|
||||
ret i32 %res.0.lcssa
|
||||
}
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
|
||||
|
||||
@@ -45,7 +45,7 @@
|
||||
middle.block: ; preds = %vector.body
|
||||
%15 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %8)
|
||||
%16 = select <4 x i1> %15, <4 x i32> %12, <4 x i32> %vec.phi
|
||||
%17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %16)
|
||||
%17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %16)
|
||||
br label %for.cond.cleanup
|
||||
|
||||
for.cond.cleanup: ; preds = %middle.block, %entry
|
||||
@@ -53,7 +53,7 @@
|
||||
ret i32 %res.0.lcssa
|
||||
}
|
||||
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
|
||||
declare void @llvm.set.loop.iterations.i32(i32) #3
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
|
||||
|
||||
@@ -572,7 +572,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %10, label %middle.block, label %vector.body, !llvm.loop !7
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
%11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
;for.cond8.for.cond.cleanup10_crit_edge.us.us: ; preds = %for.body11.us.us, %middle.block
|
||||
%add19.us.us = add i32 %j.051.us.us, %mul18.us
|
||||
%arrayidx20.us.us = getelementptr inbounds i32, i32* %C, i32 %add19.us.us
|
||||
@@ -803,7 +803,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %12, label %middle.block, label %vector.body, !llvm.loop !7
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%13 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %11)
|
||||
%13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %11)
|
||||
br i1 %cmp.n, label %for.cond5.for.cond.cleanup7_crit_edge.us.us, label %for.body8.us.us.preheader
|
||||
|
||||
for.cond5.for.cond.cleanup7_crit_edge.us.us: ; preds = %for.body8.us.us, %middle.block
|
||||
@@ -1065,7 +1065,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.gather75 = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %tmp85, i32 1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i8> undef)
|
||||
%tmp86 = sext <4 x i8> %wide.masked.gather75 to <4 x i32>
|
||||
%tmp87 = mul nsw <4 x i32> %tmp84, %tmp86
|
||||
%tmp88 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp87)
|
||||
%tmp88 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp87)
|
||||
%tmp89 = add i32 %tmp88, %vec.phi
|
||||
%index.next = add i32 %index, 4
|
||||
%vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
|
||||
@@ -1091,7 +1091,7 @@ declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <
|
||||
declare <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>)
|
||||
declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32 immarg, <4 x i1>, <4 x i8>) #3
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare void @llvm.memset.p0i8.i32(i8* align 2, i8, i32, i1)
|
||||
|
||||
declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
|
||||
|
||||
@@ -62,7 +62,7 @@ vector.body: ; preds = %vector.body, %entry
|
||||
br i1 %8, label %middle.block, label %vector.body
|
||||
middle.block: ; preds = %vector.body
|
||||
%9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi
|
||||
%10 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
%10 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
store i32 %10, i32* %arrayidx.us.us, align 4
|
||||
%inc21.us.us = add nuw i32 4, 1
|
||||
%exitcond81.not = icmp eq i32 %inc21.us.us, %n
|
||||
@@ -139,7 +139,7 @@ vector.body: ; preds = %vector.body, %entry
|
||||
br i1 %8, label %middle.block, label %vector.body
|
||||
middle.block: ; preds = %vector.body
|
||||
%9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi
|
||||
%10 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
%10 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
store i32 %10, i32* %arrayidx.us.us, align 4
|
||||
%inc21.us.us = add nuw i32 4, 1
|
||||
%exitcond81.not = icmp eq i32 %inc21.us.us, %n
|
||||
@@ -210,7 +210,7 @@ vector.body: ; preds = %vector.body, %entry
|
||||
br i1 %8, label %middle.block, label %vector.body
|
||||
middle.block: ; preds = %vector.body
|
||||
%9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi
|
||||
%10 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
%10 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %9)
|
||||
store i32 %10, i32* %arrayidx.us.us, align 4
|
||||
%inc21.us.us = add nuw i32 4, 1
|
||||
%exitcond81.not = icmp eq i32 %inc21.us.us, %n
|
||||
@@ -440,7 +440,7 @@ for.cond.cleanup: ; preds = %vector.body, %for.b
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
|
||||
declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32, <4 x i1>, <4 x i8>)
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
|
||||
@@ -1390,7 +1390,7 @@ declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4
|
||||
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32, <8 x i1>, <8 x i8>)
|
||||
declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
|
||||
declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i8(<16 x i32> %ext4)
|
||||
declare i32 @llvm.vector.reduce.add.v16i8(<16 x i32> %ext4)
|
||||
declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>)
|
||||
declare i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32, i32, i32, i32, <16 x i8>, <16 x i8>, <16 x i1>)
|
||||
declare i32 @llvm.arm.mve.vmldava.predicated.v8i16.v8i1(i32, i32, i32, i32, <8 x i16>, <8 x i16>, <8 x i1>)
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
|
||||
|
||||
declare i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8>)
|
||||
declare i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64>)
|
||||
declare i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32>)
|
||||
declare i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16>)
|
||||
declare i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8>)
|
||||
|
||||
define arm_aapcs_vfpcc i64 @vaddv_v2i64_i64(<2 x i64> %s1) {
|
||||
; CHECK-LABEL: vaddv_v2i64_i64:
|
||||
@@ -20,7 +20,7 @@ define arm_aapcs_vfpcc i64 @vaddv_v2i64_i64(<2 x i64> %s1) {
|
||||
; CHECK-NEXT: adcs r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%r = call i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
|
||||
%r = call i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
@@ -30,7 +30,7 @@ define arm_aapcs_vfpcc i32 @vaddv_v4i32_i32(<4 x i32> %s1) {
|
||||
; CHECK-NEXT: vaddv.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%r = call i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
|
||||
%r = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -41,7 +41,7 @@ define arm_aapcs_vfpcc i32 @vaddv_v8i32_i32(<8 x i32> %s1) {
|
||||
; CHECK-NEXT: vaddv.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%r = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
|
||||
%r = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
@@ -51,7 +51,7 @@ define arm_aapcs_vfpcc i16 @vaddv_v8i16_i16(<8 x i16> %s1) {
|
||||
; CHECK-NEXT: vaddv.u16 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%r = call i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
|
||||
%r = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
@@ -62,7 +62,7 @@ define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<16 x i16> %s1) {
|
||||
; CHECK-NEXT: vaddv.u16 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%r = call i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
|
||||
%r = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
@@ -72,7 +72,7 @@ define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) {
|
||||
; CHECK-NEXT: vaddv.u8 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%r = call i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
|
||||
%r = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -83,7 +83,7 @@ define arm_aapcs_vfpcc i8 @vaddv_v32i8_i8(<32 x i8> %s1) {
|
||||
; CHECK-NEXT: vaddv.u8 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%r = call i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
|
||||
%r = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -102,7 +102,7 @@ define arm_aapcs_vfpcc i64 @vaddva_v2i64_i64(<2 x i64> %s1, i64 %x) {
|
||||
; CHECK-NEXT: adcs r1, r3
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%t = call i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
|
||||
%t = call i64 @llvm.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
|
||||
%r = add i64 %t, %x
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -113,7 +113,7 @@ define arm_aapcs_vfpcc i32 @vaddva_v4i32_i32(<4 x i32> %s1, i32 %x) {
|
||||
; CHECK-NEXT: vaddva.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%t = call i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
|
||||
%t = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
|
||||
%r = add i32 %t, %x
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -125,7 +125,7 @@ define arm_aapcs_vfpcc i32 @vaddva_v8i32_i32(<8 x i32> %s1, i32 %x) {
|
||||
; CHECK-NEXT: vaddva.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%t = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
|
||||
%t = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
|
||||
%r = add i32 %t, %x
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -136,7 +136,7 @@ define arm_aapcs_vfpcc i16 @vaddva_v8i16_i16(<8 x i16> %s1, i16 %x) {
|
||||
; CHECK-NEXT: vaddva.u16 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%t = call i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
|
||||
%t = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
|
||||
%r = add i16 %t, %x
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -148,7 +148,7 @@ define arm_aapcs_vfpcc i16 @vaddva_v16i16_i16(<16 x i16> %s1, i16 %x) {
|
||||
; CHECK-NEXT: vaddva.u16 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%t = call i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
|
||||
%t = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
|
||||
%r = add i16 %t, %x
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -159,7 +159,7 @@ define arm_aapcs_vfpcc i8 @vaddva_v16i8_i8(<16 x i8> %s1, i8 %x) {
|
||||
; CHECK-NEXT: vaddva.u8 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%t = call i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
|
||||
%t = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
|
||||
%r = add i8 %t, %x
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -171,7 +171,7 @@ define arm_aapcs_vfpcc i8 @vaddva_v32i8_i8(<32 x i8> %s1, i8 %x) {
|
||||
; CHECK-NEXT: vaddva.u8 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%t = call i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
|
||||
%t = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
|
||||
%r = add i8 %t, %x
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
@@ -7,7 +7,7 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x) {
|
||||
; CHECK-NEXT: vaddv.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -18,7 +18,7 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <4 x i32> %x to <4 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -29,7 +29,7 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <4 x i32> %x to <4 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -47,7 +47,7 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_zext(<2 x i32> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <2 x i32> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -65,7 +65,7 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <2 x i32> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -76,7 +76,7 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -87,7 +87,7 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -99,7 +99,7 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <4 x i16> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -111,7 +111,7 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <4 x i16> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -122,7 +122,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x) {
|
||||
; CHECK-NEXT: uxth r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -175,7 +175,7 @@ define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_zext(<8 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -242,7 +242,7 @@ define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_sext(<8 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -258,7 +258,7 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_zext(<2 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <2 x i16> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -278,7 +278,7 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_sext(<2 x i16> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <2 x i16> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -289,7 +289,7 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -300,7 +300,7 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -313,7 +313,7 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <4 x i8> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -326,7 +326,7 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <4 x i8> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -338,7 +338,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_zext(<16 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -350,7 +350,7 @@ define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_sext(<16 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -363,7 +363,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <8 x i8> %x to <8 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -376,7 +376,7 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <8 x i8> %x to <8 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -387,7 +387,7 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x) {
|
||||
; CHECK-NEXT: uxtb r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -492,7 +492,7 @@ define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_zext(<16 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -627,7 +627,7 @@ define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_sext(<16 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -643,7 +643,7 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_zext(<2 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <2 x i8> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -663,7 +663,7 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_sext(<2 x i8> %x) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <2 x i8> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -678,7 +678,7 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x) {
|
||||
; CHECK-NEXT: adcs r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -688,7 +688,7 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, i32 %a) {
|
||||
; CHECK-NEXT: vaddva.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %x)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -700,7 +700,7 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_zext(<4 x i32> %x, i64 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <4 x i32> %x to <4 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -712,7 +712,7 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_sext(<4 x i32> %x, i64 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <4 x i32> %x to <4 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -735,7 +735,7 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_zext(<2 x i32> %x, i64 %a) {
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%xx = zext <2 x i32> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -756,7 +756,7 @@ define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, i64 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <2 x i32> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -768,7 +768,7 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_zext(<8 x i16> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -780,7 +780,7 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_sext(<8 x i16> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -793,7 +793,7 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <4 x i16> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -806,7 +806,7 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <4 x i16> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -818,7 +818,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, i16 %a) {
|
||||
; CHECK-NEXT: uxth r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %x)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -876,7 +876,7 @@ define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_zext(<8 x i16> %x, i64 %a) {
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -948,7 +948,7 @@ define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_sext(<8 x i16> %x, i64 %a) {
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -967,7 +967,7 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_zext(<2 x i16> %x, i64 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <2 x i16> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -990,7 +990,7 @@ define arm_aapcs_vfpcc i64 @add_v2i16_v2i64_acc_sext(<2 x i16> %x, i64 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <2 x i16> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1002,7 +1002,7 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1014,7 +1014,7 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_sext(<16 x i8> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1028,7 +1028,7 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <4 x i8> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1042,7 +1042,7 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, i32 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <4 x i8> %x to <4 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1055,7 +1055,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_acc_zext(<16 x i8> %x, i16
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1068,7 +1068,7 @@ define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_acc_sext(<16 x i8> %x, i16
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1082,7 +1082,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, i16 %a)
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <8 x i8> %x to <8 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1096,7 +1096,7 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, i16 %a)
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <8 x i8> %x to <8 x i16>
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1108,7 +1108,7 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, i8 %a) {
|
||||
; CHECK-NEXT: uxtb r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %x)
|
||||
%r = add i8 %z, %a
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -1218,7 +1218,7 @@ define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_zext(<16 x i8> %x, i64 %a) {
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1358,7 +1358,7 @@ define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_sext(<16 x i8> %x, i64 %a) {
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1377,7 +1377,7 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, i64 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = zext <2 x i8> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1400,7 +1400,7 @@ define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_sext(<2 x i8> %x, i64 %a) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%xx = sext <2 x i8> %x to <2 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1420,18 +1420,18 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, i64 %a) {
|
||||
; CHECK-NEXT: adcs r1, r3
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %x)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
|
||||
@@ -10,7 +10,7 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %b) {
|
||||
entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -24,7 +24,7 @@ entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%xx = zext <4 x i32> %x to <4 x i64>
|
||||
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -38,7 +38,7 @@ entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%xx = sext <4 x i32> %x to <4 x i64>
|
||||
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -73,7 +73,7 @@ entry:
|
||||
%c = icmp eq <2 x i32> %b, zeroinitializer
|
||||
%xx = zext <2 x i32> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -114,7 +114,7 @@ entry:
|
||||
%c = icmp eq <2 x i32> %b, zeroinitializer
|
||||
%xx = sext <2 x i32> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -128,7 +128,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = zext <8 x i16> %x to <8 x i32>
|
||||
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -142,7 +142,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -158,7 +158,7 @@ entry:
|
||||
%c = icmp eq <4 x i16> %b, zeroinitializer
|
||||
%xx = zext <4 x i16> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -174,7 +174,7 @@ entry:
|
||||
%c = icmp eq <4 x i16> %b, zeroinitializer
|
||||
%xx = sext <4 x i16> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -188,7 +188,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %b)
|
||||
entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -314,7 +314,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = zext <8 x i16> %x to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -456,7 +456,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = sext <8 x i16> %x to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -492,7 +492,7 @@ entry:
|
||||
%c = icmp eq <2 x i16> %b, zeroinitializer
|
||||
%xx = zext <2 x i16> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -537,7 +537,7 @@ entry:
|
||||
%c = icmp eq <2 x i16> %b, zeroinitializer
|
||||
%xx = sext <2 x i16> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -551,7 +551,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = zext <16 x i8> %x to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -565,7 +565,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = sext <16 x i8> %x to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -582,7 +582,7 @@ entry:
|
||||
%c = icmp eq <4 x i8> %b, zeroinitializer
|
||||
%xx = zext <4 x i8> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -600,7 +600,7 @@ entry:
|
||||
%c = icmp eq <4 x i8> %b, zeroinitializer
|
||||
%xx = sext <4 x i8> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -615,7 +615,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = zext <16 x i8> %x to <16 x i16>
|
||||
%s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -630,7 +630,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -647,7 +647,7 @@ entry:
|
||||
%c = icmp eq <8 x i8> %b, zeroinitializer
|
||||
%xx = zext <8 x i8> %x to <8 x i16>
|
||||
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -664,7 +664,7 @@ entry:
|
||||
%c = icmp eq <8 x i8> %b, zeroinitializer
|
||||
%xx = sext <8 x i8> %x to <8 x i16>
|
||||
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -678,7 +678,7 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %b) {
|
||||
entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -948,7 +948,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = zext <16 x i8> %x to <16 x i64>
|
||||
%s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1257,7 +1257,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = sext <16 x i8> %x to <16 x i64>
|
||||
%s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1293,7 +1293,7 @@ entry:
|
||||
%c = icmp eq <2 x i8> %b, zeroinitializer
|
||||
%xx = zext <2 x i8> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1338,7 +1338,7 @@ entry:
|
||||
%c = icmp eq <2 x i8> %b, zeroinitializer
|
||||
%xx = sext <2 x i8> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1372,7 +1372,7 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %b) {
|
||||
entry:
|
||||
%c = icmp eq <2 x i64> %b, zeroinitializer
|
||||
%s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1385,7 +1385,7 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %b, i32
|
||||
entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1400,7 +1400,7 @@ entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%xx = zext <4 x i32> %x to <4 x i64>
|
||||
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1415,7 +1415,7 @@ entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%xx = sext <4 x i32> %x to <4 x i64>
|
||||
%s = select <4 x i1> %c, <4 x i64> %xx, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1455,7 +1455,7 @@ entry:
|
||||
%c = icmp eq <2 x i32> %b, zeroinitializer
|
||||
%xx = zext <2 x i32> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1501,7 +1501,7 @@ entry:
|
||||
%c = icmp eq <2 x i32> %b, zeroinitializer
|
||||
%xx = sext <2 x i32> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1516,7 +1516,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = zext <8 x i16> %x to <8 x i32>
|
||||
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1531,7 +1531,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%s = select <8 x i1> %c, <8 x i32> %xx, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1548,7 +1548,7 @@ entry:
|
||||
%c = icmp eq <4 x i16> %b, zeroinitializer
|
||||
%xx = zext <4 x i16> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1565,7 +1565,7 @@ entry:
|
||||
%c = icmp eq <4 x i16> %b, zeroinitializer
|
||||
%xx = sext <4 x i16> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1580,7 +1580,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16>
|
||||
entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1711,7 +1711,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = zext <8 x i16> %x to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1858,7 +1858,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%xx = sext <8 x i16> %x to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %xx, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1897,7 +1897,7 @@ entry:
|
||||
%c = icmp eq <2 x i16> %b, zeroinitializer
|
||||
%xx = zext <2 x i16> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1947,7 +1947,7 @@ entry:
|
||||
%c = icmp eq <2 x i16> %b, zeroinitializer
|
||||
%xx = sext <2 x i16> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1962,7 +1962,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = zext <16 x i8> %x to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1977,7 +1977,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = sext <16 x i8> %x to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %xx, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1995,7 +1995,7 @@ entry:
|
||||
%c = icmp eq <4 x i8> %b, zeroinitializer
|
||||
%xx = zext <4 x i8> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -2014,7 +2014,7 @@ entry:
|
||||
%c = icmp eq <4 x i8> %b, zeroinitializer
|
||||
%xx = sext <4 x i8> %x to <4 x i32>
|
||||
%s = select <4 x i1> %c, <4 x i32> %xx, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -2030,7 +2030,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = zext <16 x i8> %x to <16 x i16>
|
||||
%s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2046,7 +2046,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%s = select <16 x i1> %c, <16 x i16> %xx, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2064,7 +2064,7 @@ entry:
|
||||
%c = icmp eq <8 x i8> %b, zeroinitializer
|
||||
%xx = zext <8 x i8> %x to <8 x i16>
|
||||
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2082,7 +2082,7 @@ entry:
|
||||
%c = icmp eq <8 x i8> %b, zeroinitializer
|
||||
%xx = sext <8 x i8> %x to <8 x i16>
|
||||
%s = select <8 x i1> %c, <8 x i16> %xx, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2097,7 +2097,7 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %
|
||||
entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> zeroinitializer
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
%r = add i8 %z, %a
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -2372,7 +2372,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = zext <16 x i8> %x to <16 x i64>
|
||||
%s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -2686,7 +2686,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%xx = sext <16 x i8> %x to <16 x i64>
|
||||
%s = select <16 x i1> %c, <16 x i64> %xx, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -2725,7 +2725,7 @@ entry:
|
||||
%c = icmp eq <2 x i8> %b, zeroinitializer
|
||||
%xx = zext <2 x i8> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -2775,7 +2775,7 @@ entry:
|
||||
%c = icmp eq <2 x i8> %b, zeroinitializer
|
||||
%xx = sext <2 x i8> %x to <2 x i64>
|
||||
%s = select <2 x i1> %c, <2 x i64> %xx, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -2814,18 +2814,18 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %b, i64
|
||||
entry:
|
||||
%c = icmp eq <2 x i64> %b, zeroinitializer
|
||||
%s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
|
||||
@@ -9,7 +9,7 @@ define arm_aapcs_vfpcc i32 @and_v2i32(<2 x i32> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -25,7 +25,7 @@ define arm_aapcs_vfpcc i32 @and_v4i32(<4 x i32> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -42,7 +42,7 @@ define arm_aapcs_vfpcc i32 @and_v8i32(<8 x i32> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -58,7 +58,7 @@ define arm_aapcs_vfpcc i16 @and_v4i16(<4 x i16> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -76,7 +76,7 @@ define arm_aapcs_vfpcc i16 @and_v8i16(<8 x i16> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -95,7 +95,7 @@ define arm_aapcs_vfpcc i16 @and_v16i16(<16 x i16> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -113,7 +113,7 @@ define arm_aapcs_vfpcc i8 @and_v8i8(<8 x i8> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -133,7 +133,7 @@ define arm_aapcs_vfpcc i8 @and_v16i8(<16 x i8> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -154,7 +154,7 @@ define arm_aapcs_vfpcc i8 @and_v32i8(<32 x i8> %x) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -163,7 +163,7 @@ define arm_aapcs_vfpcc i64 @and_v1i64(<1 x i64> %x) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -178,7 +178,7 @@ define arm_aapcs_vfpcc i64 @and_v2i64(<2 x i64> %x) {
|
||||
; CHECK-NEXT: ands r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -194,7 +194,7 @@ define arm_aapcs_vfpcc i64 @and_v4i64(<4 x i64> %x) {
|
||||
; CHECK-NEXT: ands r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -207,7 +207,7 @@ define arm_aapcs_vfpcc i32 @and_v2i32_acc(<2 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %x)
|
||||
%r = and i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -225,7 +225,7 @@ define arm_aapcs_vfpcc i32 @and_v4i32_acc(<4 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %x)
|
||||
%r = and i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -244,7 +244,7 @@ define arm_aapcs_vfpcc i32 @and_v8i32_acc(<8 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %x)
|
||||
%r = and i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -262,7 +262,7 @@ define arm_aapcs_vfpcc i16 @and_v4i16_acc(<4 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %x)
|
||||
%r = and i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -282,7 +282,7 @@ define arm_aapcs_vfpcc i16 @and_v8i16_acc(<8 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %x)
|
||||
%r = and i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -303,7 +303,7 @@ define arm_aapcs_vfpcc i16 @and_v16i16_acc(<16 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %x)
|
||||
%r = and i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -323,7 +323,7 @@ define arm_aapcs_vfpcc i8 @and_v8i8_acc(<8 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %x)
|
||||
%r = and i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -345,7 +345,7 @@ define arm_aapcs_vfpcc i8 @and_v16i8_acc(<16 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %x)
|
||||
%r = and i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -368,7 +368,7 @@ define arm_aapcs_vfpcc i8 @and_v32i8_acc(<32 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: ands r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %x)
|
||||
%r = and i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -380,7 +380,7 @@ define arm_aapcs_vfpcc i64 @and_v1i64_acc(<1 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: ands r1, r3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %x)
|
||||
%r = and i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -398,7 +398,7 @@ define arm_aapcs_vfpcc i64 @and_v2i64_acc(<2 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: ands r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %x)
|
||||
%r = and i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -417,7 +417,7 @@ define arm_aapcs_vfpcc i64 @and_v4i64_acc(<4 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: ands r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %x)
|
||||
%r = and i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -430,7 +430,7 @@ define arm_aapcs_vfpcc i32 @or_v2i32(<2 x i32> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -446,7 +446,7 @@ define arm_aapcs_vfpcc i32 @or_v4i32(<4 x i32> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -463,7 +463,7 @@ define arm_aapcs_vfpcc i32 @or_v8i32(<8 x i32> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -479,7 +479,7 @@ define arm_aapcs_vfpcc i16 @or_v4i16(<4 x i16> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -497,7 +497,7 @@ define arm_aapcs_vfpcc i16 @or_v8i16(<8 x i16> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -516,7 +516,7 @@ define arm_aapcs_vfpcc i16 @or_v16i16(<16 x i16> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -534,7 +534,7 @@ define arm_aapcs_vfpcc i8 @or_v8i8(<8 x i8> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -554,7 +554,7 @@ define arm_aapcs_vfpcc i8 @or_v16i8(<16 x i8> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -575,7 +575,7 @@ define arm_aapcs_vfpcc i8 @or_v32i8(<32 x i8> %x) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -584,7 +584,7 @@ define arm_aapcs_vfpcc i64 @or_v1i64(<1 x i64> %x) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -599,7 +599,7 @@ define arm_aapcs_vfpcc i64 @or_v2i64(<2 x i64> %x) {
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -615,7 +615,7 @@ define arm_aapcs_vfpcc i64 @or_v4i64(<4 x i64> %x) {
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -628,7 +628,7 @@ define arm_aapcs_vfpcc i32 @or_v2i32_acc(<2 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %x)
|
||||
%r = or i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -646,7 +646,7 @@ define arm_aapcs_vfpcc i32 @or_v4i32_acc(<4 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %x)
|
||||
%r = or i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -665,7 +665,7 @@ define arm_aapcs_vfpcc i32 @or_v8i32_acc(<8 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %x)
|
||||
%r = or i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -683,7 +683,7 @@ define arm_aapcs_vfpcc i16 @or_v4i16_acc(<4 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %x)
|
||||
%r = or i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -703,7 +703,7 @@ define arm_aapcs_vfpcc i16 @or_v8i16_acc(<8 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %x)
|
||||
%r = or i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -724,7 +724,7 @@ define arm_aapcs_vfpcc i16 @or_v16i16_acc(<16 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %x)
|
||||
%r = or i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -744,7 +744,7 @@ define arm_aapcs_vfpcc i8 @or_v8i8_acc(<8 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %x)
|
||||
%r = or i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -766,7 +766,7 @@ define arm_aapcs_vfpcc i8 @or_v16i8_acc(<16 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %x)
|
||||
%r = or i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -789,7 +789,7 @@ define arm_aapcs_vfpcc i8 @or_v32i8_acc(<32 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %x)
|
||||
%r = or i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -801,7 +801,7 @@ define arm_aapcs_vfpcc i64 @or_v1i64_acc(<1 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: orrs r1, r3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %x)
|
||||
%r = or i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -819,7 +819,7 @@ define arm_aapcs_vfpcc i64 @or_v2i64_acc(<2 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %x)
|
||||
%r = or i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -838,7 +838,7 @@ define arm_aapcs_vfpcc i64 @or_v4i64_acc(<4 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: orrs r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %x)
|
||||
%r = or i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -851,7 +851,7 @@ define arm_aapcs_vfpcc i32 @xor_v2i32(<2 x i32> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -867,7 +867,7 @@ define arm_aapcs_vfpcc i32 @xor_v4i32(<4 x i32> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -884,7 +884,7 @@ define arm_aapcs_vfpcc i32 @xor_v8i32(<8 x i32> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %x)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -900,7 +900,7 @@ define arm_aapcs_vfpcc i16 @xor_v4i16(<4 x i16> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -918,7 +918,7 @@ define arm_aapcs_vfpcc i16 @xor_v8i16(<8 x i16> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -937,7 +937,7 @@ define arm_aapcs_vfpcc i16 @xor_v16i16(<16 x i16> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %x)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -955,7 +955,7 @@ define arm_aapcs_vfpcc i8 @xor_v8i8(<8 x i8> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -975,7 +975,7 @@ define arm_aapcs_vfpcc i8 @xor_v16i8(<16 x i8> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -996,7 +996,7 @@ define arm_aapcs_vfpcc i8 @xor_v32i8(<32 x i8> %x) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %x)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -1005,7 +1005,7 @@ define arm_aapcs_vfpcc i64 @xor_v1i64(<1 x i64> %x) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1020,7 +1020,7 @@ define arm_aapcs_vfpcc i64 @xor_v2i64(<2 x i64> %x) {
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1036,7 +1036,7 @@ define arm_aapcs_vfpcc i64 @xor_v4i64(<4 x i64> %x) {
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %x)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1049,7 +1049,7 @@ define arm_aapcs_vfpcc i32 @xor_v2i32_acc(<2 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %x)
|
||||
%r = xor i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1067,7 +1067,7 @@ define arm_aapcs_vfpcc i32 @xor_v4i32_acc(<4 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %x)
|
||||
%r = xor i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1086,7 +1086,7 @@ define arm_aapcs_vfpcc i32 @xor_v8i32_acc(<8 x i32> %x, i32 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> %x)
|
||||
%z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %x)
|
||||
%r = xor i32 %y, %z
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1104,7 +1104,7 @@ define arm_aapcs_vfpcc i16 @xor_v4i16_acc(<4 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %x)
|
||||
%r = xor i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1124,7 +1124,7 @@ define arm_aapcs_vfpcc i16 @xor_v8i16_acc(<8 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %x)
|
||||
%r = xor i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1145,7 +1145,7 @@ define arm_aapcs_vfpcc i16 @xor_v16i16_acc(<16 x i16> %x, i16 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> %x)
|
||||
%z = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %x)
|
||||
%r = xor i16 %y, %z
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1165,7 +1165,7 @@ define arm_aapcs_vfpcc i8 @xor_v8i8_acc(<8 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %x)
|
||||
%r = xor i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -1187,7 +1187,7 @@ define arm_aapcs_vfpcc i8 @xor_v16i8_acc(<16 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %x)
|
||||
%r = xor i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -1210,7 +1210,7 @@ define arm_aapcs_vfpcc i8 @xor_v32i8_acc(<32 x i8> %x, i8 %y) {
|
||||
; CHECK-NEXT: eors r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> %x)
|
||||
%z = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %x)
|
||||
%r = xor i8 %y, %z
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -1222,7 +1222,7 @@ define arm_aapcs_vfpcc i64 @xor_v1i64_acc(<1 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: eors r1, r3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %x)
|
||||
%r = xor i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1240,7 +1240,7 @@ define arm_aapcs_vfpcc i64 @xor_v2i64_acc(<2 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %x)
|
||||
%r = xor i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1259,44 +1259,44 @@ define arm_aapcs_vfpcc i64 @xor_v4i64_acc(<4 x i64> %x, i64 %y) {
|
||||
; CHECK-NEXT: eors r1, r2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> %x)
|
||||
%z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %x)
|
||||
%r = xor i64 %y, %z
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8>)
|
||||
declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
|
||||
declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
|
||||
declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
|
||||
declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
|
||||
|
||||
@@ -9,7 +9,7 @@ define arm_aapcs_vfpcc float @fadd_v2f32(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vadd.f32 s0, s4, s0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float %y, <2 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float %y, <2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -30,7 +30,7 @@ define arm_aapcs_vfpcc float @fadd_v4f32(<4 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vadd.f32 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %y, <4 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %y, <4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -56,7 +56,7 @@ define arm_aapcs_vfpcc float @fadd_v8f32(<8 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vadd.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v8f32(float %y, <8 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float %y, <8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -71,7 +71,7 @@ define arm_aapcs_vfpcc void @fadd_v2f16(<2 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v2f16(half %y, <2 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fadd.f16.v2f16(half %y, <2 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -102,7 +102,7 @@ define arm_aapcs_vfpcc void @fadd_v4f16(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half %y, <4 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fadd.f16.v4f16(half %y, <4 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -139,7 +139,7 @@ define arm_aapcs_vfpcc void @fadd_v8f16(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v8f16(half %y, <8 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fadd.f16.v8f16(half %y, <8 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -189,7 +189,7 @@ define arm_aapcs_vfpcc void @fadd_v16f16(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v16f16(half %y, <16 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fadd.f16.v16f16(half %y, <16 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -200,7 +200,7 @@ define arm_aapcs_vfpcc double @fadd_v1f64(<1 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vadd.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double %y, <1 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fadd.f64.v1f64(double %y, <1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -211,7 +211,7 @@ define arm_aapcs_vfpcc double @fadd_v2f64(<2 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vadd.f64 d0, d2, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double %y, <2 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double %y, <2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -224,7 +224,7 @@ define arm_aapcs_vfpcc double @fadd_v4f64(<4 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vadd.f64 d0, d4, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v4f64(double %y, <4 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fadd.f64.v4f64(double %y, <4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -235,7 +235,7 @@ define arm_aapcs_vfpcc float @fadd_v2f32_nofast(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vadd.f32 s0, s4, s1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float %y, <2 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fadd.f32.v2f32(float %y, <2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -248,7 +248,7 @@ define arm_aapcs_vfpcc float @fadd_v4f32_nofast(<4 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vadd.f32 s0, s4, s3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %y, <4 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fadd.f32.v4f32(float %y, <4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -265,7 +265,7 @@ define arm_aapcs_vfpcc float @fadd_v8f32_nofast(<8 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vadd.f32 s0, s0, s7
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v8f32(float %y, <8 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fadd.f32.v8f32(float %y, <8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -283,7 +283,7 @@ define arm_aapcs_vfpcc void @fadd_v4f16_nofast(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half %y, <4 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fadd.f16.v4f16(half %y, <4 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -308,7 +308,7 @@ define arm_aapcs_vfpcc void @fadd_v8f16_nofast(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v8f16(half %y, <8 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fadd.f16.v8f16(half %y, <8 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -345,7 +345,7 @@ define arm_aapcs_vfpcc void @fadd_v16f16_nofast(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v16f16(half %y, <16 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fadd.f16.v16f16(half %y, <16 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -356,7 +356,7 @@ define arm_aapcs_vfpcc double @fadd_v1f64_nofast(<1 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vadd.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double %y, <1 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fadd.f64.v1f64(double %y, <1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -367,7 +367,7 @@ define arm_aapcs_vfpcc double @fadd_v2f64_nofast(<2 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vadd.f64 d0, d2, d1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double %y, <2 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fadd.f64.v2f64(double %y, <2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -380,17 +380,17 @@ define arm_aapcs_vfpcc double @fadd_v4f64_nofast(<4 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vadd.f64 d0, d0, d3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.v2.fadd.f64.v4f64(double %y, <4 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fadd.f64.v4f64(double %y, <4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double, <2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v4f64(double, <4 x double>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float, <2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v8f32(float, <8 x float>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v16f16(half, <16 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v2f16(half, <2 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half, <4 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v8f16(half, <8 x half>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v2f64(double, <2 x double>)
|
||||
declare double @llvm.vector.reduce.fadd.f64.v4f64(double, <4 x double>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v2f32(float, <2 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v16f16(half, <16 x half>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v2f16(half, <2 x half>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v4f16(half, <4 x half>)
|
||||
declare half @llvm.vector.reduce.fadd.f16.v8f16(half, <8 x half>)
|
||||
|
||||
@@ -8,7 +8,7 @@ define arm_aapcs_vfpcc float @fmin_v2f32(<2 x float> %x) {
|
||||
; CHECK-NEXT: vminnm.f32 s0, s0, s1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -27,7 +27,7 @@ define arm_aapcs_vfpcc float @fmin_v4f32(<4 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s3
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -60,7 +60,7 @@ define arm_aapcs_vfpcc float @fmin_v8f32(<8 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f32 s0, s2, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -83,7 +83,7 @@ define arm_aapcs_vfpcc half @fmin_v4f16(<4 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -112,7 +112,7 @@ define arm_aapcs_vfpcc half @fmin_v8f16(<8 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -170,7 +170,7 @@ define arm_aapcs_vfpcc half @fmin_v16f16(<16 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f16 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -179,7 +179,7 @@ define arm_aapcs_vfpcc double @fmin_v1f64(<1 x double> %x) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -189,7 +189,7 @@ define arm_aapcs_vfpcc double @fmin_v2f64(<2 x double> %x) {
|
||||
; CHECK-NEXT: vminnm.f64 d0, d0, d1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -205,7 +205,7 @@ define arm_aapcs_vfpcc double @fmin_v4f64(<4 x double> %x) {
|
||||
; CHECK-NEXT: vminnm.f64 d0, d0, d4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -215,7 +215,7 @@ define arm_aapcs_vfpcc float @fmin_v2f32_nofast(<2 x float> %x) {
|
||||
; CHECK-NEXT: vminnm.f32 s0, s0, s1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -234,7 +234,7 @@ define arm_aapcs_vfpcc float @fmin_v4f32_nofast(<4 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s3
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -258,7 +258,7 @@ define arm_aapcs_vfpcc float @fmin_v8f32_nofast(<8 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -281,7 +281,7 @@ define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -310,7 +310,7 @@ define arm_aapcs_vfpcc half @fmin_v8f16_nofast(<8 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -352,7 +352,7 @@ define arm_aapcs_vfpcc half @fmin_v16f16_nofast(<16 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f16 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -361,7 +361,7 @@ define arm_aapcs_vfpcc double @fmin_v1f64_nofast(<1 x double> %x) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -371,7 +371,7 @@ define arm_aapcs_vfpcc double @fmin_v2f64_nofast(<2 x double> %x) {
|
||||
; CHECK-NEXT: vminnm.f64 d0, d0, d1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -383,7 +383,7 @@ define arm_aapcs_vfpcc double @fmin_v4f64_nofast(<4 x double> %x) {
|
||||
; CHECK-NEXT: vminnm.f64 d0, d0, d4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -394,7 +394,7 @@ define arm_aapcs_vfpcc float @fmin_v2f32_acc(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vminnm.f32 s0, s4, s0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
%c = fcmp fast olt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -417,7 +417,7 @@ define arm_aapcs_vfpcc float @fmin_v4f32_acc(<4 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
%c = fcmp fast olt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -453,7 +453,7 @@ define arm_aapcs_vfpcc float @fmin_v8f32_acc(<8 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vminnm.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
%c = fcmp fast olt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -485,7 +485,7 @@ define arm_aapcs_vfpcc void @fmin_v4f16_acc(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
%c = fcmp fast olt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -503,7 +503,7 @@ define arm_aapcs_vfpcc void @fmin_v2f16_acc(<2 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmin.v2f16(<2 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmin.v2f16(<2 x half> %x)
|
||||
%c = fcmp fast olt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -542,7 +542,7 @@ define arm_aapcs_vfpcc void @fmin_v8f16_acc(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
%c = fcmp fast olt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -610,7 +610,7 @@ define arm_aapcs_vfpcc void @fmin_v16f16_acc(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
%c = fcmp fast olt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -623,7 +623,7 @@ define arm_aapcs_vfpcc double @fmin_v1f64_acc(<1 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vminnm.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
%c = fcmp fast olt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -636,7 +636,7 @@ define arm_aapcs_vfpcc double @fmin_v2f64_acc(<2 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vminnm.f64 d0, d2, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
%c = fcmp fast olt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -655,7 +655,7 @@ define arm_aapcs_vfpcc double @fmin_v4f64_acc(<4 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vminnm.f64 d0, d4, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
%c = fcmp fast olt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -670,7 +670,7 @@ define arm_aapcs_vfpcc float @fmin_v2f32_acc_nofast(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vselgt.f32 s0, s4, s0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
|
||||
%c = fcmp olt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -697,7 +697,7 @@ define arm_aapcs_vfpcc float @fmin_v4f32_acc_nofast(<4 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
|
||||
%c = fcmp olt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -729,7 +729,7 @@ define arm_aapcs_vfpcc float @fmin_v8f32_acc_nofast(<8 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
|
||||
%c = fcmp olt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -765,7 +765,7 @@ define arm_aapcs_vfpcc void @fmin_v4f16_acc_nofast(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
|
||||
%c = fcmp olt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -808,7 +808,7 @@ define arm_aapcs_vfpcc void @fmin_v8f16_acc_nofast(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
|
||||
%c = fcmp olt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -864,7 +864,7 @@ define arm_aapcs_vfpcc void @fmin_v16f16_acc_nofast(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
|
||||
%c = fcmp olt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -879,7 +879,7 @@ define arm_aapcs_vfpcc double @fmin_v1f64_acc_nofast(<1 x double> %x, double %y)
|
||||
; CHECK-NEXT: vselgt.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %x)
|
||||
%c = fcmp olt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -894,7 +894,7 @@ define arm_aapcs_vfpcc double @fmin_v2f64_acc_nofast(<2 x double> %x, double %y)
|
||||
; CHECK-NEXT: vselgt.f64 d0, d2, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)
|
||||
%c = fcmp olt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -911,7 +911,7 @@ define arm_aapcs_vfpcc double @fmin_v4f64_acc_nofast(<4 x double> %x, double %y)
|
||||
; CHECK-NEXT: vselgt.f64 d0, d4, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
|
||||
%c = fcmp olt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -923,7 +923,7 @@ define arm_aapcs_vfpcc float @fmax_v2f32(<2 x float> %x) {
|
||||
; CHECK-NEXT: vmaxnm.f32 s0, s0, s1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -942,7 +942,7 @@ define arm_aapcs_vfpcc float @fmax_v4f32(<4 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s3
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -974,7 +974,7 @@ define arm_aapcs_vfpcc float @fmax_v8f32(<8 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s2, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -997,7 +997,7 @@ define arm_aapcs_vfpcc half @fmax_v4f16(<4 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -1026,7 +1026,7 @@ define arm_aapcs_vfpcc half @fmax_v8f16(<8 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -1084,7 +1084,7 @@ define arm_aapcs_vfpcc half @fmax_v16f16(<16 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -1093,7 +1093,7 @@ define arm_aapcs_vfpcc double @fmax_v1f64(<1 x double> %x) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -1103,7 +1103,7 @@ define arm_aapcs_vfpcc double @fmax_v2f64(<2 x double> %x) {
|
||||
; CHECK-NEXT: vmaxnm.f64 d0, d0, d1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -1119,7 +1119,7 @@ define arm_aapcs_vfpcc double @fmax_v4f64(<4 x double> %x) {
|
||||
; CHECK-NEXT: vmaxnm.f64 d0, d0, d4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -1129,7 +1129,7 @@ define arm_aapcs_vfpcc float @fmax_v2f32_nofast(<2 x float> %x) {
|
||||
; CHECK-NEXT: vmaxnm.f32 s0, s0, s1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -1148,7 +1148,7 @@ define arm_aapcs_vfpcc float @fmax_v4f32_nofast(<4 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s3
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -1172,7 +1172,7 @@ define arm_aapcs_vfpcc float @fmax_v8f32_nofast(<8 x float> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -1195,7 +1195,7 @@ define arm_aapcs_vfpcc half @fmax_v4f16_nofast(<4 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -1224,7 +1224,7 @@ define arm_aapcs_vfpcc half @fmax_v8f16_nofast(<8 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call half @llvm.experimental.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -1266,7 +1266,7 @@ define arm_aapcs_vfpcc half @fmax_v16f16_nofast(<16 x half> %x) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call half @llvm.experimental.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
ret half %z
|
||||
}
|
||||
|
||||
@@ -1275,7 +1275,7 @@ define arm_aapcs_vfpcc double @fmax_v1f64_nofast(<1 x double> %x) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -1285,7 +1285,7 @@ define arm_aapcs_vfpcc double @fmax_v2f64_nofast(<2 x double> %x) {
|
||||
; CHECK-NEXT: vmaxnm.f64 d0, d0, d1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -1297,7 +1297,7 @@ define arm_aapcs_vfpcc double @fmax_v4f64_nofast(<4 x double> %x) {
|
||||
; CHECK-NEXT: vmaxnm.f64 d0, d0, d4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -1308,7 +1308,7 @@ define arm_aapcs_vfpcc float @fmax_v2f32_acc(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vmaxnm.f32 s0, s4, s0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
%c = fcmp fast ogt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -1331,7 +1331,7 @@ define arm_aapcs_vfpcc float @fmax_v4f32_acc(<4 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
%c = fcmp fast ogt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -1367,7 +1367,7 @@ define arm_aapcs_vfpcc float @fmax_v8f32_acc(<8 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
%c = fcmp fast ogt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -1384,7 +1384,7 @@ define arm_aapcs_vfpcc void @fmax_v2f16_acc(<2 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmax.v2f16(<2 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmax.v2f16(<2 x half> %x)
|
||||
%c = fcmp fast ogt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -1417,7 +1417,7 @@ define arm_aapcs_vfpcc void @fmax_v4f16_acc(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
%c = fcmp fast ogt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -1456,7 +1456,7 @@ define arm_aapcs_vfpcc void @fmax_v8f16_acc(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
%c = fcmp fast ogt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -1524,7 +1524,7 @@ define arm_aapcs_vfpcc void @fmax_v16f16_acc(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
%c = fcmp fast ogt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -1537,7 +1537,7 @@ define arm_aapcs_vfpcc double @fmax_v1f64_acc(<1 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmaxnm.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
%c = fcmp fast ogt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -1550,7 +1550,7 @@ define arm_aapcs_vfpcc double @fmax_v2f64_acc(<2 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmaxnm.f64 d0, d2, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
%c = fcmp fast ogt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -1569,7 +1569,7 @@ define arm_aapcs_vfpcc double @fmax_v4f64_acc(<4 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmaxnm.f64 d0, d4, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
%c = fcmp fast ogt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -1584,7 +1584,7 @@ define arm_aapcs_vfpcc float @fmax_v2f32_acc_nofast(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vselgt.f32 s0, s4, s0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
|
||||
%c = fcmp ogt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -1611,7 +1611,7 @@ define arm_aapcs_vfpcc float @fmax_v4f32_acc_nofast(<4 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
|
||||
%c = fcmp ogt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -1643,7 +1643,7 @@ define arm_aapcs_vfpcc float @fmax_v8f32_acc_nofast(<8 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
|
||||
%c = fcmp ogt float %y, %z
|
||||
%r = select i1 %c, float %y, float %z
|
||||
ret float %r
|
||||
@@ -1679,7 +1679,7 @@ define arm_aapcs_vfpcc void @fmax_v4f16_acc_nofast(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
|
||||
%c = fcmp ogt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -1722,7 +1722,7 @@ define arm_aapcs_vfpcc void @fmax_v8f16_acc_nofast(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
|
||||
%c = fcmp ogt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -1778,7 +1778,7 @@ define arm_aapcs_vfpcc void @fmax_v16f16_acc_nofast(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
|
||||
%c = fcmp ogt half %y, %z
|
||||
%r = select i1 %c, half %y, half %z
|
||||
store half %r, half* %yy
|
||||
@@ -1793,7 +1793,7 @@ define arm_aapcs_vfpcc double @fmax_v1f64_acc_nofast(<1 x double> %x, double %y)
|
||||
; CHECK-NEXT: vselgt.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %x)
|
||||
%c = fcmp ogt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -1808,7 +1808,7 @@ define arm_aapcs_vfpcc double @fmax_v2f64_acc_nofast(<2 x double> %x, double %y)
|
||||
; CHECK-NEXT: vselgt.f64 d0, d2, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)
|
||||
%c = fcmp ogt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
@@ -1825,29 +1825,29 @@ define arm_aapcs_vfpcc double @fmax_v4f64_acc_nofast(<4 x double> %x, double %y)
|
||||
; CHECK-NEXT: vselgt.f64 d0, d4, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
|
||||
%c = fcmp ogt double %y, %z
|
||||
%r = select i1 %c, double %y, double %z
|
||||
ret double %r
|
||||
}
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v1f64(<1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v1f64(<1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.fmin.v4f64(<4 x double>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v16f16(<16 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v2f16(<2 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmax.v8f16(<8 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v16f16(<16 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v2f16(<2 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.fmin.v8f16(<8 x half>)
|
||||
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v1f64(<1 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
|
||||
declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)
|
||||
declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)
|
||||
declare half @llvm.vector.reduce.fmax.v16f16(<16 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)
|
||||
declare half @llvm.vector.reduce.fmax.v8f16(<8 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v16f16(<16 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
|
||||
declare half @llvm.vector.reduce.fmin.v8f16(<8 x half>)
|
||||
|
||||
@@ -9,7 +9,7 @@ define arm_aapcs_vfpcc float @fmul_v2f32(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vmul.f32 s0, s4, s0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v2f32(float %y, <2 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -30,7 +30,7 @@ define arm_aapcs_vfpcc float @fmul_v4f32(<4 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vmul.f32 s0, s4, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %y, <4 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -56,7 +56,7 @@ define arm_aapcs_vfpcc float @fmul_v8f32(<8 x float> %x, float %y) {
|
||||
; CHECK-NOFP-NEXT: vmul.f32 s0, s8, s0
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v8f32(float %y, <8 x float> %x)
|
||||
%z = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -71,7 +71,7 @@ define arm_aapcs_vfpcc void @fmul_v2f16(<2 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fmul.f16.v2f16(half %y, <2 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -102,7 +102,7 @@ define arm_aapcs_vfpcc void @fmul_v4f16(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fmul.f16.v4f16(half %y, <4 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -139,7 +139,7 @@ define arm_aapcs_vfpcc void @fmul_v8f16(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fmul.f16.v8f16(half %y, <8 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -189,7 +189,7 @@ define arm_aapcs_vfpcc void @fmul_v16f16(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NOFP-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call fast half @llvm.experimental.vector.reduce.v2.fmul.f16.v16f16(half %y, <16 x half> %x)
|
||||
%z = call fast half @llvm.vector.reduce.fmul.f16.v16f16(half %y, <16 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -200,7 +200,7 @@ define arm_aapcs_vfpcc double @fmul_v1f64(<1 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmul.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double %y, <1 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmul.f64.v1f64(double %y, <1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -211,7 +211,7 @@ define arm_aapcs_vfpcc double @fmul_v2f64(<2 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmul.f64 d0, d2, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.v2.fmul.f64.v2f64(double %y, <2 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -224,7 +224,7 @@ define arm_aapcs_vfpcc double @fmul_v4f64(<4 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmul.f64 d0, d4, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call fast double @llvm.experimental.vector.reduce.v2.fmul.f64.v4f64(double %y, <4 x double> %x)
|
||||
%z = call fast double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -235,7 +235,7 @@ define arm_aapcs_vfpcc float @fmul_v2f32_nofast(<2 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vmul.f32 s0, s4, s1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v2f32(float %y, <2 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -248,7 +248,7 @@ define arm_aapcs_vfpcc float @fmul_v4f32_nofast(<4 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vmul.f32 s0, s4, s3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %y, <4 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -265,7 +265,7 @@ define arm_aapcs_vfpcc float @fmul_v8f32_nofast(<8 x float> %x, float %y) {
|
||||
; CHECK-NEXT: vmul.f32 s0, s0, s7
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v8f32(float %y, <8 x float> %x)
|
||||
%z = call float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x)
|
||||
ret float %z
|
||||
}
|
||||
|
||||
@@ -280,7 +280,7 @@ define arm_aapcs_vfpcc void @fmul_v2f16_nofast(<2 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v2f16(half %y, <2 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -299,7 +299,7 @@ define arm_aapcs_vfpcc void @fmul_v4f16_nofast(<4 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v4f16(half %y, <4 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -324,7 +324,7 @@ define arm_aapcs_vfpcc void @fmul_v8f16_nofast(<8 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v8f16(half %y, <8 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -361,7 +361,7 @@ define arm_aapcs_vfpcc void @fmul_v16f16_nofast(<16 x half> %x, half* %yy) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%y = load half, half* %yy
|
||||
%z = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v16f16(half %y, <16 x half> %x)
|
||||
%z = call half @llvm.vector.reduce.fmul.f16.v16f16(half %y, <16 x half> %x)
|
||||
store half %z, half* %yy
|
||||
ret void
|
||||
}
|
||||
@@ -372,7 +372,7 @@ define arm_aapcs_vfpcc double @fmul_v1f64_nofast(<1 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmul.f64 d0, d1, d0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double %y, <1 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmul.f64.v1f64(double %y, <1 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -383,7 +383,7 @@ define arm_aapcs_vfpcc double @fmul_v2f64_nofast(<2 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmul.f64 d0, d2, d1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.v2.fmul.f64.v2f64(double %y, <2 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
@@ -396,17 +396,17 @@ define arm_aapcs_vfpcc double @fmul_v4f64_nofast(<4 x double> %x, double %y) {
|
||||
; CHECK-NEXT: vmul.f64 d0, d0, d3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = call double @llvm.experimental.vector.reduce.v2.fmul.f64.v4f64(double %y, <4 x double> %x)
|
||||
%z = call double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x)
|
||||
ret double %z
|
||||
}
|
||||
|
||||
declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double, <1 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v2f64(double, <2 x double>)
|
||||
declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v4f64(double, <4 x double>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v2f32(float, <2 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v8f32(float, <8 x float>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v16f16(half, <16 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v2f16(half, <2 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v4f16(half, <4 x half>)
|
||||
declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v8f16(half, <8 x half>)
|
||||
declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>)
|
||||
declare double @llvm.vector.reduce.fmul.f64.v2f64(double, <2 x double>)
|
||||
declare double @llvm.vector.reduce.fmul.f64.v4f64(double, <4 x double>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v2f32(float, <2 x float>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v8f32(float, <8 x float>)
|
||||
declare half @llvm.vector.reduce.fmul.f16.v16f16(half, <16 x half>)
|
||||
declare half @llvm.vector.reduce.fmul.f16.v2f16(half, <2 x half>)
|
||||
declare half @llvm.vector.reduce.fmul.f16.v4f16(half, <4 x half>)
|
||||
declare half @llvm.vector.reduce.fmul.f16.v8f16(half, <8 x half>)
|
||||
|
||||
@@ -65,7 +65,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%0 = getelementptr inbounds i32, i32* %x, i32 %index
|
||||
%1 = bitcast i32* %0 to <4 x i32>*
|
||||
%wide.load = load <4 x i32>, <4 x i32>* %1, align 4
|
||||
%2 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %wide.load)
|
||||
%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %wide.load)
|
||||
%3 = add i32 %2, %vec.phi
|
||||
%index.next = add i32 %index, 4
|
||||
%4 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -167,7 +167,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %3, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%4 = call i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> %2)
|
||||
%4 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %2)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -267,7 +267,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %3, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%4 = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %2)
|
||||
%4 = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %2)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -367,7 +367,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %3, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%4 = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %2)
|
||||
%4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %2)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -467,7 +467,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %3, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%4 = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %2)
|
||||
%4 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %2)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -568,7 +568,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %3, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%4 = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %2)
|
||||
%4 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %2)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -665,7 +665,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %3, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%4 = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float 1.000000e+00, <4 x float> %2)
|
||||
%4 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.000000e+00, <4 x float> %2)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -762,7 +762,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %4, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %3)
|
||||
%5 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %3)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -852,7 +852,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%0 = getelementptr inbounds i32, i32* %x, i32 %index
|
||||
%1 = bitcast i32* %0 to <4 x i32>*
|
||||
%wide.load = load <4 x i32>, <4 x i32>* %1, align 4
|
||||
%l5 = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %wide.load)
|
||||
%l5 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %wide.load)
|
||||
%2 = icmp slt i32 %vec.phi, %l5
|
||||
%3 = select i1 %2, i32 %vec.phi, i32 %l5
|
||||
%index.next = add i32 %index, 4
|
||||
@@ -958,7 +958,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %4, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %3)
|
||||
%5 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %3)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -1048,7 +1048,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%0 = getelementptr inbounds i32, i32* %x, i32 %index
|
||||
%1 = bitcast i32* %0 to <4 x i32>*
|
||||
%wide.load = load <4 x i32>, <4 x i32>* %1, align 4
|
||||
%l5 = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %wide.load)
|
||||
%l5 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %wide.load)
|
||||
%2 = icmp sgt i32 %vec.phi, %l5
|
||||
%3 = select i1 %2, i32 %vec.phi, i32 %l5
|
||||
%index.next = add i32 %index, 4
|
||||
@@ -1154,7 +1154,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %4, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %3)
|
||||
%5 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %3)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -1244,7 +1244,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%0 = getelementptr inbounds i32, i32* %x, i32 %index
|
||||
%1 = bitcast i32* %0 to <4 x i32>*
|
||||
%wide.load = load <4 x i32>, <4 x i32>* %1, align 4
|
||||
%l5 = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %wide.load)
|
||||
%l5 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %wide.load)
|
||||
%2 = icmp ult i32 %vec.phi, %l5
|
||||
%3 = select i1 %2, i32 %vec.phi, i32 %l5
|
||||
%index.next = add i32 %index, 4
|
||||
@@ -1350,7 +1350,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %4, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %3)
|
||||
%5 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %3)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -1440,7 +1440,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%0 = getelementptr inbounds i32, i32* %x, i32 %index
|
||||
%1 = bitcast i32* %0 to <4 x i32>*
|
||||
%wide.load = load <4 x i32>, <4 x i32>* %1, align 4
|
||||
%l5 = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %wide.load)
|
||||
%l5 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %wide.load)
|
||||
%2 = icmp ugt i32 %vec.phi, %l5
|
||||
%3 = select i1 %2, i32 %vec.phi, i32 %l5
|
||||
%index.next = add i32 %index, 4
|
||||
@@ -1553,7 +1553,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %4, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %3)
|
||||
%5 = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %3)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -1658,7 +1658,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
br i1 %4, label %middle.block, label %vector.body
|
||||
|
||||
middle.block: ; preds = %vector.body
|
||||
%5 = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %3)
|
||||
%5 = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %3)
|
||||
%cmp.n = icmp eq i32 %n.vec, %n
|
||||
br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader1
|
||||
|
||||
@@ -1722,7 +1722,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%1 = bitcast i32* %0 to <4 x i32>*
|
||||
%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
|
||||
%2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
|
||||
%3 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %2)
|
||||
%3 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %2)
|
||||
%4 = add i32 %3, %vec.phi
|
||||
%index.next = add i32 %index, 4
|
||||
%5 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -1777,7 +1777,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load13 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %3, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
|
||||
%4 = mul nsw <4 x i32> %wide.masked.load13, %wide.masked.load
|
||||
%5 = select <4 x i1> %active.lane.mask, <4 x i32> %4, <4 x i32> zeroinitializer
|
||||
%6 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %5)
|
||||
%6 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %5)
|
||||
%7 = add i32 %6, %vec.phi
|
||||
%index.next = add i32 %index, 4
|
||||
%8 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -1828,7 +1828,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
|
||||
%2 = sext <8 x i16> %wide.masked.load to <8 x i32>
|
||||
%3 = select <8 x i1> %active.lane.mask, <8 x i32> %2, <8 x i32> zeroinitializer
|
||||
%4 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %3)
|
||||
%4 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %3)
|
||||
%5 = add i32 %4, %vec.phi
|
||||
%index.next = add i32 %index, 8
|
||||
%6 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -1885,7 +1885,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%5 = sext <8 x i16> %wide.masked.load14 to <8 x i32>
|
||||
%6 = mul nsw <8 x i32> %5, %2
|
||||
%7 = select <8 x i1> %active.lane.mask, <8 x i32> %6, <8 x i32> zeroinitializer
|
||||
%8 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %7)
|
||||
%8 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %7)
|
||||
%9 = add i32 %8, %vec.phi
|
||||
%index.next = add i32 %index, 8
|
||||
%10 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -1936,7 +1936,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %1, i32 1, <16 x i1> %active.lane.mask, <16 x i8> undef)
|
||||
%2 = zext <16 x i8> %wide.masked.load to <16 x i32>
|
||||
%3 = select <16 x i1> %active.lane.mask, <16 x i32> %2, <16 x i32> zeroinitializer
|
||||
%4 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %3)
|
||||
%4 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %3)
|
||||
%5 = add i32 %4, %vec.phi
|
||||
%index.next = add i32 %index, 16
|
||||
%6 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -1993,7 +1993,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%5 = zext <16 x i8> %wide.masked.load14 to <16 x i32>
|
||||
%6 = mul nuw nsw <16 x i32> %5, %2
|
||||
%7 = select <16 x i1> %active.lane.mask, <16 x i32> %6, <16 x i32> zeroinitializer
|
||||
%8 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %7)
|
||||
%8 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %7)
|
||||
%9 = add i32 %8, %vec.phi
|
||||
%index.next = add i32 %index, 16
|
||||
%10 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2043,7 +2043,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%1 = bitcast i16* %0 to <8 x i16>*
|
||||
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
|
||||
%2 = select <8 x i1> %active.lane.mask, <8 x i16> %wide.masked.load, <8 x i16> zeroinitializer
|
||||
%3 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %2)
|
||||
%3 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %2)
|
||||
%4 = add i16 %3, %vec.phi
|
||||
%index.next = add i32 %index, 8
|
||||
%5 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2098,7 +2098,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load16 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
|
||||
%4 = mul <8 x i16> %wide.masked.load16, %wide.masked.load
|
||||
%5 = select <8 x i1> %active.lane.mask, <8 x i16> %4, <8 x i16> zeroinitializer
|
||||
%6 = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %5)
|
||||
%6 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %5)
|
||||
%7 = add i16 %6, %vec.phi
|
||||
%index.next = add i32 %index, 8
|
||||
%8 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2149,7 +2149,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %1, i32 1, <16 x i1> %active.lane.mask, <16 x i8> undef)
|
||||
%2 = zext <16 x i8> %wide.masked.load to <16 x i16>
|
||||
%3 = select <16 x i1> %active.lane.mask, <16 x i16> %2, <16 x i16> zeroinitializer
|
||||
%4 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %3)
|
||||
%4 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %3)
|
||||
%5 = add i16 %4, %vec.phi
|
||||
%index.next = add i32 %index, 16
|
||||
%6 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2206,7 +2206,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%5 = zext <16 x i8> %wide.masked.load18 to <16 x i16>
|
||||
%6 = mul nuw <16 x i16> %5, %2
|
||||
%7 = select <16 x i1> %active.lane.mask, <16 x i16> %6, <16 x i16> zeroinitializer
|
||||
%8 = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %7)
|
||||
%8 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %7)
|
||||
%9 = add i16 %8, %vec.phi
|
||||
%index.next = add i32 %index, 16
|
||||
%10 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2256,7 +2256,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%1 = bitcast i8* %0 to <16 x i8>*
|
||||
%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %1, i32 1, <16 x i1> %active.lane.mask, <16 x i8> undef)
|
||||
%2 = select <16 x i1> %active.lane.mask, <16 x i8> %wide.masked.load, <16 x i8> zeroinitializer
|
||||
%3 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %2)
|
||||
%3 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %2)
|
||||
%4 = add i8 %3, %vec.phi
|
||||
%index.next = add i32 %index, 16
|
||||
%5 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2311,7 +2311,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load15 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %3, i32 1, <16 x i1> %active.lane.mask, <16 x i8> undef)
|
||||
%4 = mul <16 x i8> %wide.masked.load15, %wide.masked.load
|
||||
%5 = select <16 x i1> %active.lane.mask, <16 x i8> %4, <16 x i8> zeroinitializer
|
||||
%6 = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %5)
|
||||
%6 = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %5)
|
||||
%7 = add i8 %6, %vec.phi
|
||||
%index.next = add i32 %index, 16
|
||||
%8 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2364,7 +2364,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
|
||||
%2 = sext <4 x i32> %wide.masked.load to <4 x i64>
|
||||
%3 = select <4 x i1> %active.lane.mask, <4 x i64> %2, <4 x i64> zeroinitializer
|
||||
%4 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %3)
|
||||
%4 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %3)
|
||||
%5 = add i64 %4, %vec.phi
|
||||
%index.next = add i32 %index, 4
|
||||
%6 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2423,7 +2423,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%5 = sext <4 x i32> %wide.masked.load14 to <4 x i64>
|
||||
%6 = mul nsw <4 x i64> %5, %2
|
||||
%7 = select <4 x i1> %active.lane.mask, <4 x i64> %6, <4 x i64> zeroinitializer
|
||||
%8 = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %7)
|
||||
%8 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %7)
|
||||
%9 = add i64 %8, %vec.phi
|
||||
%index.next = add i32 %index, 4
|
||||
%10 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2482,7 +2482,7 @@ vector.body: ; preds = %vector.body, %vecto
|
||||
%5 = sext <8 x i16> %wide.masked.load14 to <8 x i64>
|
||||
%6 = mul nsw <8 x i64> %5, %2
|
||||
%7 = select <8 x i1> %active.lane.mask, <8 x i64> %6, <8 x i64> zeroinitializer
|
||||
%8 = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %7)
|
||||
%8 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %7)
|
||||
%9 = add i64 %8, %vec.phi
|
||||
%index.next = add i32 %index, 8
|
||||
%10 = icmp eq i32 %index.next, %n.vec
|
||||
@@ -2497,26 +2497,26 @@ declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #1
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
|
||||
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) #1
|
||||
declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>) #2
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>) #3
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) #3
|
||||
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32) #1
|
||||
declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>) #2
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>) #3
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>) #3
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>) #3
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>) #3
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>) #3
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64>) #3
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) #3
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) #3
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>) #3
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>) #3
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>) #3
|
||||
declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>) #3
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float, <4 x float>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
|
||||
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
|
||||
declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)
|
||||
declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
|
||||
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
||||
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
||||
|
||||
@@ -8,7 +8,7 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%m = mul <4 x i32> %x, %y
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -21,7 +21,7 @@ entry:
|
||||
%xx = zext <4 x i32> %x to <4 x i64>
|
||||
%yy = zext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -34,7 +34,7 @@ entry:
|
||||
%xx = sext <4 x i32> %x to <4 x i64>
|
||||
%yy = sext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -53,7 +53,7 @@ entry:
|
||||
%xx = zext <2 x i32> %x to <2 x i64>
|
||||
%yy = zext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -72,7 +72,7 @@ entry:
|
||||
%xx = sext <2 x i32> %x to <2 x i64>
|
||||
%yy = sext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -85,7 +85,7 @@ entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i32>
|
||||
%yy = zext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -98,7 +98,7 @@ entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%yy = sext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -113,7 +113,7 @@ entry:
|
||||
%xx = zext <4 x i16> %x to <4 x i32>
|
||||
%yy = zext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -128,7 +128,7 @@ entry:
|
||||
%xx = sext <4 x i16> %x to <4 x i32>
|
||||
%yy = sext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -140,7 +140,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y)
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%m = mul <8 x i16> %x, %y
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -153,7 +153,7 @@ entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i64>
|
||||
%yy = zext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -166,7 +166,7 @@ entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i64>
|
||||
%yy = sext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -180,7 +180,7 @@ entry:
|
||||
%yy = zext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -194,7 +194,7 @@ entry:
|
||||
%yy = sext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = sext <8 x i32> %m to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -207,7 +207,7 @@ entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %xx
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -228,7 +228,7 @@ entry:
|
||||
%xx = zext <2 x i16> %x to <2 x i64>
|
||||
%yy = zext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -250,7 +250,7 @@ entry:
|
||||
%xx = sext <2 x i16> %x to <2 x i64>
|
||||
%yy = sext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -263,7 +263,7 @@ entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i32>
|
||||
%yy = zext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -276,7 +276,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i32>
|
||||
%yy = sext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -290,7 +290,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -304,7 +304,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = sext <16 x i16> %m to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -317,7 +317,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %xx
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -333,7 +333,7 @@ entry:
|
||||
%xx = zext <4 x i8> %x to <4 x i32>
|
||||
%yy = zext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -350,7 +350,7 @@ entry:
|
||||
%xx = sext <4 x i8> %x to <4 x i32>
|
||||
%yy = sext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -364,7 +364,7 @@ entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i16>
|
||||
%yy = zext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -378,7 +378,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%yy = sext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -394,7 +394,7 @@ entry:
|
||||
%xx = zext <8 x i8> %x to <8 x i16>
|
||||
%yy = zext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -410,7 +410,7 @@ entry:
|
||||
%xx = sext <8 x i8> %x to <8 x i16>
|
||||
%yy = sext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -422,7 +422,7 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) {
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%m = mul <16 x i8> %x, %y
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %m)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %m)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -636,7 +636,7 @@ entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i64>
|
||||
%yy = zext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -803,7 +803,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i64>
|
||||
%yy = sext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -826,7 +826,7 @@ entry:
|
||||
%xx = zext <2 x i8> %x to <2 x i64>
|
||||
%yy = zext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -848,7 +848,7 @@ entry:
|
||||
%xx = sext <2 x i8> %x to <2 x i64>
|
||||
%yy = sext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -879,7 +879,7 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) {
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%m = mul <2 x i64> %x, %y
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -890,7 +890,7 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %y, i32
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%m = mul <4 x i32> %x, %y
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -904,7 +904,7 @@ entry:
|
||||
%xx = zext <4 x i32> %x to <4 x i64>
|
||||
%yy = zext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -918,7 +918,7 @@ entry:
|
||||
%xx = sext <4 x i32> %x to <4 x i64>
|
||||
%yy = sext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -942,7 +942,7 @@ entry:
|
||||
%xx = zext <2 x i32> %x to <2 x i64>
|
||||
%yy = zext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -966,7 +966,7 @@ entry:
|
||||
%xx = sext <2 x i32> %x to <2 x i64>
|
||||
%yy = sext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -980,7 +980,7 @@ entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i32>
|
||||
%yy = zext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -994,7 +994,7 @@ entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%yy = sext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1010,7 +1010,7 @@ entry:
|
||||
%xx = zext <4 x i16> %x to <4 x i32>
|
||||
%yy = zext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1026,7 +1026,7 @@ entry:
|
||||
%xx = sext <4 x i16> %x to <4 x i32>
|
||||
%yy = sext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1039,7 +1039,7 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16>
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%m = mul <8 x i16> %x, %y
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1053,7 +1053,7 @@ entry:
|
||||
%xx = zext <8 x i16> %x to <8 x i64>
|
||||
%yy = zext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1067,7 +1067,7 @@ entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i64>
|
||||
%yy = sext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1082,7 +1082,7 @@ entry:
|
||||
%yy = zext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1097,7 +1097,7 @@ entry:
|
||||
%yy = sext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = sext <8 x i32> %m to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1111,7 +1111,7 @@ entry:
|
||||
%xx = sext <8 x i16> %x to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %xx
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %ma)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1137,7 +1137,7 @@ entry:
|
||||
%xx = zext <2 x i16> %x to <2 x i64>
|
||||
%yy = zext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1164,7 +1164,7 @@ entry:
|
||||
%xx = sext <2 x i16> %x to <2 x i64>
|
||||
%yy = sext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1178,7 +1178,7 @@ entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i32>
|
||||
%yy = zext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1192,7 +1192,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i32>
|
||||
%yy = sext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1207,7 +1207,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1222,7 +1222,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = sext <16 x i16> %m to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1236,7 +1236,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %xx
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %ma)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1253,7 +1253,7 @@ entry:
|
||||
%xx = zext <4 x i8> %x to <4 x i32>
|
||||
%yy = zext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1271,7 +1271,7 @@ entry:
|
||||
%xx = sext <4 x i8> %x to <4 x i32>
|
||||
%yy = sext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %m)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1286,7 +1286,7 @@ entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i16>
|
||||
%yy = zext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1301,7 +1301,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i16>
|
||||
%yy = sext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %m)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1318,7 +1318,7 @@ entry:
|
||||
%xx = zext <8 x i8> %x to <8 x i16>
|
||||
%yy = zext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1335,7 +1335,7 @@ entry:
|
||||
%xx = sext <8 x i8> %x to <8 x i16>
|
||||
%yy = sext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %m)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1348,7 +1348,7 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%m = mul <16 x i8> %x, %y
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %m)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %m)
|
||||
%r = add i8 %z, %a
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -1565,7 +1565,7 @@ entry:
|
||||
%xx = zext <16 x i8> %x to <16 x i64>
|
||||
%yy = zext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1737,7 +1737,7 @@ entry:
|
||||
%xx = sext <16 x i8> %x to <16 x i64>
|
||||
%yy = sext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1765,7 +1765,7 @@ entry:
|
||||
%xx = zext <2 x i8> %x to <2 x i64>
|
||||
%yy = zext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1792,7 +1792,7 @@ entry:
|
||||
%xx = sext <2 x i8> %x to <2 x i64>
|
||||
%yy = sext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1826,18 +1826,18 @@ define arm_aapcs_vfpcc i64 @add_v2i64_v2i64_acc(<2 x i64> %x, <2 x i64> %y, i64
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
entry:
|
||||
%m = mul <2 x i64> %x, %y
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %m)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
|
||||
@@ -11,7 +11,7 @@ entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%m = mul <4 x i32> %x, %y
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -27,7 +27,7 @@ entry:
|
||||
%yy = zext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i64> %m, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -43,7 +43,7 @@ entry:
|
||||
%yy = sext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i64> %m, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -79,7 +79,7 @@ entry:
|
||||
%yy = zext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -115,7 +115,7 @@ entry:
|
||||
%yy = sext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -131,7 +131,7 @@ entry:
|
||||
%yy = zext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -147,7 +147,7 @@ entry:
|
||||
%yy = sext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -166,7 +166,7 @@ entry:
|
||||
%yy = zext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -185,7 +185,7 @@ entry:
|
||||
%yy = sext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -200,7 +200,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%m = mul <8 x i16> %x, %y
|
||||
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -216,7 +216,7 @@ entry:
|
||||
%yy = zext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i64> %m, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -232,7 +232,7 @@ entry:
|
||||
%yy = sext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i64> %m, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -249,7 +249,7 @@ entry:
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -266,7 +266,7 @@ entry:
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = sext <8 x i32> %m to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -282,7 +282,7 @@ entry:
|
||||
%m = mul <8 x i32> %xx, %xx
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -334,7 +334,7 @@ entry:
|
||||
%yy = zext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -385,7 +385,7 @@ entry:
|
||||
%yy = sext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -401,7 +401,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -417,7 +417,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -434,7 +434,7 @@ entry:
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -451,7 +451,7 @@ entry:
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = sext <16 x i16> %m to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -467,7 +467,7 @@ entry:
|
||||
%m = mul <16 x i16> %xx, %xx
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -487,7 +487,7 @@ entry:
|
||||
%yy = zext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -509,7 +509,7 @@ entry:
|
||||
%yy = sext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
ret i32 %z
|
||||
}
|
||||
|
||||
@@ -526,7 +526,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -543,7 +543,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -563,7 +563,7 @@ entry:
|
||||
%yy = zext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -583,7 +583,7 @@ entry:
|
||||
%yy = sext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
ret i16 %z
|
||||
}
|
||||
|
||||
@@ -598,7 +598,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%m = mul <16 x i8> %x, %y
|
||||
%s = select <16 x i1> %c, <16 x i8> %m, <16 x i8> zeroinitializer
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
ret i8 %z
|
||||
}
|
||||
|
||||
@@ -1010,7 +1010,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i64> %m, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1353,7 +1353,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i64> %m, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1405,7 +1405,7 @@ entry:
|
||||
%yy = zext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1456,7 +1456,7 @@ entry:
|
||||
%yy = sext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1509,7 +1509,7 @@ entry:
|
||||
%c = icmp eq <2 x i64> %b, zeroinitializer
|
||||
%m = mul <2 x i64> %x, %y
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
ret i64 %z
|
||||
}
|
||||
|
||||
@@ -1523,7 +1523,7 @@ entry:
|
||||
%c = icmp eq <4 x i32> %b, zeroinitializer
|
||||
%m = mul <4 x i32> %x, %y
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1540,7 +1540,7 @@ entry:
|
||||
%yy = zext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i64> %m, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1557,7 +1557,7 @@ entry:
|
||||
%yy = sext <4 x i32> %y to <4 x i64>
|
||||
%m = mul <4 x i64> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i64> %m, <4 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1598,7 +1598,7 @@ entry:
|
||||
%yy = zext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1639,7 +1639,7 @@ entry:
|
||||
%yy = sext <2 x i32> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1656,7 +1656,7 @@ entry:
|
||||
%yy = zext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1673,7 +1673,7 @@ entry:
|
||||
%yy = sext <8 x i16> %y to <8 x i32>
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1693,7 +1693,7 @@ entry:
|
||||
%yy = zext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1713,7 +1713,7 @@ entry:
|
||||
%yy = sext <4 x i16> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1729,7 +1729,7 @@ entry:
|
||||
%c = icmp eq <8 x i16> %b, zeroinitializer
|
||||
%m = mul <8 x i16> %x, %y
|
||||
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -1746,7 +1746,7 @@ entry:
|
||||
%yy = zext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i64> %m, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1763,7 +1763,7 @@ entry:
|
||||
%yy = sext <8 x i16> %y to <8 x i64>
|
||||
%m = mul <8 x i64> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i64> %m, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1781,7 +1781,7 @@ entry:
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1799,7 +1799,7 @@ entry:
|
||||
%m = mul <8 x i32> %xx, %yy
|
||||
%ma = sext <8 x i32> %m to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1816,7 +1816,7 @@ entry:
|
||||
%m = mul <8 x i32> %xx, %xx
|
||||
%ma = zext <8 x i32> %m to <8 x i64>
|
||||
%s = select <8 x i1> %c, <8 x i64> %ma, <8 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1873,7 +1873,7 @@ entry:
|
||||
%yy = zext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1929,7 +1929,7 @@ entry:
|
||||
%yy = sext <2 x i16> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -1946,7 +1946,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1963,7 +1963,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i32>
|
||||
%m = mul <16 x i32> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1981,7 +1981,7 @@ entry:
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -1999,7 +1999,7 @@ entry:
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%ma = sext <16 x i16> %m to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -2016,7 +2016,7 @@ entry:
|
||||
%m = mul <16 x i16> %xx, %xx
|
||||
%ma = zext <16 x i16> %m to <16 x i32>
|
||||
%s = select <16 x i1> %c, <16 x i32> %ma, <16 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -2037,7 +2037,7 @@ entry:
|
||||
%yy = zext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -2060,7 +2060,7 @@ entry:
|
||||
%yy = sext <4 x i8> %y to <4 x i32>
|
||||
%m = mul <4 x i32> %xx, %yy
|
||||
%s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer
|
||||
%z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %s)
|
||||
%r = add i32 %z, %a
|
||||
ret i32 %r
|
||||
}
|
||||
@@ -2078,7 +2078,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2096,7 +2096,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i16>
|
||||
%m = mul <16 x i16> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2117,7 +2117,7 @@ entry:
|
||||
%yy = zext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2138,7 +2138,7 @@ entry:
|
||||
%yy = sext <8 x i8> %y to <8 x i16>
|
||||
%m = mul <8 x i16> %xx, %yy
|
||||
%s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer
|
||||
%z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %s)
|
||||
%r = add i16 %z, %a
|
||||
ret i16 %r
|
||||
}
|
||||
@@ -2154,7 +2154,7 @@ entry:
|
||||
%c = icmp eq <16 x i8> %b, zeroinitializer
|
||||
%m = mul <16 x i8> %x, %y
|
||||
%s = select <16 x i1> %c, <16 x i8> %m, <16 x i8> zeroinitializer
|
||||
%z = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
%z = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %s)
|
||||
%r = add i8 %z, %a
|
||||
ret i8 %r
|
||||
}
|
||||
@@ -2569,7 +2569,7 @@ entry:
|
||||
%yy = zext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i64> %m, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -2917,7 +2917,7 @@ entry:
|
||||
%yy = sext <16 x i8> %y to <16 x i64>
|
||||
%m = mul <16 x i64> %xx, %yy
|
||||
%s = select <16 x i1> %c, <16 x i64> %m, <16 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -2974,7 +2974,7 @@ entry:
|
||||
%yy = zext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -3030,7 +3030,7 @@ entry:
|
||||
%yy = sext <2 x i8> %y to <2 x i64>
|
||||
%m = mul <2 x i64> %xx, %yy
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
@@ -3088,18 +3088,18 @@ entry:
|
||||
%c = icmp eq <2 x i64> %b, zeroinitializer
|
||||
%m = mul <2 x i64> %x, %y
|
||||
%s = select <2 x i1> %c, <2 x i64> %m, <2 x i64> zeroinitializer
|
||||
%z = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %s)
|
||||
%r = add i64 %z, %a
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>)
|
||||
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
|
||||
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>)
|
||||
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
|
||||
declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
|
||||
declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
|
||||
declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>)
|
||||
|
||||
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Reference in New Issue
Block a user