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AMDGPU/GFX12: Fix s_barrier_signal_isfirst for single-wave workgroups (#143634)

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Barrier instructions are no-ops in single-wave workgroups. This includes
s_barrier_signal_isfirst, which will leave SCC unmodified.

Model this correctly (via an implicit use of SCC) and ensure SCC==1
before the barrier instruction (if the wave is the only one of the
workgroup, then it is the first).

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
This commit is contained in:
Nicolai Hähnle
2025-06-19 11:22:49 -07:00
committed by GitHub
parent 74ec1c287a
commit 3bee9ba015
6 changed files with 66 additions and 3 deletions
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4
llvm/docs/AMDGPUUsage.rst
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@@ -1402,6 +1402,10 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
performs subtraction only if the memory value is greater than or
equal to the data value.
llvm.amdgcn.s.barrier.signal.isfirst Provides access to the s_barrier_signal_first instruction;
additionally ensures that the result value is valid even when the
intrinsic is used from a wave that is not running in a workgroup.
llvm.amdgcn.s.getpc Provides access to the s_getpc_b64 instruction, but with the return value
sign-extended from the width of the underlying PC hardware register even on
processors where the s_getpc_b64 instruction returns a zero-extended value.