[InstCombine] fold (trunc (X>>C1)) << C to shift+mask directly
This is no-externally-visible-functional-difference-intended. That is, the test diffs show identical instructions other than name changes (those are included specifically to verify the logic). The existing transforms created extra instructions and relied on subsequent folds to get to the final result, but that could conflict with other transforms like the proposed D110170 (and caused that patch to be reverted twice so far because of infinite combine loops).
This commit is contained in:
Sanjay Patel
@@ -845,6 +845,26 @@ Instruction *InstCombinerImpl::visitShl(BinaryOperator &I) {
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}
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}
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// Similar to above, but look through an intermediate trunc instruction.
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BinaryOperator *Shr;
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if (match(Op0, m_OneUse(m_Trunc(m_OneUse(m_BinOp(Shr))))) &&
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match(Shr, m_Shr(m_Value(X), m_APInt(C1)))) {
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// The larger shift direction survives through the transform.
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unsigned ShrAmtC = C1->getZExtValue();
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unsigned ShDiff = ShrAmtC > ShAmtC ? ShrAmtC - ShAmtC : ShAmtC - ShrAmtC;
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Constant *ShiftDiffC = ConstantInt::get(X->getType(), ShDiff);
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auto ShiftOpc = ShrAmtC > ShAmtC ? Shr->getOpcode() : Instruction::Shl;
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// If C1 > C:
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// (trunc (X >> C1)) << C --> (trunc (X >> (C1 - C))) && (-1 << C)
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// If C > C1:
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// (trunc (X >> C1)) << C --> (trunc (X << (C - C1))) && (-1 << C)
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Value *NewShift = Builder.CreateBinOp(ShiftOpc, X, ShiftDiffC, "sh.diff");
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Value *Trunc = Builder.CreateTrunc(NewShift, Ty, "tr.sh.diff");
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APInt Mask(APInt::getHighBitsSet(BitWidth, BitWidth - ShAmtC));
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return BinaryOperator::CreateAnd(Trunc, ConstantInt::get(Ty, Mask));
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}
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if (match(Op0, m_Shl(m_Value(X), m_APInt(C1))) && C1->ult(BitWidth)) {
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unsigned AmtSum = ShAmtC + C1->getZExtValue();
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// Oversized shifts are simplified to zero in InstSimplify.
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@@ -853,41 +873,6 @@ Instruction *InstCombinerImpl::visitShl(BinaryOperator &I) {
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return BinaryOperator::CreateShl(X, ConstantInt::get(Ty, AmtSum));
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}
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// Fold shl(trunc(shr(x,c1)),c2) -> trunc(and(shl(shr(x,c1),c2),c2'))
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// Require that the input operand is a non-poison shift-by-constant so that
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// we have confidence that the shifts will get folded together.
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Instruction *TrOp;
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const APInt *TrShiftAmt;
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if (match(Op0, m_OneUse(m_Trunc(m_Instruction(TrOp)))) &&
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match(TrOp, m_OneUse(m_Shr(m_Value(), m_APInt(TrShiftAmt)))) &&
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TrShiftAmt->ult(TrOp->getType()->getScalarSizeInBits())) {
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Type *SrcTy = TrOp->getType();
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// Okay, we'll do this xform. Make the shift of shift.
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unsigned SrcSize = SrcTy->getScalarSizeInBits();
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Constant *ShAmt = ConstantInt::get(SrcTy, C->zext(SrcSize));
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// (shift2 (shift1 & 0x00FF), c2)
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Value *NSh = Builder.CreateBinOp(I.getOpcode(), TrOp, ShAmt, I.getName());
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// For logical shifts, the truncation has the effect of making the high
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// part of the register be zeros. Emulate this by inserting an AND to
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// clear the top bits as needed. This 'and' will usually be zapped by
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// other xforms later if dead.
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Constant *MaskV =
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ConstantInt::get(SrcTy, APInt::getLowBitsSet(SrcSize, BitWidth));
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// The mask we constructed says what the trunc would do if occurring
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// between the shifts. We want to know the effect *after* the second
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// shift. We know that it is a logical shift by a constant, so adjust the
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// mask as appropriate.
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MaskV = ConstantExpr::get(I.getOpcode(), MaskV, ShAmt);
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// shift1 & 0x00FF
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Value *And = Builder.CreateAnd(NSh, MaskV, Op0->getName());
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// Return the value truncated to the interesting size.
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return new TruncInst(And, Ty);
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}
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// If we have an opposite shift by the same amount, we may be able to
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// reorder binops and shifts to eliminate math/logic.
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auto isSuitableBinOpcode = [](Instruction::BinaryOps BinOpcode) {
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@@ -743,9 +743,9 @@ define i16 @trunc_bswap_i160(i160* %a0) {
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; CHECK-NEXT: [[LSHR1:%.*]] = lshr i160 [[LOAD]], 136
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; CHECK-NEXT: [[CAST1:%.*]] = trunc i160 [[LSHR1]] to i16
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; CHECK-NEXT: [[AND1:%.*]] = and i16 [[CAST1]], 255
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i160 [[LOAD]], 120
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i160 [[TMP1]] to i16
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; CHECK-NEXT: [[SHL:%.*]] = and i16 [[TMP2]], -256
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; CHECK-NEXT: [[SH_DIFF:%.*]] = lshr i160 [[LOAD]], 120
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; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc i160 [[SH_DIFF]] to i16
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; CHECK-NEXT: [[SHL:%.*]] = and i16 [[TR_SH_DIFF]], -256
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; CHECK-NEXT: [[OR:%.*]] = or i16 [[AND1]], [[SHL]]
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; CHECK-NEXT: ret i16 [[OR]]
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;
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@@ -139,9 +139,9 @@ define <2 x i32> @lshr_lshr_vec(<2 x i32> %A) {
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define i8 @shl_trunc_bigger_lshr(i32 %x) {
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; CHECK-LABEL: @shl_trunc_bigger_lshr(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
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; CHECK-NEXT: [[LT:%.*]] = and i8 [[TMP2]], -8
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; CHECK-NEXT: [[SH_DIFF:%.*]] = lshr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc i32 [[SH_DIFF]] to i8
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; CHECK-NEXT: [[LT:%.*]] = and i8 [[TR_SH_DIFF]], -8
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; CHECK-NEXT: ret i8 [[LT]]
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;
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%rt = lshr i32 %x, 5
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@@ -153,8 +153,8 @@ define i8 @shl_trunc_bigger_lshr(i32 %x) {
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define i8 @shl_trunc_smaller_lshr(i32 %x) {
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; CHECK-LABEL: @shl_trunc_smaller_lshr(
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i8
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; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[X_TR]], 2
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; CHECK-NEXT: [[LT:%.*]] = and i8 [[TMP1]], -32
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; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = shl i8 [[X_TR]], 2
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; CHECK-NEXT: [[LT:%.*]] = and i8 [[TR_SH_DIFF]], -32
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; CHECK-NEXT: ret i8 [[LT]]
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;
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%rt = lshr i32 %x, 3
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@@ -165,9 +165,9 @@ define i8 @shl_trunc_smaller_lshr(i32 %x) {
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define i24 @shl_trunc_bigger_ashr(i32 %x) {
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; CHECK-LABEL: @shl_trunc_bigger_ashr(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 9
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
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; CHECK-NEXT: [[LT:%.*]] = and i24 [[TMP2]], -8
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; CHECK-NEXT: [[SH_DIFF:%.*]] = ashr i32 [[X:%.*]], 9
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; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc i32 [[SH_DIFF]] to i24
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; CHECK-NEXT: [[LT:%.*]] = and i24 [[TR_SH_DIFF]], -8
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; CHECK-NEXT: ret i24 [[LT]]
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;
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%rt = ashr i32 %x, 12
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@@ -179,8 +179,8 @@ define i24 @shl_trunc_bigger_ashr(i32 %x) {
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define i24 @shl_trunc_smaller_ashr(i32 %x) {
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; CHECK-LABEL: @shl_trunc_smaller_ashr(
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i24
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; CHECK-NEXT: [[TMP1:%.*]] = shl i24 [[X_TR]], 3
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; CHECK-NEXT: [[LT:%.*]] = and i24 [[TMP1]], -8192
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; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = shl i24 [[X_TR]], 3
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; CHECK-NEXT: [[LT:%.*]] = and i24 [[TR_SH_DIFF]], -8192
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; CHECK-NEXT: ret i24 [[LT]]
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;
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%rt = ashr i32 %x, 10
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