[InstCombine] "Bypass" NUW trunc of lshr if we are going to sext the result (PR49543)
This is a more convoluted form of the same pattern "sext of NSW trunc", but in this case the operand of trunc was a right-shift, and the truncation chops off just the zero bits that were shifted-in.
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@@ -1498,6 +1498,36 @@ Instruction *InstCombinerImpl::visitSExt(SExtInst &CI) {
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unsigned DestBitSize = DestTy->getScalarSizeInBits();
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unsigned XBitSize = X->getType()->getScalarSizeInBits();
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// Iff we are chopping off all the zero bits that were just shifted-in,
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// instead perform the arithmetic shift, and bypass trunc by sign-extending
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// it directly. Either one of the lshr and trunc can have extra uses, we can
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// fix them up, but only one of them, else we increase instruction count.
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if (match(X,
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m_LShr(m_Value(), m_SpecificInt_ICMP(
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ICmpInst::Predicate::ICMP_EQ,
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APInt(XBitSize, XBitSize - SrcBitSize)))) &&
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(Src->hasOneUse() || X->hasOneUser())) {
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auto *LShr = cast<Instruction>(X);
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auto *AShr =
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BinaryOperator::CreateAShr(LShr->getOperand(0), LShr->getOperand(1),
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LShr->getName() + ".signed", LShr);
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if (!LShr->hasOneUse()) {
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auto *Mask =
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ConstantExpr::getLShr(Constant::getAllOnesValue(AShr->getType()),
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cast<Constant>(LShr->getOperand(1)));
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auto *NewLShr =
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BinaryOperator::CreateAnd(AShr, Mask, LShr->getName(), LShr);
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replaceInstUsesWith(*LShr, NewLShr);
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}
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if (!Src->hasOneUse()) {
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auto *OldTrunc = cast<Instruction>(Src);
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auto *NewTrunc = CastInst::Create(Instruction::Trunc, AShr, SrcTy,
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OldTrunc->getName(), OldTrunc);
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replaceInstUsesWith(*OldTrunc, NewTrunc);
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}
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return CastInst::Create(Instruction::SExt, AShr, DestTy);
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}
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// Iff X had more sign bits than the number of bits that were chopped off
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// by the truncation, we can directly sign-extend the X.
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unsigned XNumSignBits = ComputeNumSignBits(X, 0, &CI);
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@@ -12,9 +12,8 @@ declare void @usevec4(<2 x i4>)
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define i16 @t0(i8 %x) {
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; CHECK-LABEL: @t0(
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; CHECK-NEXT: [[A:%.*]] = lshr i8 [[X:%.*]], 4
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; CHECK-NEXT: [[B:%.*]] = trunc i8 [[A]] to i4
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; CHECK-NEXT: [[C:%.*]] = sext i4 [[B]] to i16
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr i8 [[X:%.*]], 4
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; CHECK-NEXT: [[C:%.*]] = sext i8 [[A_SIGNED]] to i16
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; CHECK-NEXT: ret i16 [[C]]
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;
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%a = lshr i8 %x, 4
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@@ -25,9 +24,8 @@ define i16 @t0(i8 %x) {
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define i16 @t1(i8 %x) {
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; CHECK-LABEL: @t1(
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; CHECK-NEXT: [[A:%.*]] = lshr i8 [[X:%.*]], 5
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; CHECK-NEXT: [[B:%.*]] = trunc i8 [[A]] to i3
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; CHECK-NEXT: [[C:%.*]] = sext i3 [[B]] to i16
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr i8 [[X:%.*]], 5
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; CHECK-NEXT: [[C:%.*]] = sext i8 [[A_SIGNED]] to i16
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; CHECK-NEXT: ret i16 [[C]]
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;
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%a = lshr i8 %x, 5
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@@ -38,9 +36,8 @@ define i16 @t1(i8 %x) {
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define i16 @t2(i7 %x) {
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; CHECK-LABEL: @t2(
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; CHECK-NEXT: [[A:%.*]] = lshr i7 [[X:%.*]], 3
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; CHECK-NEXT: [[B:%.*]] = trunc i7 [[A]] to i4
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; CHECK-NEXT: [[C:%.*]] = sext i4 [[B]] to i16
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr i7 [[X:%.*]], 3
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; CHECK-NEXT: [[C:%.*]] = sext i7 [[A_SIGNED]] to i16
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; CHECK-NEXT: ret i16 [[C]]
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;
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%a = lshr i7 %x, 3
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@@ -64,9 +61,8 @@ define i16 @n3(i8 %x) {
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define <2 x i16> @t4_vec_splat(<2 x i8> %x) {
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; CHECK-LABEL: @t4_vec_splat(
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; CHECK-NEXT: [[A:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 4, i8 4>
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; CHECK-NEXT: [[B:%.*]] = trunc <2 x i8> [[A]] to <2 x i4>
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i4> [[B]] to <2 x i16>
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 4, i8 4>
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i8> [[A_SIGNED]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[C]]
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;
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%a = lshr <2 x i8> %x, <i8 4, i8 4>
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@@ -77,9 +73,8 @@ define <2 x i16> @t4_vec_splat(<2 x i8> %x) {
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define <2 x i16> @t5_vec_undef(<2 x i8> %x) {
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; CHECK-LABEL: @t5_vec_undef(
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; CHECK-NEXT: [[A:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 4, i8 undef>
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; CHECK-NEXT: [[B:%.*]] = trunc <2 x i8> [[A]] to <2 x i4>
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i4> [[B]] to <2 x i16>
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 4, i8 undef>
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i8> [[A_SIGNED]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[C]]
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;
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%a = lshr <2 x i8> %x, <i8 4, i8 undef>
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@@ -90,10 +85,10 @@ define <2 x i16> @t5_vec_undef(<2 x i8> %x) {
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define i16 @t6_extrause0(i8 %x) {
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; CHECK-LABEL: @t6_extrause0(
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; CHECK-NEXT: [[A:%.*]] = lshr i8 [[X:%.*]], 4
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; CHECK-NEXT: [[B:%.*]] = trunc i8 [[A]] to i4
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; CHECK-NEXT: call void @use4(i4 [[B]])
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; CHECK-NEXT: [[C:%.*]] = sext i4 [[B]] to i16
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr i8 [[X:%.*]], 4
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; CHECK-NEXT: [[B1:%.*]] = trunc i8 [[A_SIGNED]] to i4
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; CHECK-NEXT: call void @use4(i4 [[B1]])
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; CHECK-NEXT: [[C:%.*]] = sext i8 [[A_SIGNED]] to i16
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; CHECK-NEXT: ret i16 [[C]]
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;
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%a = lshr i8 %x, 4
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@@ -104,10 +99,10 @@ define i16 @t6_extrause0(i8 %x) {
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}
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define <2 x i16> @t7_extrause0_vec_undef(<2 x i8> %x) {
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; CHECK-LABEL: @t7_extrause0_vec_undef(
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; CHECK-NEXT: [[A:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 4, i8 undef>
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; CHECK-NEXT: [[B:%.*]] = trunc <2 x i8> [[A]] to <2 x i4>
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; CHECK-NEXT: call void @usevec4(<2 x i4> [[B]])
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i4> [[B]] to <2 x i16>
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 4, i8 undef>
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; CHECK-NEXT: [[B1:%.*]] = trunc <2 x i8> [[A_SIGNED]] to <2 x i4>
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; CHECK-NEXT: call void @usevec4(<2 x i4> [[B1]])
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i8> [[A_SIGNED]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[C]]
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;
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%a = lshr <2 x i8> %x, <i8 4, i8 undef>
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@@ -118,10 +113,10 @@ define <2 x i16> @t7_extrause0_vec_undef(<2 x i8> %x) {
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}
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define i16 @t8_extrause1(i8 %x) {
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; CHECK-LABEL: @t8_extrause1(
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; CHECK-NEXT: [[A:%.*]] = lshr i8 [[X:%.*]], 4
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; CHECK-NEXT: call void @use8(i8 [[A]])
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; CHECK-NEXT: [[B:%.*]] = trunc i8 [[A]] to i4
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; CHECK-NEXT: [[C:%.*]] = sext i4 [[B]] to i16
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr i8 [[X:%.*]], 4
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; CHECK-NEXT: [[A1:%.*]] = and i8 [[A_SIGNED]], 15
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; CHECK-NEXT: call void @use8(i8 [[A1]])
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; CHECK-NEXT: [[C:%.*]] = sext i8 [[A_SIGNED]] to i16
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; CHECK-NEXT: ret i16 [[C]]
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;
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%a = lshr i8 %x, 4 ; has extra use, but we can deal with that
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@@ -132,10 +127,10 @@ define i16 @t8_extrause1(i8 %x) {
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}
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define <2 x i16> @t9_extrause1_vec_undef(<2 x i8> %x) {
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; CHECK-LABEL: @t9_extrause1_vec_undef(
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; CHECK-NEXT: [[A:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 4, i8 undef>
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; CHECK-NEXT: call void @usevec8(<2 x i8> [[A]])
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; CHECK-NEXT: [[B:%.*]] = trunc <2 x i8> [[A]] to <2 x i4>
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i4> [[B]] to <2 x i16>
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; CHECK-NEXT: [[A_SIGNED:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 4, i8 undef>
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; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A_SIGNED]], <i8 15, i8 undef>
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; CHECK-NEXT: call void @usevec8(<2 x i8> [[A1]])
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; CHECK-NEXT: [[C:%.*]] = sext <2 x i8> [[A_SIGNED]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[C]]
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;
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%a = lshr <2 x i8> %x, <i8 4, i8 undef>
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