[Clang] Start moving X86Builtins.def to X86Builtins.td (#106005)
This starts moving `X86Builtins.def` to be a tablegen file. It's quite large, so I think it'd be good to move things in multiple steps to avoid a bunch of merge conflicts due to the amount of time this takes to complete.
This commit is contained in:
Nikolas Klauser
@@ -60,6 +60,10 @@ def ConstIgnoringExceptions : Attribute<"g">;
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// This function requires a specific header or an explicit declaration.
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def RequireDeclaration : Attribute<"h">;
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// FIXME: Why is this not simply the min_vector_width attribute?
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// Vector has to be at least N bits wide.
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class RequiredVectorWidth<int N> : IndexedAttribute<"V", N>;
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class PrintfFormat<int I> : IndexedAttribute<"p", I>;
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class VPrintfFormat<int I> : IndexedAttribute<"P", I>;
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class ScanfFormat<int I> : IndexedAttribute<"s", I>;
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@@ -26,17 +26,6 @@
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# define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE) BUILTIN(ID, TYPE, ATTRS)
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#endif
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// Undefined Values
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//
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TARGET_BUILTIN(__builtin_ia32_undef128, "V2d", "ncV:128:", "")
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TARGET_BUILTIN(__builtin_ia32_undef256, "V4d", "ncV:256:", "")
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TARGET_BUILTIN(__builtin_ia32_undef512, "V8d", "ncV:512:", "")
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// FLAGS
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//
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TARGET_BUILTIN(__builtin_ia32_readeflags_u32, "Ui", "n", "")
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TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "")
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// MMX
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//
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// All MMX instructions will be generated via builtins. Any MMX vector
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@@ -46,113 +35,8 @@ TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "")
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// argument and our prior approach of using a #define to the current built-in
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// doesn't work in the presence of re-declaration of _mm_prefetch for windows.
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TARGET_BUILTIN(_mm_prefetch, "vcC*i", "nc", "mmx")
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TARGET_BUILTIN(__builtin_ia32_emms, "v", "n", "mmx")
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TARGET_BUILTIN(__builtin_ia32_vec_ext_v4hi, "sV4sIi", "ncV:64:", "sse")
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TARGET_BUILTIN(__builtin_ia32_vec_set_v4hi, "V4sV4ssIi", "ncV:64:", "sse")
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// SSE intrinsics.
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TARGET_BUILTIN(__builtin_ia32_comieq, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_comilt, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_comile, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_comigt, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_comige, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_comineq, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_ucomieq, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_ucomilt, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_ucomile, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_ucomigt, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_ucomige, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_ucomineq, "iV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_comisdeq, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_comisdlt, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_comisdle, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_comisdgt, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_comisdge, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_comisdneq, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_ucomisdeq, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_ucomisdlt, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_ucomisdle, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_ucomisdgt, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_ucomisdge, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_ucomisdneq, "iV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpeqps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpltps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpleps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpunordps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpneqps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpnltps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpnleps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpordps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpeqss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpltss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpless, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpunordss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpneqss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpnltss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpnless, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpordss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "sse")
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TARGET_BUILTIN(__builtin_ia32_cmpeqpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpltpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmplepd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpunordpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpneqpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpnltpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpnlepd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpordpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpeqsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpltsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmplesd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpunordsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpneqsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpnltsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpnlesd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpordsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_maxsd, "V2dV2dV2d", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_pmulhw128, "V8sV8sV8s", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_pavgb128, "V16cV16cV16c", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_pavgw128, "V8sV8sV8s", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_packsswb128, "V16cV8sV8s", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_packssdw128, "V8sV4iV4i", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_packuswb128, "V16cV8sV8s", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_pmulhuw128, "V8sV8sV8s", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_vec_ext_v2di, "OiV2OiIi", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_vec_ext_v4si, "iV4iIi", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_vec_ext_v4sf, "fV4fIi", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_vec_ext_v8hi, "sV8sIi", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_vec_set_v8hi, "V8sV8ssIi", "ncV:128:", "sse2")
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TARGET_BUILTIN(__builtin_ia32_addsubps, "V4fV4fV4f", "ncV:128:", "sse3")
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TARGET_BUILTIN(__builtin_ia32_addsubpd, "V2dV2dV2d", "ncV:128:", "sse3")
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TARGET_BUILTIN(__builtin_ia32_haddps, "V4fV4fV4f", "ncV:128:", "sse3")
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TARGET_BUILTIN(__builtin_ia32_haddpd, "V2dV2dV2d", "ncV:128:", "sse3")
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TARGET_BUILTIN(__builtin_ia32_hsubps, "V4fV4fV4f", "ncV:128:", "sse3")
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TARGET_BUILTIN(__builtin_ia32_hsubpd, "V2dV2dV2d", "ncV:128:", "sse3")
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TARGET_BUILTIN(__builtin_ia32_phaddw128, "V8sV8sV8s", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_phaddd128, "V4iV4iV4i", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_phaddsw128, "V8sV8sV8s", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_phsubw128, "V8sV8sV8s", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_phsubd128, "V4iV4iV4i", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_phsubsw128, "V8sV8sV8s", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_pmaddubsw128, "V8sV16cV16c", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_pmulhrsw128, "V8sV8sV8s", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_pshufb128, "V16cV16cV16c", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_psignb128, "V16cV16cV16c", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_psignw128, "V8sV8sV8s", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_psignd128, "V4iV4iV4i", "ncV:128:", "ssse3")
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TARGET_BUILTIN(__builtin_ia32_ldmxcsr, "vUi", "n", "sse")
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TARGET_HEADER_BUILTIN(_mm_setcsr, "vUi", "nh",XMMINTRIN_H, ALL_LANGUAGES, "sse")
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@@ -316,16 +200,6 @@ TARGET_BUILTIN(__builtin_ia32_pclmulqdq256, "V4OiV4OiV4OiIc", "ncV:256:", "vpclm
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TARGET_BUILTIN(__builtin_ia32_pclmulqdq512, "V8OiV8OiV8OiIc", "ncV:512:", "avx512f,evex512,vpclmulqdq")
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// AVX
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TARGET_BUILTIN(__builtin_ia32_addsubpd256, "V4dV4dV4d", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_addsubps256, "V8fV8fV8f", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_haddpd256, "V4dV4dV4d", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_hsubps256, "V8fV8fV8f", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_hsubpd256, "V4dV4dV4d", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_haddps256, "V8fV8fV8f", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_maxpd256, "V4dV4dV4d", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_maxps256, "V8fV8fV8f", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_minpd256, "V4dV4dV4d", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_minps256, "V8fV8fV8f", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_vpermilvarpd, "V2dV2dV2Oi", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_vpermilvarps, "V4fV4fV4i", "ncV:256:", "avx")
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TARGET_BUILTIN(__builtin_ia32_vpermilvarpd256, "V4dV4dV4Oi", "ncV:256:", "avx")
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137
clang/include/clang/Basic/BuiltinsX86.td
Normal file
137
clang/include/clang/Basic/BuiltinsX86.td
Normal file
@@ -0,0 +1,137 @@
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//===--- BuiltinsX86.td - X86 Builtin function database ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86-specific builtin function database.
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//
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//===----------------------------------------------------------------------===//
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include "clang/Basic/BuiltinsBase.td"
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class X86Builtin<string prototype> : TargetBuiltin {
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let Spellings = ["__builtin_ia32_" # NAME];
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let Prototype = prototype;
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}
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// Undefined Values
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def undef128 : X86Builtin<"_Vector<2, double>()"> {
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let Attributes = [Const, NoThrow, RequiredVectorWidth<128>];
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}
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def undef256 : X86Builtin<"_Vector<4, double>()"> {
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let Attributes = [Const, NoThrow, RequiredVectorWidth<256>];
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}
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def undef512 : X86Builtin<"_Vector<8, double>()"> {
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let Attributes = [Const, NoThrow, RequiredVectorWidth<512>];
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}
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// FLAGS
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def readeflags_u32 : X86Builtin<"unsigned int()"> {
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let Attributes = [NoThrow];
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}
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def writeeflags_u32 : X86Builtin<"void(unsigned int)"> {
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let Attributes = [NoThrow];
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}
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// MMX
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//
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// All MMX instructions will be generated via builtins. Any MMX vector
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// types (<1 x i64>, <2 x i32>, etc.) that aren't used by these builtins will be
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// expanded by the back-end.
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def emms : X86Builtin<"void()"> {
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let Attributes = [NoThrow];
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let Features = "mmx";
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}
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let Attributes = [NoThrow, Const, RequiredVectorWidth<64>], Features = "sse" in {
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def vec_ext_v4hi : X86Builtin<"short(_Vector<4, short>, _Constant int)">;
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def vec_set_v4hi : X86Builtin<"_Vector<4, short>(_Vector<4, short>, short, _Constant int)">;
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}
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// SSE intrinsics
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let Attributes = [Const, NoThrow, RequiredVectorWidth<128>] in {
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foreach Cmp = ["eq", "lt", "le", "gt", "ge", "neq"] in {
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let Features = "sse" in {
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def comi#Cmp : X86Builtin<"int(_Vector<4, float>, _Vector<4, float>)">;
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def ucomi#Cmp : X86Builtin<"int(_Vector<4, float>, _Vector<4, float>)">;
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}
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let Features = "sse2" in {
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def comisd#Cmp : X86Builtin<"int(_Vector<2, double>, _Vector<2, double>)">;
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def ucomisd#Cmp : X86Builtin<"int(_Vector<2, double>, _Vector<2, double>)">;
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}
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}
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foreach Cmp = ["cmpeq", "cmplt", "cmple", "cmpunord", "cmpneq", "cmpnlt",
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"cmpnle", "cmpord", "min", "max"] in {
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let Features = "sse" in {
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def Cmp#ps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">;
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def Cmp#ss : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">;
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}
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let Features = "sse2" in {
|
||||
def Cmp#pd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">;
|
||||
def Cmp#sd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">;
|
||||
}
|
||||
}
|
||||
|
||||
let Features = "sse" in {
|
||||
def cmpps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant char)">;
|
||||
def cmpss : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant char)">;
|
||||
}
|
||||
|
||||
let Features = "sse2" in {
|
||||
def cmppd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant char)">;
|
||||
def cmpsd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant char)">;
|
||||
}
|
||||
|
||||
let Features = "sse2" in {
|
||||
def pmulhw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def pavgb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">;
|
||||
def pavgw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def packsswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def packssdw128 : X86Builtin<"_Vector<8, short>(_Vector<4, int>, _Vector<4, int>)">;
|
||||
def packuswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def pmulhuw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def vec_ext_v2di : X86Builtin<"long long int(_Vector<2, long long int>, _Constant int)">;
|
||||
def vec_ext_v4si : X86Builtin<"int(_Vector<4, int>, _Constant int)">;
|
||||
def vec_ext_v4sf : X86Builtin<"float(_Vector<4, float>, _Constant int)">;
|
||||
def vec_ext_v8hi : X86Builtin<"short(_Vector<8, short>, _Constant int)">;
|
||||
def vec_set_v8hi : X86Builtin<"_Vector<8, short>(_Vector<8, short>, short, _Constant int)">;
|
||||
}
|
||||
|
||||
let Features = "sse3" in {
|
||||
foreach Op = ["addsub", "hadd", "hsub"] in {
|
||||
def Op#ps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">;
|
||||
def Op#pd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">;
|
||||
}
|
||||
}
|
||||
|
||||
let Features = "ssse3" in {
|
||||
foreach Op = ["phadd", "phsub"] in {
|
||||
def Op#w128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def Op#sw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def Op#d128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">;
|
||||
}
|
||||
|
||||
def pmaddubsw128 : X86Builtin<"_Vector<8, short>(_Vector<16, char>, _Vector<16, char>)">;
|
||||
def pmulhrsw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def pshufb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">;
|
||||
def psignb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">;
|
||||
def psignw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
|
||||
def psignd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">;
|
||||
}
|
||||
}
|
||||
|
||||
// AVX
|
||||
let Attributes = [Const, NoThrow, RequiredVectorWidth<256>], Features = "avx" in {
|
||||
foreach Op = ["addsub", "hadd", "hsub", "max", "min"] in {
|
||||
def Op#pd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>)">;
|
||||
def Op#ps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>)">;
|
||||
}
|
||||
}
|
||||
@@ -60,6 +60,10 @@ clang_tablegen(BuiltinsRISCV.inc -gen-clang-builtins
|
||||
SOURCE BuiltinsRISCV.td
|
||||
TARGET ClangBuiltinsRISCV)
|
||||
|
||||
clang_tablegen(BuiltinsX86.inc -gen-clang-builtins
|
||||
SOURCE BuiltinsX86.td
|
||||
TARGET ClangBuiltinsX86)
|
||||
|
||||
# ARM NEON and MVE
|
||||
clang_tablegen(arm_neon.inc -gen-arm-neon-sema
|
||||
SOURCE arm_neon.td
|
||||
|
||||
@@ -125,6 +125,8 @@ namespace clang {
|
||||
LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
|
||||
#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
|
||||
#include "clang/Basic/BuiltinsX86.def"
|
||||
#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
|
||||
#include "clang/Basic/BuiltinsX86.inc"
|
||||
FirstX86_64Builtin,
|
||||
LastX86CommonBuiltin = FirstX86_64Builtin - 1,
|
||||
#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
|
||||
|
||||
@@ -32,6 +32,14 @@ static constexpr Builtin::Info BuiltinInfoX86[] = {
|
||||
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
|
||||
#include "clang/Basic/BuiltinsX86.def"
|
||||
|
||||
#define BUILTIN(ID, TYPE, ATTRS) \
|
||||
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
|
||||
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
|
||||
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
|
||||
#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
|
||||
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
|
||||
#include "clang/Basic/BuiltinsX86.inc"
|
||||
|
||||
#define BUILTIN(ID, TYPE, ATTRS) \
|
||||
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
|
||||
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
|
||||
|
||||
@@ -64,7 +64,8 @@ private:
|
||||
// detecting the comma of the template class as a separator for
|
||||
// the parameters of the prototype. Note: the assumption is that
|
||||
// we cannot have nested _ExtVector.
|
||||
if (Current.starts_with("_ExtVector<")) {
|
||||
if (Current.starts_with("_ExtVector<") ||
|
||||
Current.starts_with("_Vector<")) {
|
||||
const size_t EndTemplate = Current.find('>', 0);
|
||||
ParseType(Current.substr(0, EndTemplate + 1));
|
||||
// Move the prototype beyond _ExtVector<...>
|
||||
@@ -123,7 +124,8 @@ private:
|
||||
if (Substitution.empty())
|
||||
PrintFatalError(Loc, "Not a template");
|
||||
ParseType(Substitution);
|
||||
} else if (T.consume_front("_ExtVector")) {
|
||||
} else if (auto IsExt = T.consume_front("_ExtVector");
|
||||
IsExt || T.consume_front("_Vector")) {
|
||||
// Clang extended vector types are mangled as follows:
|
||||
//
|
||||
// '_ExtVector<' <lanes> ',' <scalar type> '>'
|
||||
@@ -135,7 +137,7 @@ private:
|
||||
unsigned long long Lanes;
|
||||
if (consumeUnsignedInteger(T, 10, Lanes))
|
||||
PrintFatalError(Loc, "Expected number of lanes after '_ExtVector<'");
|
||||
Type += "E" + std::to_string(Lanes);
|
||||
Type += (IsExt ? "E" : "V") + std::to_string(Lanes);
|
||||
if (!T.consume_front(","))
|
||||
PrintFatalError(Loc,
|
||||
"Expected ',' after number of lanes in '_ExtVector<'");
|
||||
|
||||
Reference in New Issue
Block a user