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[RISCV][TII] Add and use new hook to simplify/canonicalize instructions after MachineCopyPropagation (#137973)

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PR #136875 was posted as a draft PR that handled a subset of these
cases, using the CompressPat mechanism. The consensus from that
discussion (and a conclusion I agree with) is that it would be
beneficial doing this optimisation earlier on, and in a way that isn't
limited just to cases that can be handled by instruction compression.

The most common source for instructions that can be
optimized/canonicalized in this way is through tail duplication in
MachineBlockPlacement followed by machine copy propagation. For RISC-V,
choosing a more canonical instruction allows it to be compressed when it
couldn't be before. There is the potential that it would make other
MI-level optimisations easier.

This modifies ~910 instructions across an llvm-test-suite build
including SPEC2017, targeting rva22u64. Looking at the diff, it seems
there's room for eliminating instructions or further propagating after
this.

Coverage of instructions is based on observations from a script written
to find redundant or improperly canonicalized instructions (though I aim
to support all instructions in a 'group' at once, e.g. MUL* even if I
only saw some variants of MUL in practice).
This commit is contained in:
Alex Bradbury
2025-05-08 12:33:14 +01:00
committed by GitHub
parent 245def9def
commit 52b345d036
5 changed files with 310 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
llvm/include/llvm/CodeGen/TargetInstrInfo.h
View File

@@ -510,6 +510,16 @@ public:
return false;
}
/// If possible, converts the instruction to a simplified/canonical form.
/// Returns true if the instruction was modified.
///
/// This function is only called after register allocation. The MI will be
/// modified in place. This is called by passes such as
/// MachineCopyPropagation, where their mutation of the MI operands may
/// expose opportunities to convert the instruction to a simpler form (e.g.
/// a load of 0).
virtual bool simplifyInstruction(MachineInstr &MI) const { return false; }
/// A pair composed of a register and a sub-register index.
/// Used to give some type checking when modeling Reg:SubReg.
struct RegSubRegPair {

6
llvm/lib/CodeGen/MachineCopyPropagation.cpp
View File

@@ -870,6 +870,12 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
++NumCopyForwards;
Changed = true;
}
// Attempt to canonicalize/optimize the instruction now its arguments have
// been mutated.
if (TII->simplifyInstruction(MI)) {
Changed = true;
LLVM_DEBUG(dbgs() << "MCP: After optimizeInstruction: " << MI);
}
}
void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {

225
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View File

@@ -2347,6 +2347,21 @@ static unsigned getSHXADDShiftAmount(unsigned Opc) {
}
}
// Returns the shift amount from a SHXADD.UW instruction. Returns 0 if the
// instruction is not a SHXADD.UW.
static unsigned getSHXADDUWShiftAmount(unsigned Opc) {
switch (Opc) {
default:
return 0;
case RISCV::SH1ADD_UW:
return 1;
case RISCV::SH2ADD_UW:
return 2;
case RISCV::SH3ADD_UW:
return 3;
}
}
// Look for opportunities to combine (sh3add Z, (add X, (slli Y, 5))) into
// (sh3add (sh2add Y, Z), X).
static bool getSHXADDPatterns(const MachineInstr &Root,
@@ -3876,6 +3891,216 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
#undef CASE_VFMA_OPCODE_VV
#undef CASE_VFMA_SPLATS
bool RISCVInstrInfo::simplifyInstruction(MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
break;
case RISCV::ADD:
case RISCV::OR:
case RISCV::XOR:
// Normalize (so we hit the next if clause).
// add/[x]or rd, zero, rs => add/[x]or rd, rs, zero
if (MI.getOperand(1).getReg() == RISCV::X0)
commuteInstruction(MI);
// add/[x]or rd, rs, zero => addi rd, rs, 0
if (MI.getOperand(2).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
// xor rd, rs, rs => addi rd, zero, 0
if (MI.getOpcode() == RISCV::XOR &&
MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
MI.getOperand(1).setReg(RISCV::X0);
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::ORI:
case RISCV::XORI:
// [x]ori rd, zero, N => addi rd, zero, N
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::SUB:
// sub rd, rs, zero => addi rd, rs, 0
if (MI.getOperand(2).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::SUBW:
// subw rd, rs, zero => addiw rd, rs, 0
if (MI.getOperand(2).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDIW));
return true;
}
break;
case RISCV::ADDW:
// Normalize (so we hit the next if clause).
// addw rd, zero, rs => addw rd, rs, zero
if (MI.getOperand(1).getReg() == RISCV::X0)
commuteInstruction(MI);
// addw rd, rs, zero => addiw rd, rs, 0
if (MI.getOperand(2).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDIW));
return true;
}
break;
case RISCV::SH1ADD:
case RISCV::SH1ADD_UW:
case RISCV::SH2ADD:
case RISCV::SH2ADD_UW:
case RISCV::SH3ADD:
case RISCV::SH3ADD_UW:
// shNadd[.uw] rd, zero, rs => addi rd, rs, 0
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.removeOperand(1);
MI.addOperand(MachineOperand::CreateImm(0));
MI.setDesc(get(RISCV::ADDI));
return true;
}
// shNadd[.uw] rd, rs, zero => slli[.uw] rd, rs, N
if (MI.getOperand(2).getReg() == RISCV::X0) {
MI.removeOperand(2);
unsigned Opc = MI.getOpcode();
if (Opc == RISCV::SH1ADD_UW || Opc == RISCV::SH2ADD_UW ||
Opc == RISCV::SH3ADD_UW) {
MI.addOperand(MachineOperand::CreateImm(getSHXADDUWShiftAmount(Opc)));
MI.setDesc(get(RISCV::SLLI_UW));
return true;
}
MI.addOperand(MachineOperand::CreateImm(getSHXADDShiftAmount(Opc)));
MI.setDesc(get(RISCV::SLLI));
return true;
}
break;
case RISCV::AND:
case RISCV::MUL:
case RISCV::MULH:
case RISCV::MULHSU:
case RISCV::MULHU:
case RISCV::MULW:
// and rd, zero, rs => addi rd, zero, 0
// mul* rd, zero, rs => addi rd, zero, 0
// and rd, rs, zero => addi rd, zero, 0
// mul* rd, rs, zero => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0 ||
MI.getOperand(2).getReg() == RISCV::X0) {
MI.getOperand(1).setReg(RISCV::X0);
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::ANDI:
// andi rd, zero, C => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.getOperand(2).setImm(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::SLL:
case RISCV::SRL:
case RISCV::SRA:
// shift rd, zero, rs => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
// shift rd, rs, zero => addi rd, rs, 0
if (MI.getOperand(2).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::SLLW:
case RISCV::SRLW:
case RISCV::SRAW:
// shiftw rd, zero, rs => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::SLLI:
case RISCV::SRLI:
case RISCV::SRAI:
case RISCV::SLLIW:
case RISCV::SRLIW:
case RISCV::SRAIW:
case RISCV::SLLI_UW:
// shiftimm rd, zero, N => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.getOperand(2).setImm(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::SLTU:
case RISCV::ADD_UW:
// sltu rd, zero, zero => addi rd, zero, 0
// add.uw rd, zero, zero => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0 &&
MI.getOperand(2).getReg() == RISCV::X0) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
// add.uw rd, zero, rs => addi rd, rs, 0
if (MI.getOpcode() == RISCV::ADD_UW &&
MI.getOperand(1).getReg() == RISCV::X0) {
MI.removeOperand(1);
MI.addOperand(MachineOperand::CreateImm(0));
MI.setDesc(get(RISCV::ADDI));
}
break;
case RISCV::SLTIU:
// sltiu rd, zero, NZC => addi rd, zero, 1
// sltiu rd, zero, 0 => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.getOperand(2).setImm(MI.getOperand(2).getImm() != 0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::SEXT_H:
case RISCV::SEXT_B:
case RISCV::ZEXT_H_RV32:
case RISCV::ZEXT_H_RV64:
// sext.[hb] rd, zero => addi rd, zero, 0
// zext.h rd, zero => addi rd, zero, 0
if (MI.getOperand(1).getReg() == RISCV::X0) {
MI.addOperand(MachineOperand::CreateImm(0));
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
case RISCV::MIN:
case RISCV::MINU:
case RISCV::MAX:
case RISCV::MAXU:
// min|max rd, rs, rs => addi rd, rs, 0
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
MI.getOperand(2).ChangeToImmediate(0);
MI.setDesc(get(RISCV::ADDI));
return true;
}
break;
}
return false;
}
// clang-format off
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) \
RISCV::PseudoV##OP##_##LMUL##_TIED

2
llvm/lib/Target/RISCV/RISCVInstrInfo.h
View File

@@ -242,6 +242,8 @@ public:
unsigned OpIdx1,
unsigned OpIdx2) const override;
bool simplifyInstruction(MachineInstr &MI) const override;
MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
LiveIntervals *LIS) const override;

136
llvm/test/CodeGen/RISCV/machine-copyprop-simplifyinstruction.mir
View File

@@ -4,14 +4,12 @@
# Check that instruction simplifications expected to be performed after
# machine copy propagation are done.
# TODO: Not yet implemented.
---
name: add1
body: |
bb.0:
; CHECK-LABEL: name: add1
; CHECK: renamable $x10 = ADD $x12, $x0
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = ADD renamable $x11, $x0
@@ -22,7 +20,7 @@ name: add2
body: |
bb.0:
; CHECK-LABEL: name: add2
; CHECK: renamable $x10 = ADD $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = ADD $x0, renamable $x11
@@ -33,7 +31,7 @@ name: or1
body: |
bb.0:
; CHECK-LABEL: name: or1
; CHECK: renamable $x10 = OR $x12, $x0
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = OR renamable $x11, $x0
@@ -44,7 +42,7 @@ name: or2
body: |
bb.0:
; CHECK-LABEL: name: or2
; CHECK: renamable $x10 = OR $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = OR $x0, renamable $x11
@@ -55,7 +53,7 @@ name: xor1
body: |
bb.0:
; CHECK-LABEL: name: xor1
; CHECK: renamable $x10 = XOR $x12, $x0
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = XOR renamable $x11, $x0
@@ -66,7 +64,7 @@ name: xor2
body: |
bb.0:
; CHECK-LABEL: name: xor2
; CHECK: renamable $x10 = XOR $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = XOR $x0, renamable $x11
@@ -78,7 +76,7 @@ name: xor3
body: |
bb.0:
; CHECK-LABEL: name: xor3
; CHECK: renamable $x10 = XOR $x12, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = XOR renamable $x11, renamable $x11
@@ -89,7 +87,7 @@ name: addw1
body: |
bb.0:
; CHECK-LABEL: name: addw1
; CHECK: renamable $x10 = ADDW $x0, $x12
; CHECK: renamable $x10 = ADDIW $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = ADDW renamable $x11, $x12
@@ -100,7 +98,7 @@ name: addw2
body: |
bb.0:
; CHECK-LABEL: name: addw2
; CHECK: renamable $x10 = ADDW $x12, $x0
; CHECK: renamable $x10 = ADDIW $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = ADDW $x12, renamable $x11
@@ -111,7 +109,7 @@ name: sub
body: |
bb.0:
; CHECK-LABEL: name: sub
; CHECK: renamable $x10 = SUB $x12, $x0
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SUB renamable $x11, $x0
@@ -122,7 +120,7 @@ name: subw
body: |
bb.0:
; CHECK-LABEL: name: subw
; CHECK: renamable $x10 = SUBW $x12, $x0
; CHECK: renamable $x10 = ADDIW $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SUBW renamable $x11, $x0
@@ -133,7 +131,7 @@ name: sh1add1
body: |
bb.0:
; CHECK-LABEL: name: sh1add1
; CHECK: renamable $x10 = SH1ADD $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH1ADD $x0, renamable $x11
@@ -144,7 +142,7 @@ name: sh1add2
body: |
bb.0:
; CHECK-LABEL: name: sh1add2
; CHECK: renamable $x10 = SH1ADD $x12, $x0
; CHECK: renamable $x10 = SLLI $x12, 1
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH1ADD renamable $x11, $x0
@@ -155,7 +153,7 @@ name: sh1add.uw1
body: |
bb.0:
; CHECK-LABEL: name: sh1add.uw1
; CHECK: renamable $x10 = SH1ADD_UW $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH1ADD_UW $x0, renamable $x11
@@ -166,7 +164,7 @@ name: sh1add.uw2
body: |
bb.0:
; CHECK-LABEL: name: sh1add.uw2
; CHECK: renamable $x10 = SH1ADD_UW $x12, $x0
; CHECK: renamable $x10 = SLLI_UW $x12, 1
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH1ADD_UW renamable $x11, $x0
@@ -177,7 +175,7 @@ name: sh2add1
body: |
bb.0:
; CHECK-LABEL: name: sh2add1
; CHECK: renamable $x10 = SH2ADD $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH2ADD $x0, renamable $x11
@@ -188,7 +186,7 @@ name: sh2add2
body: |
bb.0:
; CHECK-LABEL: name: sh2add2
; CHECK: renamable $x10 = SH2ADD $x12, $x0
; CHECK: renamable $x10 = SLLI $x12, 2
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH2ADD renamable $x11, $x0
@@ -199,7 +197,7 @@ name: sh2add.uw1
body: |
bb.0:
; CHECK-LABEL: name: sh2add.uw1
; CHECK: renamable $x10 = SH2ADD_UW $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH2ADD_UW $x0, renamable $x11
@@ -210,7 +208,7 @@ name: sh2add.uw2
body: |
bb.0:
; CHECK-LABEL: name: sh2add.uw2
; CHECK: renamable $x10 = SH2ADD_UW $x12, $x0
; CHECK: renamable $x10 = SLLI_UW $x12, 2
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH2ADD_UW renamable $x11, $x0
@@ -221,7 +219,7 @@ name: sh3add1
body: |
bb.0:
; CHECK-LABEL: name: sh3add1
; CHECK: renamable $x10 = SH3ADD $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH3ADD $x0, renamable $x11
@@ -232,7 +230,7 @@ name: sh3add2
body: |
bb.0:
; CHECK-LABEL: name: sh3add2
; CHECK: renamable $x10 = SH3ADD $x12, $x0
; CHECK: renamable $x10 = SLLI $x12, 3
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH3ADD renamable $x11, $x0
@@ -243,7 +241,7 @@ name: sh3add.uw1
body: |
bb.0:
; CHECK-LABEL: name: sh3add.uw1
; CHECK: renamable $x10 = SH3ADD_UW $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH3ADD_UW $x0, renamable $x11
@@ -254,7 +252,7 @@ name: sh3add.uw2
body: |
bb.0:
; CHECK-LABEL: name: sh3add.uw2
; CHECK: renamable $x10 = SH3ADD_UW $x12, $x0
; CHECK: renamable $x10 = SLLI_UW $x12, 3
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SH3ADD_UW renamable $x11, $x0
@@ -265,7 +263,7 @@ name: andi
body: |
bb.0:
; CHECK-LABEL: name: andi
; CHECK: renamable $x10 = ANDI $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = ANDI renamable $x11, 13
@@ -276,7 +274,7 @@ name: and1
body: |
bb.0:
; CHECK-LABEL: name: and1
; CHECK: renamable $x10 = AND $x12, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = AND renamable $x11, $x0
@@ -287,7 +285,7 @@ name: and2
body: |
bb.0:
; CHECK-LABEL: name: and2
; CHECK: renamable $x10 = AND $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = AND $x0, renamable $x11
@@ -298,7 +296,7 @@ name: mul1
body: |
bb.0:
; CHECK-LABEL: name: mul1
; CHECK: renamable $x10 = MUL $x12, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MUL renamable $x11, $x0
@@ -309,7 +307,7 @@ name: mul2
body: |
bb.0:
; CHECK-LABEL: name: mul2
; CHECK: renamable $x10 = MUL $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MUL $x0, renamable $x11
@@ -320,7 +318,7 @@ name: mulh1
body: |
bb.0:
; CHECK-LABEL: name: mulh1
; CHECK: renamable $x10 = MULH $x12, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULH renamable $x11, $x0
@@ -331,7 +329,7 @@ name: mulh2
body: |
bb.0:
; CHECK-LABEL: name: mulh2
; CHECK: renamable $x10 = MULH $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULH $x0, renamable $x11
@@ -342,7 +340,7 @@ name: mulhsu1
body: |
bb.0:
; CHECK-LABEL: name: mulhsu1
; CHECK: renamable $x10 = MULHSU $x12, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULHSU renamable $x11, $x0
@@ -353,7 +351,7 @@ name: mulhsu2
body: |
bb.0:
; CHECK-LABEL: name: mulhsu2
; CHECK: renamable $x10 = MULHSU $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULHSU $x0, renamable $x11
@@ -364,7 +362,7 @@ name: mulhu1
body: |
bb.0:
; CHECK-LABEL: name: mulhu1
; CHECK: renamable $x10 = MULHU $x12, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULHU renamable $x11, $x0
@@ -375,7 +373,7 @@ name: mulhu2
body: |
bb.0:
; CHECK-LABEL: name: mulhu2
; CHECK: renamable $x10 = MULHU $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULHU $x0, renamable $x11
@@ -386,7 +384,7 @@ name: mulw1
body: |
bb.0:
; CHECK-LABEL: name: mulw1
; CHECK: renamable $x10 = MULW $x12, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULW renamable $x11, $x0
@@ -397,7 +395,7 @@ name: mulw2
body: |
bb.0:
; CHECK-LABEL: name: mulw2
; CHECK: renamable $x10 = MULW $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MULW $x0, renamable $x11
@@ -408,7 +406,7 @@ name: slli
body: |
bb.0:
; CHECK-LABEL: name: slli
; CHECK: renamable $x10 = SLLI $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SLLI renamable $x11, 13
@@ -419,7 +417,7 @@ name: srli
body: |
bb.0:
; CHECK-LABEL: name: srli
; CHECK: renamable $x10 = SRLI $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SRLI renamable $x11, 13
@@ -430,7 +428,7 @@ name: srai
body: |
bb.0:
; CHECK-LABEL: name: srai
; CHECK: renamable $x10 = SRAI $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SRAI renamable $x11, 13
@@ -441,7 +439,7 @@ name: slliw
body: |
bb.0:
; CHECK-LABEL: name: slliw
; CHECK: renamable $x10 = SLLIW $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SLLIW renamable $x11, 13
@@ -452,7 +450,7 @@ name: srliw
body: |
bb.0:
; CHECK-LABEL: name: srliw
; CHECK: renamable $x10 = SRLIW $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SRLIW renamable $x11, 13
@@ -463,7 +461,7 @@ name: sraiw
body: |
bb.0:
; CHECK-LABEL: name: sraiw
; CHECK: renamable $x10 = SRAIW $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SRAIW renamable $x11, 13
@@ -474,7 +472,7 @@ name: slli_uw
body: |
bb.0:
; CHECK-LABEL: name: slli_uw
; CHECK: renamable $x10 = SLLI_UW $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SLLI_UW renamable $x11, 13
@@ -485,7 +483,7 @@ name: ori
body: |
bb.0:
; CHECK-LABEL: name: ori
; CHECK: renamable $x10 = ORI $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 13
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = ORI renamable $x11, 13
@@ -496,7 +494,7 @@ name: xori
body: |
bb.0:
; CHECK-LABEL: name: xori
; CHECK: renamable $x10 = XORI $x0, 13
; CHECK: renamable $x10 = ADDI $x0, 13
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = XORI renamable $x11, 13
@@ -507,7 +505,7 @@ name: sltiu1
body: |
bb.0:
; CHECK-LABEL: name: sltiu1
; CHECK: renamable $x10 = SLTIU $x0, 2
; CHECK: renamable $x10 = ADDI $x0, 1
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SLTIU renamable $x11, 2
@@ -518,7 +516,7 @@ name: sltiu2
body: |
bb.0:
; CHECK-LABEL: name: sltiu2
; CHECK: renamable $x10 = SLTIU $x0, 0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SLTIU renamable $x11, 0
@@ -529,7 +527,7 @@ name: sltu
body: |
bb.0:
; CHECK-LABEL: name: sltu
; CHECK: renamable $x10 = SLTU $x0, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SLTU renamable $x11, $x0
@@ -540,7 +538,7 @@ name: add.uw1
body: |
bb.0:
; CHECK-LABEL: name: add.uw1
; CHECK: renamable $x10 = ADD_UW $x0, $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = ADD_UW renamable $x11, $x0
@@ -551,7 +549,7 @@ name: add.uw2
body: |
bb.0:
; CHECK-LABEL: name: add.uw2
; CHECK: renamable $x10 = ADD_UW $x0, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = ADD_UW $x0, renamable $x11
@@ -562,7 +560,7 @@ name: sext.h
body: |
bb.0:
; CHECK-LABEL: name: sext.h
; CHECK: renamable $x10 = SEXT_H $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SEXT_H renamable $x11
@@ -573,7 +571,7 @@ name: sext.b
body: |
bb.0:
; CHECK-LABEL: name: sext.b
; CHECK: renamable $x10 = SEXT_B $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = SEXT_B renamable $x11
@@ -584,7 +582,7 @@ name: zext.h.rv32
body: |
bb.0:
; CHECK-LABEL: name: zext.h.rv32
; CHECK: renamable $x10 = ZEXT_H_RV32 $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = ZEXT_H_RV32 renamable $x11
@@ -595,7 +593,7 @@ name: zext.h.rv64
body: |
bb.0:
; CHECK-LABEL: name: zext.h.rv64
; CHECK: renamable $x10 = ZEXT_H_RV64 $x0
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x0
renamable $x10 = ZEXT_H_RV64 renamable $x11
@@ -606,7 +604,7 @@ name: sll1
body: |
bb.0:
; CHECK-LABEL: name: sll1
; CHECK: renamable $x10 = SLL $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SLL $x0, renamable $x11
@@ -617,7 +615,7 @@ name: sll2
body: |
bb.0:
; CHECK-LABEL: name: sll2
; CHECK: renamable $x10 = SLL $x12, $x0
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SLL renamable $x11, $x0
@@ -628,7 +626,7 @@ name: sr11
body: |
bb.0:
; CHECK-LABEL: name: sr11
; CHECK: renamable $x10 = SRL $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SRL $x0, renamable $x11
@@ -639,7 +637,7 @@ name: sr12
body: |
bb.0:
; CHECK-LABEL: name: sr12
; CHECK: renamable $x10 = SRL $x12, $x0
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SRL renamable $x11, $x0
@@ -650,7 +648,7 @@ name: sra1
body: |
bb.0:
; CHECK-LABEL: name: sra1
; CHECK: renamable $x10 = SRA $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SRA $x0, renamable $x11
@@ -661,7 +659,7 @@ name: sra2
body: |
bb.0:
; CHECK-LABEL: name: sra2
; CHECK: renamable $x10 = SRA $x12, $x0
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SRA renamable $x11, $x0
@@ -672,7 +670,7 @@ name: sllw
body: |
bb.0:
; CHECK-LABEL: name: sllw
; CHECK: renamable $x10 = SLLW $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SLLW $x0, renamable $x11
@@ -683,7 +681,7 @@ name: srlw
body: |
bb.0:
; CHECK-LABEL: name: srlw
; CHECK: renamable $x10 = SRLW $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SRLW $x0, renamable $x11
@@ -694,7 +692,7 @@ name: sraw
body: |
bb.0:
; CHECK-LABEL: name: sraw
; CHECK: renamable $x10 = SRAW $x0, $x12
; CHECK: renamable $x10 = ADDI $x0, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = SRAW $x0, renamable $x11
@@ -705,7 +703,7 @@ name: min
body: |
bb.0:
; CHECK-LABEL: name: min
; CHECK: renamable $x10 = MIN $x12, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MIN renamable $x11, renamable $x11
@@ -716,7 +714,7 @@ name: minu
body: |
bb.0:
; CHECK-LABEL: name: minu
; CHECK: renamable $x10 = MINU $x12, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MINU renamable $x11, renamable $x11
@@ -727,7 +725,7 @@ name: max
body: |
bb.0:
; CHECK-LABEL: name: max
; CHECK: renamable $x10 = MAX $x12, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MAX renamable $x11, renamable $x11
@@ -738,7 +736,7 @@ name: maxu
body: |
bb.0:
; CHECK-LABEL: name: maxu
; CHECK: renamable $x10 = MAXU $x12, $x12
; CHECK: renamable $x10 = ADDI $x12, 0
; CHECK-NEXT: PseudoRET implicit $x10
renamable $x11 = COPY $x12
renamable $x10 = MAXU renamable $x11, renamable $x11