[AMDGPU] Fix crash with 160-bit p7's by manually defining getPointerTy
While pointers in address space 7 (128 bit rsrc + 32 bit offset) should be rewritten out of the code before IR translation on AMDGPU, higher-level analyses may still call MVT getPointerTy() and the like on the target machine. Currently, since there is no MVT::i160, this operation ends up causing crashes. The changes to the data layout that caused such crashes were D149776. This patch causes getPointerTy() to return the type MVT::v5i32 and getPointerMemTy() to be MVT::v8i32. These are accurate types, but mean that we can't use vectors of address space 7 pointers during codegen. This is mostly OK, since vectors of buffers aren't supported in LPC anyway, but it's a noticable limitation. Potential alternative solutions include adjusting getPointerTy() to return an EVT or adding MVT::i160 and MVT::i256, both of which are rather disruptive to the rest of the compiler. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D150002
This commit is contained in:
Krzysztof Drewniak
@@ -979,6 +979,26 @@ static EVT memVTFromLoadIntrReturn(Type *Ty, unsigned MaxNumLanes) {
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return memVTFromLoadIntrData(ST->getContainedType(0), MaxNumLanes);
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}
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/// Map address space 7 to MVT::v5i32 because that's its in-memory
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/// representation. This return value is vector-typed because there is no
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/// MVT::i160 and it is not clear if one can be added. While this could
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/// cause issues during codegen, these address space 7 pointers will be
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/// rewritten away by then. Therefore, we can return MVT::v5i32 in order
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/// to allow pre-codegen passes that query TargetTransformInfo, often for cost
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/// modeling, to work.
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MVT SITargetLowering::getPointerTy(const DataLayout &DL, unsigned AS) const {
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if (AMDGPUAS::BUFFER_FAT_POINTER == AS && DL.getPointerSizeInBits(AS) == 160)
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return MVT::v5i32;
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return AMDGPUTargetLowering::getPointerTy(DL, AS);
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}
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/// Similarly, the in-memory representation of a p7 is {p8, i32}, aka
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/// v8i32 when padding is added.
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MVT SITargetLowering::getPointerMemTy(const DataLayout &DL, unsigned AS) const {
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if (AMDGPUAS::BUFFER_FAT_POINTER == AS && DL.getPointerSizeInBits(AS) == 160)
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return MVT::v8i32;
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return AMDGPUTargetLowering::getPointerMemTy(DL, AS);
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}
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bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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const CallInst &CI,
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MachineFunction &MF,
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@@ -273,6 +273,12 @@ public:
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bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
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// While address space 7 should never make it to codegen, it still needs to
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// have a MVT to prevent some analyses that query this function from breaking,
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// so, to work around the lack of i160, map it to v5i32.
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MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
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MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
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MachineFunction &MF,
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unsigned IntrinsicID) const override;
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@@ -0,0 +1,14 @@
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; RUN: not --crash llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - -stop-after=irtranslator < %s
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; Confirm that no one's gotten vectors of addrspace(7) pointers to go through the
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; IR translater incidentally.
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define <2 x ptr addrspace(7)> @no_auto_constfold_gep_vector() {
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%gep = getelementptr i8, <2 x ptr addrspace(7)> zeroinitializer, <2 x i32> <i32 123, i32 123>
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ret <2 x ptr addrspace(7)> %gep
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}
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define <2 x ptr addrspace(7)> @gep_vector_splat(<2 x ptr addrspace(7)> %ptrs, i64 %idx) {
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%gep = getelementptr i8, <2 x ptr addrspace(7)> %ptrs, i64 %idx
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ret <2 x ptr addrspace(7)> %gep
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}
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@@ -0,0 +1,20 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - -stop-after=irtranslator %s | FileCheck %s
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; Check that the CSEMIRBuilder doesn't fold away the getelementptr during IRTranslator
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define ptr addrspace(7) @no_auto_constfold_gep() {
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; CHECK-LABEL: name: no_auto_constfold_gep
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: [[C:%[0-9]+]]:_(p7) = G_CONSTANT i160 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s160) = G_CONSTANT i160 123
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p7) = G_PTR_ADD [[C]], [[C1]](s160)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[PTR_ADD]](p7)
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; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
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; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
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; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)
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; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4
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%gep = getelementptr i8, ptr addrspace(7) null, i32 123
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ret ptr addrspace(7) %gep
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}
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@@ -0,0 +1,60 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -passes=indvars -S < %s | FileCheck %s
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
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target triple = "amdgcn--amdpal"
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define void @f(ptr addrspace(7) %arg) {
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; CHECK-LABEL: define void @f
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; CHECK-SAME: (ptr addrspace(7) [[ARG:%.*]]) {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: br i1 false, label [[BB2:%.*]], label [[BB1]]
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; CHECK: bb2:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(7) [[ARG]], i32 8
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[I4:%.*]] = load i32, ptr addrspace(7) [[SCEVGEP]], align 4
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; CHECK-NEXT: br label [[BB3]]
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;
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bb:
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br label %bb1
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bb1:
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%i = getelementptr i32, ptr addrspace(7) %arg, i32 2
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br i1 false, label %bb2, label %bb1
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bb2:
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br label %bb3
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bb3:
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%i4 = load i32, ptr addrspace(7) %i, align 4
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br label %bb3
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}
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define void @f2(<2 x ptr addrspace(7)> %arg) {
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; CHECK-LABEL: define void @f2
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; CHECK-SAME: (<2 x ptr addrspace(7)> [[ARG:%.*]]) {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[P:%.*]] = extractelement <2 x ptr addrspace(7)> [[ARG]], i32 0
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; CHECK-NEXT: [[I:%.*]] = getelementptr i32, ptr addrspace(7) [[P]], i32 2
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; CHECK-NEXT: br i1 false, label [[BB2:%.*]], label [[BB1]]
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; CHECK: bb2:
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; CHECK-NEXT: [[I_LCSSA:%.*]] = phi ptr addrspace(7) [ [[I]], [[BB1]] ]
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[I4:%.*]] = load i32, ptr addrspace(7) [[I_LCSSA]], align 4
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; CHECK-NEXT: br label [[BB3]]
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;
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bb:
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br label %bb1
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bb1:
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%p = extractelement <2 x ptr addrspace(7)> %arg, i32 0
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%i = getelementptr i32, ptr addrspace(7) %p, i32 2
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br i1 false, label %bb2, label %bb1
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bb2:
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br label %bb3
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bb3:
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%i4 = load i32, ptr addrspace(7) %i, align 4
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br label %bb3
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}
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