[DAG] SimplifyDemandedBits - ensure we drop NSW/NUW flags when we simplify a SHL node's input
We already do this for variable shifts, but we missed it for constant shifts Fixes #69965
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@@ -1786,8 +1786,17 @@ bool TargetLowering::SimplifyDemandedBits(
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APInt InDemandedMask = DemandedBits.lshr(ShAmt);
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if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
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Depth + 1))
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Depth + 1)) {
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SDNodeFlags Flags = Op.getNode()->getFlags();
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if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
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// Disable the nsw and nuw flags. We can no longer guarantee that we
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// won't wrap after simplification.
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Flags.setNoSignedWrap(false);
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Flags.setNoUnsignedWrap(false);
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Op->setFlags(Flags);
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}
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return true;
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}
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assert(!Known.hasConflict() && "Bits known to be one AND zero?");
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Known.Zero <<= ShAmt;
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Known.One <<= ShAmt;
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@@ -10,10 +10,12 @@ define i64 @PR69965(ptr %input_ptrs, ptr %output_ptrs) {
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; X86-NEXT: movl (%eax), %eax
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; X86-NEXT: movzbl (%eax), %eax
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; X86-NEXT: notl %eax
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; X86-NEXT: movzbl %al, %edx
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; X86-NEXT: shll $8, %eax
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; X86-NEXT: movl %eax, %edx
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; X86-NEXT: shll $8, %edx
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; X86-NEXT: movl (%ecx), %ecx
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; X86-NEXT: leal (%eax,%edx,2), %eax
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; X86-NEXT: addb %al, %al
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; X86-NEXT: movzbl %al, %eax
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; X86-NEXT: orl %edx, %eax
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; X86-NEXT: orl $32768, %eax # imm = 0x8000
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; X86-NEXT: movw %ax, (%ecx)
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; X86-NEXT: xorl %eax, %eax
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@@ -25,13 +27,14 @@ define i64 @PR69965(ptr %input_ptrs, ptr %output_ptrs) {
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: movzbl (%rax), %eax
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; X64-NEXT: notl %eax
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; X64-NEXT: movzbl %al, %ecx
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; X64-NEXT: # kill: def $eax killed $eax def $rax
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; X64-NEXT: leal (%rax,%rax), %ecx
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; X64-NEXT: # kill: def $eax killed $eax killed $rax
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; X64-NEXT: shll $8, %eax
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; X64-NEXT: movq (%rsi), %rdx
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; X64-NEXT: leal (%rax,%rcx,2), %eax
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; X64-NEXT: orl $32768, %eax # imm = 0x8000
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; X64-NEXT: movw %ax, (%rdx)
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; X64-NEXT: movzbl %cl, %ecx
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; X64-NEXT: orl %eax, %ecx
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; X64-NEXT: orl $32768, %ecx # imm = 0x8000
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; X64-NEXT: movw %cx, (%rdx)
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: retq
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entry:
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