caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fix typo of colon to semicolon in lit tests

Browse Source
This commit is contained in:
Qiu Chaofan
2021-10-09 10:01:27 +08:00
parent 85ad566335
commit 573531fb1f
16 changed files with 32 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test
View File

@@ -8,9 +8,9 @@
# RUN: -o 'command source %t/foo/magritte.in' \
# RUN: -o 'command source %t/foo/zip.in' \
# RUN: -o 'command source %t/foo/magritte.in' \
# RUN; -o 'zip' \
# RUN: -o 'zip' \
# RUN: -o 'hello'
# RUN -o 'magritte' 2>&1 | FileCheck %s
# RUN: -o 'magritte' 2>&1 | FileCheck %s
# The first time importing 'magritte' fails because we didn't pass -c.
# CHECK: ModuleNotFoundError: No module named 'magritte'

2
llvm/test/Bitcode/attributes.ll
View File

@@ -404,7 +404,7 @@ define void @f68() mustprogress
ret void
}
; CHECK; define void @f69() #42
; CHECK: define void @f69() #42
define void @f69() nocallback
{
ret void

4
llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
View File

@@ -125,7 +125,7 @@ define i1 @test_EQ_IssEbT(i16 %a, i16 %b) {
; CHECK: sxth w8, w1
; CHECK-NEXT: cmn w8, w0, sxth
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT; ret
; CHECK-NEXT: ret
entry:
%conv = sext i16 %a to i32
%conv1 = sext i16 %b to i32
@@ -139,7 +139,7 @@ define i1 @test_EQ_IscEbT(i16 %a, i8 %b) {
; CHECK: and w8, w1, #0xff
; CHECK-NEXT: cmn w8, w0, sxth
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT; ret
; CHECK-NEXT: ret
entry:
%conv = sext i16 %a to i32
%conv1 = zext i8 %b to i32

2
llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
View File

@@ -97,7 +97,7 @@
; GCN: ; %Flow5
; GCN-NEXT: s_or_b64 exec, exec,
; GCN-NEXT; s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[EXIT0]]
; GCN-NEXT: s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[EXIT0]]
; GCN: ; %exit0
; GCN: buffer_store_dword

2
llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
View File

@@ -14,7 +14,7 @@ target triple = "thumbv7s-apple-ios"
; VMRS instruction comes before any other instruction writing FPSCR:
; CHECK-NOT: vcmp
; CHECK: vmrs {{r[0-9]}}, fpscr
; CHECK; vcmp
; CHECK: vcmp
; ...
; CHECK: add sp, #8
; CHECK: bx lr

2
llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
View File

@@ -42,7 +42,7 @@
declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
; 32BIT-LABEL: name: int_va_arg
; 32BIT-LABEL; liveins:
; 32BIT-LABEL: liveins:
; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' }
; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' }
; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }

4
llvm/test/CodeGen/PowerPC/vec_sldwi.ll
View File

@@ -105,7 +105,7 @@ entry:
%0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
ret <4 x i32> %0
; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_0
; CHECK-LE; vmr 2, 3
; CHECK-LE: vmr 2, 3
; CHECK-LE: blr
}
@@ -211,7 +211,7 @@ entry:
%0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
ret <4 x i32> %0
; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_0
; CHECK-LE; vmr 2, 3
; CHECK-LE: vmr 2, 3
; CHECK-BE: blr
}

2
llvm/test/CodeGen/X86/elf-associated-discarded.ll
View File

@@ -10,7 +10,7 @@
; CHECK: .section .data.b,"awo",@progbits,foo
;; No 'L' (SHF_LINK_ORDER). sh_link=0.
; SEC; Name {{.*}} Flg Lk Inf
; SEC: Name {{.*}} Flg Lk Inf
; SEC: .data.a {{.*}} WAL 0 0
; SEC: .data.b {{.*}} WAL 0 0

2
llvm/test/ExecutionEngine/OrcLazy/printargv.ll
View File

@@ -2,7 +2,7 @@
; CHECK: argc = 4
; CHECK-NEXT: argv = ["{{.*}}printargv.ll", "a", "b", "c"]
; CHECK-NEXT; argv[4] = null
; CHECK-NEXT: argv[4] = null
@.str = private unnamed_addr constant [11 x i8] c"argc = %i\0A\00", align 1
@.str.1 = private unnamed_addr constant [9 x i8] c"argv = [\00", align 1

2
llvm/test/Linker/scalable-vector-type-construction.ll
View File

@@ -1,7 +1,7 @@
; RUN: llvm-link %p/Inputs/fixed-vector-type-construction.ll %s -S -o - | FileCheck %s
%t = type {i32, float}
; CHECK: define void @foo(<4 x
; CHECK; define void @bar(<vscale x 4 x
; CHECK: define void @bar(<vscale x 4 x
define void @bar(<vscale x 4 x %t*> %x) {
ret void
}

2
llvm/test/MC/AMDGPU/vop3-convert.s
View File

@@ -49,7 +49,7 @@ v_ffbh_i32_e32 v1, v2
v_frexp_exp_i32_f64 v1, v[2:3]
// SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e]
// VI; v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
// VI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
v_frexp_mant_f64 v[1:2], v[2:3]
// SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e]

24
llvm/test/MC/Mips/macro-aliases.s
View File

@@ -4,32 +4,32 @@
# rendering the operand.
subu $4, $4, 4 # CHECK: ADDiu
# CHECK; Imm:-4
# CHECK: Imm:-4
subu $gp, $gp, 4 # CHECK: ADDiu
# CHECK; Imm:-4
# CHECK: Imm:-4
subu $sp, $sp, 4 # CHECK: ADDiu
# CHECK; Imm:-4
# CHECK: Imm:-4
subu $4, $4, -4 # CHECK: ADDiu
# CHECK; Imm:4
# CHECK: Imm:4
subu $gp, $gp, -4 # CHECK: ADDiu
# CHECK; Imm:4
# CHECK: Imm:4
subu $sp, $sp, -4 # CHECK: ADDiu
# CHECK; Imm:4
# CHECK: Imm:4
subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
# CHECK: Imm:8
subu $4, 8 # CHECK: ADDiu
# CHECK; Imm:-8
# CHECK: Imm:-8
subu $gp, 8 # CHECK: ADDiu
# CHECK; Imm:-8
# CHECK: Imm:-8
subu $sp, 8 # CHECK: ADDiu
# CHECK; Imm:-8
# CHECK: Imm:-8
subu $4, -8 # CHECK: ADDiu
# CHECK; Imm:8
# CHECK: Imm:8
subu $gp, -8 # CHECK: ADDiu
# CHECK; Imm:8
# CHECK: Imm:8
subu $sp, -8 # CHECK: ADDiu
# CHECK; Imm:8
# CHECK: Imm:8
subu $sp, -(4 + 4) # CHECK: ADDiu
# CHECK: Imm:8

2
llvm/test/MC/Mips/macro-drem.s
View File

@@ -186,7 +186,7 @@
# CHECK-TRAP: ddiv $zero, $5, $6 # encoding: [0x1e,0x00,0xa6,0x00]
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
# CHECK-TRAP: bne $6, $1, .Ltmp3 # encoding: [A,A,0xc1,0x14]
# CHECK-TRAP; # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0xfc,0x0f,0x01,0x00]
# CHECK-TRAP: teq $5, $1, 6 # encoding: [0xb4,0x01,0xa1,0x00]

2
llvm/test/Transforms/InstCombine/bitcast-store.ll
View File

@@ -35,7 +35,7 @@ entry:
; Check that we don't combine the bitcast into the store. This would create a
; bitcast of the swifterror which is invalid.
; CHECK-LABEL; @swifterror_store
; CHECK-LABEL: @swifterror_store
; CHECK: bitcast i64
; CHECK: store %swift.error

4
llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
View File

@@ -11,8 +11,8 @@ bb:
; CHECK-ALL: bb4
bb4:
; CHECK-INTERESTINGNESS; callbr void asm
; CHECK-INTERESTINGNESS-SAME; blockaddress
; CHECK-INTERESTINGNESS: callbr void asm
; CHECK-INTERESTINGNESS-SAME: blockaddress
; CHECK-FINAL: callbr void asm sideeffect "", "X"(i8* blockaddress(@func, %bb11))
; CHECK-ALL: to label %bb5 [label %bb11]
callbr void asm sideeffect "", "X"(i8* blockaddress(@func, %bb11))

4
polly/test/ScopInfo/scop-affine-parameter-ordering.ll
View File

@@ -8,8 +8,8 @@ target triple = "aarch64--linux-android"
; CHECK-NEXT: [p_0] -> { Stmt_for_body8_us_us95_i[i0] : 0 <= i0 <= 4 };
; CHECK-NEXT: Schedule :=
; CHECK-NEXT: [p_0] -> { Stmt_for_body8_us_us95_i[i0] -> [i0] };
; CHECK-NEXT; MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT; [p_0] -> { Stmt_for_body8_us_us95_i[i0] -> MemRef_0[1 + p_0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: [p_0] -> { Stmt_for_body8_us_us95_i[i0] -> MemRef_0[1 + p_0] };
; CHECK-NEXT }
define void @test1() unnamed_addr align 2 {