caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

SystemZ: Implement copyPhysReg between vr128 and gr128 (#90616)

Browse Source 
I have no idea if this is correct and I probably swapped the element
ordering somewhere.
This commit is contained in:
Matt Arsenault
2024-04-30 23:02:54 +02:00
committed by GitHub
parent 928db7e7ed
commit 75f4baa705
3 changed files with 173 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@@ -866,6 +866,31 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
}
if (SystemZ::GR128BitRegClass.contains(DestReg) &&
SystemZ::VR128BitRegClass.contains(SrcReg)) {
MCRegister DestH64 = RI.getSubReg(DestReg, SystemZ::subreg_h64);
MCRegister DestL64 = RI.getSubReg(DestReg, SystemZ::subreg_l64);
BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestH64)
.addReg(SrcReg)
.addReg(SystemZ::NoRegister)
.addImm(0)
.addDef(DestReg, RegState::Implicit);
BuildMI(MBB, MBBI, DL, get(SystemZ::VLGVG), DestL64)
.addReg(SrcReg, getKillRegState(KillSrc))
.addReg(SystemZ::NoRegister)
.addImm(1);
return;
}
if (SystemZ::VR128BitRegClass.contains(DestReg) &&
SystemZ::GR128BitRegClass.contains(SrcReg)) {
BuildMI(MBB, MBBI, DL, get(SystemZ::VLVGP), DestReg)
.addReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64))
.addReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64));
return;
}
// Everything else needs only one instruction.
unsigned Opcode;
if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))

78
llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-vr128.mir Normal file
View File

@@ -0,0 +1,78 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s
---
name: copy_gr128_to_vr128__r0q_to_v0
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0q
; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0
; CHECK: liveins: $r0q
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d
; CHECK-NEXT: Return implicit $v0
$v0 = COPY $r0q
Return implicit $v0
...
---
name: copy_gr128_to_vr128__r0q_to_v0_killed
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0q
; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_killed
; CHECK: liveins: $r0q
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d
; CHECK-NEXT: Return implicit $v0
$v0 = COPY killed $r0q
Return implicit $v0
...
---
name: copy_gr128_to_vr128__r0q_to_v0_undef
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0q
; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_undef
; CHECK: liveins: $r0q
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $v0 = KILL undef $r0q
; CHECK-NEXT: Return implicit $v0
$v0 = COPY undef $r0q
Return implicit $v0
...
---
name: copy_gr128_to_vr128__r0q_to_v0_subreg0
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0d
; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg0
; CHECK: liveins: $r0d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d
; CHECK-NEXT: Return implicit $v0
$v0 = COPY $r0q
Return implicit $v0
...
---
name: copy_gr128_to_vr128__r0q_to_v0_subreg1
tracksRegLiveness: true
body: |
bb.0:
liveins: $r1d
; CHECK-LABEL: name: copy_gr128_to_vr128__r0q_to_v0_subreg1
; CHECK: liveins: $r1d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $v0 = VLVGP $r0d, $r1d
; CHECK-NEXT: Return implicit $v0
$v0 = COPY $r0q
Return implicit $v0
...

70
llvm/test/CodeGen/SystemZ/copy-phys-reg-vr128-to-gr128.mir Normal file
View File

@@ -0,0 +1,70 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s
---
name: copy_vr128_to_gr128__v0_to_r0q
tracksRegLiveness: true
body: |
bb.0:
liveins: $v0
; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q
; CHECK: liveins: $v0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r0d = VLGVG $v0, $noreg, 0, implicit-def $r0q
; CHECK-NEXT: $r1d = VLGVG $v0, $noreg, 1
; CHECK-NEXT: Return implicit $r0q
$r0q = COPY $v0
Return implicit $r0q
...
---
name: copy_vr128_to_gr128__v0_to_r0q_killed
tracksRegLiveness: true
body: |
bb.0:
liveins: $v0
; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_killed
; CHECK: liveins: $v0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r0d = VLGVG $v0, $noreg, 0, implicit-def $r0q
; CHECK-NEXT: $r1d = VLGVG killed $v0, $noreg, 1
; CHECK-NEXT: Return implicit $r0q
$r0q = COPY killed $v0
Return implicit $r0q
...
---
name: copy_vr128_to_gr128__v0_to_r0q_undef
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef
; CHECK: $r0q = KILL undef $v0
; CHECK-NEXT: Return implicit $r0q
$r0q = COPY undef $v0
Return implicit $r0q
...
---
name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg0
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg0
; CHECK: $r0q = KILL undef $v0
; CHECK-NEXT: Return implicit $r0d
$r0q = COPY undef $v0
Return implicit $r0d
...
---
name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg1
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: copy_vr128_to_gr128__v0_to_r0q_undef_use_subreg1
; CHECK: $r0q = KILL undef $v0
; CHECK-NEXT: Return implicit $r1d
$r0q = COPY undef $v0
Return implicit $r1d
...