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[RISCV] Change input register type for QC_SWM and QC_SWMI (#144294)

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Version 0.13 of the `Xqci` spec changes the register type of input
operand `rs3` from `GPR` to `GPRNoX0` for these two instructions.

The spec can be found at
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0
This commit is contained in:
Sudharsan Veeravalli
2025-06-16 12:28:12 +05:30
committed by GitHub
parent f875efe1d8
commit 7d9a451d87
3 changed files with 18 additions and 9 deletions
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llvm/docs/RISCVUsage.rst
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@@ -487,7 +487,7 @@ The current vendor extensions supported are:
LLVM implements `version 0.3 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.11.0>`__ by Qualcomm. These instructions are only available for riscv32.
``experimental-Xqcilsm``
LLVM implements `version 0.5 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.11.0>`__ by Qualcomm. These instructions are only available for riscv32.
LLVM implements `version 0.6 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
``experimental-Xqcisim``
LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.11.0>`__ by Qualcomm. These instructions are only available for riscv32.