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[AArch64] Fix spillfill-sve.mir with expensive checks.

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This fixes an issue introduced by PR #70679.

Using constrainRegClass() is not strong enough to actually force
the use of a register to be a PPR register class. It will need an
actual COPY to do the conversion.

The downside is that this introduces an extra register, which is an
issue we may want to fix at a later point using a custom copy operation
where the register allocator uses the same register when it can.
This commit is contained in:
Sander de Smalen
2023-11-01 16:15:47 +00:00
parent 9220e0e647
commit 7dc20abed0
2 changed files with 22 additions and 9 deletions
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20
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@@ -4773,9 +4773,13 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
"Unexpected register store without SVE2p1 or SME2");
if (SrcReg.isVirtual())
MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::PPRRegClass);
else
if (SrcReg.isVirtual()) {
auto NewSrcReg =
MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg)
.addReg(SrcReg);
SrcReg = NewSrcReg;
} else
SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
Opc = AArch64::STR_PXI;
StackID = TargetStackID::ScalableVector;
@@ -4931,7 +4935,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned Opc = 0;
bool Offset = true;
unsigned StackID = TargetStackID::Default;
MCRegister PNRReg = MCRegister::NoRegister;
Register PNRReg = MCRegister::NoRegister;
switch (TRI->getSpillSize(*RC)) {
case 1:
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
@@ -4950,7 +4954,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
"Unexpected register load without SVE2p1 or SME2");
PNRReg = DestReg;
if (DestReg.isVirtual())
MF.getRegInfo().constrainRegClass(DestReg, &AArch64::PPRRegClass);
DestReg = MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
else
DestReg = (DestReg - AArch64::PN0) + AArch64::P0;
Opc = AArch64::LDR_PXI;
@@ -5061,9 +5065,13 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
.addFrameIndex(FI);
if (Offset)
MI.addImm(0);
if (PNRReg.isValid())
if (PNRReg.isValid() && !PNRReg.isVirtual())
MI.addDef(PNRReg, RegState::Implicit);
MI.addMemOperand(MMO);
if (PNRReg.isValid() && PNRReg.isVirtual())
BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), PNRReg)
.addReg(DestReg);
}
bool llvm::isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,

11
llvm/test/CodeGen/AArch64/spillfill-sve.mir
View File

@@ -121,8 +121,13 @@ body: |
; EXPAND-LABEL: name: spills_fills_stack_id_virtreg_pnr
; EXPAND: renamable $pn8 = WHILEGE_CXX_B
; EXPAND: STR_PXI killed renamable $pn8, $sp, 7
; EXPAND: $p0 = LDR_PXI $sp, 7, implicit-def $pn0
; EXPAND: $p0 = ORR_PPzPP $p8, $p8, killed $p8
; EXPAND: STR_PXI killed renamable $p0, $sp, 7
;
; EXPAND: renamable $p0 = LDR_PXI $sp, 7
; EXPAND: $p8 = ORR_PPzPP $p0, $p0, killed $p0, implicit-def $pn8
; EXPAND: $p0 = PEXT_PCI_B killed renamable $pn8, 0
%0:pnr_p8to15 = WHILEGE_CXX_B undef $x0, undef $x0, 0, implicit-def dead $nzcv
@@ -143,7 +148,7 @@ body: |
$pn14 = IMPLICIT_DEF
$pn15 = IMPLICIT_DEF
$pn0 = COPY %0
$p0 = PEXT_PCI_B %0, 0
RET_ReallyLR
...
---