From 7e830f76711f0dfc66780ea13cf780b8760b458b Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 1 Jul 2025 09:06:41 +0200 Subject: [PATCH] [Clang] Partially fix m68k alignments (#144740) As the data layout a few lines further up specifies, the int, long and pointer alignment should be 16 instead of the default of 32. The long long alignment is also incorrect, but that would require a change to the data layout as well. Comparison with GCC, which consistently uses 2 byte alignment: https://gcc.godbolt.org/z/K3x6a7dEf At least based on some spot checks, the changes to bit field layout also make use match GCC now. This was found by https://github.com/llvm/llvm-project/pull/144720. --- clang/lib/Basic/Targets/M68k.cpp | 1 + clang/test/CodeGen/bitfield-access-pad.c | 52 ++++++++++++++++++- .../test/CodeGenCXX/bitfield-access-empty.cpp | 22 +++++++- 3 files changed, 73 insertions(+), 2 deletions(-) diff --git a/clang/lib/Basic/Targets/M68k.cpp b/clang/lib/Basic/Targets/M68k.cpp index f0c77f027858..3988cb529456 100644 --- a/clang/lib/Basic/Targets/M68k.cpp +++ b/clang/lib/Basic/Targets/M68k.cpp @@ -56,6 +56,7 @@ M68kTargetInfo::M68kTargetInfo(const llvm::Triple &Triple, SizeType = UnsignedInt; PtrDiffType = SignedInt; IntPtrType = SignedInt; + IntAlign = LongAlign = PointerAlign = 16; } bool M68kTargetInfo::setCPU(const std::string &Name) { diff --git a/clang/test/CodeGen/bitfield-access-pad.c b/clang/test/CodeGen/bitfield-access-pad.c index 8608c5bd8be1..2044746118ad 100644 --- a/clang/test/CodeGen/bitfield-access-pad.c +++ b/clang/test/CodeGen/bitfield-access-pad.c @@ -18,7 +18,7 @@ // RUN: %clang_cc1 -triple=hexagon-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s // Big endian -// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s +// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-M68K %s // RUN: %clang_cc1 -triple=mips-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s // And now a few with -fno-bitfield-type-align. Precisely how this behaves is @@ -45,6 +45,7 @@ struct P1 { // CHECK-LABEL: LLVMType:%struct.P1 = // LAYOUT-T-SAME: type { i8, i8, [2 x i8] } // LAYOUT-ARM64-T-SAME: type { i8, i8 } +// LAYOUT-M68K-SAME: type { i8, i8 } // LAYOUT-NT-SAME: type { i8, i8 } // LAYOUT-STRICT-NT-SAME: type { i8, i8 } // LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] } @@ -60,6 +61,9 @@ struct P1 { // LAYOUT-ARM64-T-NEXT: struct P2 { @@ -68,6 +72,7 @@ struct P2 { // CHECK-LABEL: LLVMType:%struct.P2 = // LAYOUT-SAME: type { i16, i16 } // LAYOUT-DWN32-SAME: type { i16, i16 } +// LAYOUT-M68K-SAME: type { i16, i16 } // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P2 = // CHECK: BitFields:[ // LAYOUT-NEXT: struct P3 { @@ -85,6 +93,7 @@ struct P3 { // CHECK-LABEL: LLVMType:%struct.P3 = // LAYOUT-SAME: type { i16, [2 x i8], i16, [2 x i8] } // LAYOUT-DWN32-SAME: type <{ i16, i8, i16 }> +// LAYOUT-M68K-SAME: type <{ i16, i8, i16, i8 }> // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P3 = // CHECK: BitFields:[ // LAYOUT-NEXT: struct P4 { @@ -121,6 +133,7 @@ struct P6 { // CHECK-LABEL: LLVMType:%struct.P6 = // LAYOUT-SAME: type { i32, i32 } // LAYOUT-DWN32-SAME: type { i32, i32 } +// LAYOUT-M68K-SAME: type { i32, i32 } // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P6 = // CHECK: BitFields:[ // LAYOUT-NEXT: struct P7 { @@ -139,6 +155,7 @@ struct P7 { // CHECK-LABEL: LLVMType:%struct.P7 = // LAYOUT-SAME: type { i32, i32 } // LAYOUT-DWN32-SAME: type { i32, i32 } +// LAYOUT-M68K-SAME: type { i32, i32 } // CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P7 = // CHECK: BitFields:[ // LAYOUT-NEXT: