From 84ce59a0e4e47ff3ed3e9e7ea348a821735ea768 Mon Sep 17 00:00:00 2001 From: Lei Zhang Date: Mon, 9 Jan 2023 12:58:26 -0800 Subject: [PATCH] [mlir][spirv] Fix MLIR code snippet marker in TD files Reviewed By: kuhar Differential Revision: https://reviews.llvm.org/D141316 --- .../mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td | 8 +-- .../mlir/Dialect/SPIRV/IR/SPIRVCLOps.td | 42 ++++++++------- .../mlir/Dialect/SPIRV/IR/SPIRVCastOps.td | 4 -- .../Dialect/SPIRV/IR/SPIRVCompositeOps.td | 4 +- .../mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td | 52 +++++++++---------- .../mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td | 10 ++-- .../mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td | 9 ++-- .../mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td | 8 +-- .../mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td | 4 +- .../Dialect/SPIRV/IR/SPIRVNonUniformOps.td | 4 +- mlir/utils/spirv/gen_spirv_dialect.py | 4 +- 11 files changed, 73 insertions(+), 76 deletions(-) diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td index 4fa47ad7c08e..f2032e940d08 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td @@ -134,7 +134,7 @@ def SPIRV_AtomicCompareExchangeOp : SPIRV_Op<"AtomicCompareExchange", []> { `spirv.AtomicCompareExchange` scope memory-semantics memory-semantics ssa-use `,` ssa-use `,` ssa-use `:` spv-pointer-type - ```mlir + ``` #### Example: @@ -238,11 +238,11 @@ def SPIRV_AtomicExchangeOp : SPIRV_Op<"AtomicExchange", []> { atomic-exchange-op ::= `spirv.AtomicCompareExchange` scope memory-semantics ssa-use `,` ssa-use `:` spv-pointer-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.AtomicExchange "Workgroup" "Acquire" %pointer, %value, : !spirv.ptr ``` @@ -299,7 +299,7 @@ def SPIRV_EXTAtomicFAddOp : SPIRV_ExtVendorOp<"AtomicFAdd", []> { ```mlir %0 = spirv.EXT.AtomicFAdd "Device" "None" %pointer, %value : !spirv.ptr - ```mlir + ``` }]; let availability = [ diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td index 1e7ca2b97a0b..2561eca97c0c 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td @@ -133,11 +133,11 @@ def SPIRV_CLCeilOp : SPIRV_CLUnaryArithmeticOp<"ceil", 12, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` ceil-op ::= ssa-id `=` `spirv.CL.ceil` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.ceil %0 : f32 %3 = spirv.CL.ceil %1 : vector<3xf16> ``` @@ -163,11 +163,11 @@ def SPIRV_CLCosOp : SPIRV_CLUnaryArithmeticOp<"cos", 14, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` cos-op ::= ssa-id `=` `spirv.CL.cos` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.cos %0 : f32 %3 = spirv.CL.cos %1 : vector<3xf16> ``` @@ -195,11 +195,11 @@ def SPIRV_CLErfOp : SPIRV_CLUnaryArithmeticOp<"erf", 18, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` erf-op ::= ssa-id `=` `spirv.CL.erf` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.erf %0 : f32 %3 = spirv.CL.erf %1 : vector<3xf16> ``` @@ -288,11 +288,11 @@ def SPIRV_CLFloorOp : SPIRV_CLUnaryArithmeticOp<"floor", 25, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` floor-op ::= ssa-id `=` `spirv.CL.floor` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.floor %0 : f32 %3 = spirv.CL.ceifloorl %1 : vector<3xf16> ``` @@ -321,9 +321,11 @@ def SPIRV_CLFmaOp : SPIRV_CLTernaryArithmeticOp<"fma", 26, SPIRV_Float> { ``` fma-op ::= ssa-id `=` `spirv.CL.fma` ssa-use, ssa-use, ssa-use `:` float-scalar-vector-type - ```mlir - ``` + + #### Example: + + ```mlir %0 = spirv.CL.fma %a, %b, %c : f32 %1 = spirv.CL.fma %a, %b, %c : vector<3xf16> ``` @@ -410,11 +412,11 @@ def SPIRV_CLLogOp : SPIRV_CLUnaryArithmeticOp<"log", 37, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` log-op ::= ssa-id `=` `spirv.CL.log` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.log %0 : f32 %3 = spirv.CL.log %1 : vector<3xf16> ``` @@ -536,11 +538,11 @@ def SPIRV_CLRsqrtOp : SPIRV_CLUnaryArithmeticOp<"rsqrt", 56, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` rsqrt-op ::= ssa-id `=` `spirv.CL.rsqrt` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.rsqrt %0 : f32 %3 = spirv.CL.rsqrt %1 : vector<3xf16> ``` @@ -566,11 +568,11 @@ def SPIRV_CLSinOp : SPIRV_CLUnaryArithmeticOp<"sin", 57, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` sin-op ::= ssa-id `=` `spirv.CL.sin` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.sin %0 : f32 %3 = spirv.CL.sin %1 : vector<3xf16> ``` @@ -596,11 +598,11 @@ def SPIRV_CLSqrtOp : SPIRV_CLUnaryArithmeticOp<"sqrt", 61, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` sqrt-op ::= ssa-id `=` `spirv.CL.sqrt` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.sqrt %0 : f32 %3 = spirv.CL.sqrt %1 : vector<3xf16> ``` @@ -626,11 +628,11 @@ def SPIRV_CLTanhOp : SPIRV_CLUnaryArithmeticOp<"tanh", 63, SPIRV_Float> { `vector<` integer-literal `x` float-type `>` tanh-op ::= ssa-id `=` `spirv.CL.tanh` ssa-use `:` float-scalar-vector-type - ```mlir + ``` #### Example: - ``` + ```mlir %2 = spirv.CL.tanh %0 : f32 %3 = spirv.CL.tanh %1 : vector<3xf16> ``` diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td index 8975fa01df40..1c9eeab689e4 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td @@ -437,10 +437,6 @@ def SPIRV_GenericCastToPtrExplicitOp : SPIRV_Op<"GenericCastToPtrExplicit", [Pur - ``` - [TODO] - ```mlir - #### Example: ```mlir diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td index 7147e522cdd7..4feca83eee6b 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td @@ -258,11 +258,11 @@ def SPIRV_VectorInsertDynamicOp : SPIRV_Op<"VectorInsertDynamic", [ ssa-use `[` ssa-use `]` `:` `vector<` integer-literal `x` scalar-type `>` `,` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %scalar = ... : f32 %2 = spirv.VectorInsertDynamic %scalar %0[%1] : f32, vector<8xf32>, i32 ``` diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td index 0d2f416947c5..795d895933b8 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td @@ -47,11 +47,11 @@ def SPIRV_GroupFMulKHROp : SPIRV_KhrVendorOp<"GroupFMul", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.KHR.GroupFMul` scope operation ssa-use `:` float-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.KHR.GroupFMul %value : f32 ``` }]; @@ -117,11 +117,11 @@ def SPIRV_GroupBroadcastOp : SPIRV_Op<"GroupBroadcast", `vector<` integer-literal `x` integer-type `>` group-broadcast-op ::= ssa-id `=` `spirv.GroupBroadcast` scope ssa_use, ssa_use `:` integer-float-scalar-vector-type `,` localid-type - ```mlir + ``` #### Example: - ``` + ```mlir %scalar_value = ... : f32 %vector_value = ... : vector<4xf32> %scalar_localid = ... : i32 @@ -185,11 +185,11 @@ def SPIRV_GroupFAddOp : SPIRV_Op<"GroupFAdd", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupFAdd` scope operation ssa-use `:` float-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupFAdd %value : f32 ``` }]; @@ -247,11 +247,11 @@ def SPIRV_GroupFMaxOp : SPIRV_Op<"GroupFMax", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupFMax` scope operation ssa-use `:` float-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupFMax %value : f32 ``` }]; @@ -309,11 +309,11 @@ def SPIRV_GroupFMinOp : SPIRV_Op<"GroupFMin", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupFMin` scope operation ssa-use `:` float-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupFMin %value : f32 ``` }]; @@ -371,11 +371,11 @@ def SPIRV_GroupIAddOp : SPIRV_Op<"GroupIAdd", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupIAdd` scope operation ssa-use `:` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupIAdd %value : i32 ``` }]; @@ -434,11 +434,11 @@ def SPIRV_GroupIMulKHROp : SPIRV_KhrVendorOp<"GroupIMul", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.KHR.GroupIMul` scope operation ssa-use `:` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.KHR.GroupIMul %value : i32 ``` }]; @@ -497,11 +497,11 @@ def SPIRV_GroupSMaxOp : SPIRV_Op<"GroupSMax", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupSMax` scope operation ssa-use `:` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupSMax %value : i32 ``` }]; @@ -560,11 +560,11 @@ def SPIRV_GroupSMinOp : SPIRV_Op<"GroupSMin", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupSMin` scope operation ssa-use `:` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupSMin %value : i32 ``` }]; @@ -622,11 +622,11 @@ def SPIRV_GroupUMaxOp : SPIRV_Op<"GroupUMax", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupUMax` scope operation ssa-use `:` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupUMax %value : i32 ``` }]; @@ -685,11 +685,11 @@ def SPIRV_GroupUMinOp : SPIRV_Op<"GroupUMin", [Pure, operation ::= `"Reduce"` | `"InclusiveScan"` | `"ExclusiveScan"` op ::= ssa-id `=` `spirv.GroupUMin` scope operation ssa-use `:` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.GroupUMin %value : i32 ``` }]; @@ -742,11 +742,11 @@ def SPIRV_INTELSubgroupBlockReadOp : SPIRV_IntelVendorOp<"SubgroupBlockRead", [] ``` subgroup-block-read-INTEL-op ::= ssa-id `=` `spirv.INTEL.SubgroupBlockRead` storage-class ssa_use `:` spirv-element-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.INTEL.SubgroupBlockRead "StorageBuffer" %ptr : i32 ``` }]; @@ -792,11 +792,11 @@ def SPIRV_INTELSubgroupBlockWriteOp : SPIRV_IntelVendorOp<"SubgroupBlockWrite", ``` subgroup-block-write-INTEL-op ::= ssa-id `=` `spirv.INTEL.SubgroupBlockWrite` storage-class ssa_use `,` ssa-use `:` spirv-element-type - ```mlir + ``` #### Example: - ``` + ```mlir spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : i32 ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td index 93c9d75b45fe..02959ae9940e 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td @@ -788,11 +788,11 @@ def SPIRV_OrderedOp : SPIRV_LogicalBinaryOp<"Ordered", SPIRV_Float, [Commutative float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` ordered-op ::= ssa-id `=` `spirv.Ordered` ssa-use, ssa-use - ```mlir + ``` #### Example: - ``` + ```mlir %4 = spirv.Ordered %0, %1 : f32 %5 = spirv.Ordered %2, %3 : vector<4xf32> ``` @@ -870,7 +870,7 @@ def SPIRV_SGreaterThanEqualOp : SPIRV_LogicalBinaryOp<"SGreaterThanEqual", ``` #### Example: - ``` + ```mlir %4 = spirv.SGreaterThanEqual %0, %1 : i32 %5 = spirv.SGreaterThanEqual %2, %3 : vector<4xi32> @@ -1146,11 +1146,11 @@ def SPIRV_UnorderedOp : SPIRV_LogicalBinaryOp<"Unordered", SPIRV_Float, [Commuta float-scalar-vector-type ::= float-type | `vector<` integer-literal `x` float-type `>` unordered-op ::= ssa-id `=` `spirv.Unordered` ssa-use, ssa-use - ```mlir + ``` #### Example: - ``` + ```mlir %4 = spirv.Unordered %0, %1 : f32 %5 = spirv.Unordered %2, %3 : vector<4xf32> ``` diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td index b6b8c742dee4..a21fc0ce2f92 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td @@ -36,11 +36,11 @@ def SPIRV_MatrixTimesMatrixOp : SPIRV_Op<"MatrixTimesMatrix", [Pure]> { ``` matrix-times-matrix-op ::= ssa-id `=` `spirv.MatrixTimesMatrix` ssa-use, ssa-use `:` matrix-type `,` matrix-type `->` matrix-type - ```mlir + ``` #### Example: - ``` + ```mlir %0 = spirv.MatrixTimesMatrix %matrix_1, %matrix_2 : !spirv.matrix<4 x vector<3xf32>>, !spirv.matrix<3 x vector<4xf32>> -> !spirv.matrix<4 x vector<4xf32>> @@ -94,7 +94,6 @@ def SPIRV_MatrixTimesScalarOp : SPIRV_Op< #### Example: ```mlir - %0 = spirv.MatrixTimesScalar %matrix, %scalar : !spirv.matrix<3 x vector<3xf32>>, f32 -> !spirv.matrix<3 x vector<3xf32>> @@ -149,12 +148,12 @@ def SPIRV_TransposeOp : SPIRV_Op<"Transpose", [Pure]> { ``` transpose-op ::= ssa-id `=` `spirv.Transpose` ssa-use `:` matrix-type `->` matrix-type + ``` - ```mlir #### Example: - ``` + ```mlir %0 = spirv.Transpose %matrix: !spirv.matrix<2 x vector<3xf32>> -> !spirv.matrix<3 x vector<2xf32>> diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td index 925891dc6987..41cb4819ea38 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td @@ -147,11 +147,11 @@ def SPIRV_InBoundsPtrAccessChainOp : SPIRV_Op<"InBoundsPtrAccessChain", [Pure]> access-chain-op ::= ssa-id `=` `spirv.InBoundsPtrAccessChain` ssa-use `[` ssa-use (',' ssa-use)* `]` `:` pointer-type - ```mlir + ``` #### Example: - ``` + ```mlir func @inbounds_ptr_access_chain(%arg0: !spirv.ptr, %arg1 : i64) -> () { %0 = spirv.InBoundsPtrAccessChain %arg0[%arg1] : !spirv.ptr, i64 ... @@ -273,11 +273,11 @@ def SPIRV_PtrAccessChainOp : SPIRV_Op<"PtrAccessChain", [Pure]> { [access-chain-op ::= ssa-id `=` `spirv.PtrAccessChain` ssa-use `[` ssa-use (',' ssa-use)* `]` `:` pointer-type - ```mlir + ``` #### Example: - ``` + ```mlir func @ptr_access_chain(%arg0: !spirv.ptr, %arg1 : i64) -> () { %0 = spirv.PtrAccessChain %arg0[%arg1] : !spirv.ptr, i64 ... diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td index 702ad88bf720..f1d703151fe3 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td @@ -28,11 +28,11 @@ def SPIRV_KHRAssumeTrueOp : SPIRV_KhrVendorOp<"AssumeTrue", []> { ``` assumetruekhr-op ::= `spirv.KHR.AssumeTrue` ssa-use - ```mlir + ``` #### Example: - ``` + ```mlir spirv.KHR.AssumeTrue %arg ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td index 8e900bef63ea..df29b632f958 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td @@ -124,11 +124,11 @@ def SPIRV_GroupNonUniformBroadcastOp : SPIRV_Op<"GroupNonUniformBroadcast", group-non-uniform-broadcast-op ::= ssa-id `=` `spirv.GroupNonUniformBroadcast` scope ssa_use, ssa_use `:` integer-float-scalar-vector-type `,` integer-type - ```mlir + ``` #### Example: - ``` + ```mlir %scalar_value = ... : f32 %vector_value = ... : vector<4xf32> %id = ... : i32 diff --git a/mlir/utils/spirv/gen_spirv_dialect.py b/mlir/utils/spirv/gen_spirv_dialect.py index 94ab267ae311..aeb1827e7285 100755 --- a/mlir/utils/spirv/gen_spirv_dialect.py +++ b/mlir/utils/spirv/gen_spirv_dialect.py @@ -810,9 +810,9 @@ def get_op_definition(instruction, opname, doc, existing_info, capability_mappin if description is None: assembly = '\n ```\n'\ ' [TODO]\n'\ - ' ```mlir\n\n'\ + ' ```\n\n'\ ' #### Example:\n\n'\ - ' ```\n'\ + ' ```mlir\n'\ ' [TODO]\n' \ ' ```' description = get_description(text, assembly)