From 99b862efba9c2db5ec0aa32f62b5bc78df61d7a4 Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Wed, 4 Dec 2024 15:32:15 +0100 Subject: [PATCH] [DAGISel][ARM] Fix vector truncate combine for big-endian (#118101) This DAG combine was incorrect for big-endian targets, because it assumes that when a bitcast changes the lane width, the least-significant bits of the wider lanes are in the lower-numbered lanes of the smaller type, which is only true for little-endian. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +- llvm/test/CodeGen/ARM/vector-trunc.ll | 52 +++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/ARM/vector-trunc.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e78dd8cdf3e6..1aab0fce4e1e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15498,12 +15498,14 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { unsigned BuildVecNumElts = BuildVect.getNumOperands(); unsigned TruncVecNumElts = VT.getVectorNumElements(); unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts; + unsigned FirstElt = isLE ? 0 : (TruncEltOffset - 1); assert((BuildVecNumElts % TruncVecNumElts) == 0 && "Invalid number of elements"); SmallVector Opnds; - for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset) + for (unsigned i = FirstElt, e = BuildVecNumElts; i < e; + i += TruncEltOffset) Opnds.push_back(BuildVect.getOperand(i)); return DAG.getBuildVector(VT, DL, Opnds); diff --git a/llvm/test/CodeGen/ARM/vector-trunc.ll b/llvm/test/CodeGen/ARM/vector-trunc.ll new file mode 100644 index 000000000000..9acf463c2be9 --- /dev/null +++ b/llvm/test/CodeGen/ARM/vector-trunc.ll @@ -0,0 +1,52 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=armv7-unknown-none-eabihf -mattr=+neon < %s | FileCheck %s --check-prefix=LE +; RUN: llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon < %s | FileCheck %s --check-prefix=BE + +define i32 @test(i64 %arg1) { +; LE-LABEL: test: +; LE: @ %bb.0: @ %entry +; LE-NEXT: subs r0, r0, #1 +; LE-NEXT: mov r2, #0 +; LE-NEXT: sbcs r0, r1, #0 +; LE-NEXT: vldr s0, .LCPI0_0 +; LE-NEXT: movwhs r2, #1 +; LE-NEXT: cmp r2, #0 +; LE-NEXT: mvnne r2, #0 +; LE-NEXT: vmov s1, r2 +; LE-NEXT: vmovn.i32 d16, q0 +; LE-NEXT: vmovn.i16 d16, q8 +; LE-NEXT: vmov.u8 r0, d16[0] +; LE-NEXT: and r0, r0, #1 +; LE-NEXT: bx lr +; LE-NEXT: .p2align 2 +; LE-NEXT: @ %bb.1: +; LE-NEXT: .LCPI0_0: +; LE-NEXT: .long 0xffffffff @ float NaN +; +; BE-LABEL: test: +; BE: @ %bb.0: @ %entry +; BE-NEXT: subs r1, r1, #1 +; BE-NEXT: mov r2, #0 +; BE-NEXT: sbcs r0, r0, #0 +; BE-NEXT: vldr s0, .LCPI0_0 +; BE-NEXT: movwhs r2, #1 +; BE-NEXT: cmp r2, #0 +; BE-NEXT: mvnne r2, #0 +; BE-NEXT: vmov s1, r2 +; BE-NEXT: vmovn.i32 d16, q0 +; BE-NEXT: vmovn.i16 d16, q8 +; BE-NEXT: vmov.u8 r0, d16[0] +; BE-NEXT: and r0, r0, #1 +; BE-NEXT: bx lr +; BE-NEXT: .p2align 2 +; BE-NEXT: @ %bb.1: +; BE-NEXT: .LCPI0_0: +; BE-NEXT: .long 0xffffffff @ float NaN +entry: + %insert_zero = insertelement <8 x i64> poison, i64 %arg1, i64 0 + %splat_zero = shufflevector <8 x i64> %insert_zero, <8 x i64> poison, <8 x i32> zeroinitializer + %cmp_vec = icmp ule <8 x i64> , %splat_zero + %first_cmp = extractelement <8 x i1> %cmp_vec, i32 0 + %ext = zext i1 %first_cmp to i32 + ret i32 %ext +}