From 9c7e803f2d512f97cc3195c8a73539cedfef46cb Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Mon, 6 Jun 2022 15:50:10 +0300 Subject: [PATCH] [AMDGPU][GFX7][DOC][NFC] Update assembler syntax description Summary of changes: - Updated MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Enabled literals with src0 of v_madak_f32, v_madmk_f32 (see https://reviews.llvm.org/D111067). - Corrected LGKM_CNT description. - Minor bug fixing. --- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 2496 ++++++++--------- llvm/docs/AMDGPU/gfx7_hwreg.rst | 22 +- llvm/docs/AMDGPU/gfx7_imm16_2.rst | 13 - .../{gfx7_imm16.rst => gfx7_imm16_73139a.rst} | 2 +- ...gfx7_imm16_1.rst => gfx7_imm16_a04fb3.rst} | 2 +- llvm/docs/AMDGPU/gfx7_msg.rst | 32 +- llvm/docs/AMDGPU/gfx7_opt_0d447d.rst | 13 + .../{gfx7_opt.rst => gfx7_opt_847aed.rst} | 2 +- .../{gfx7_sbase.rst => gfx7_sbase_010ce0.rst} | 2 +- ...gfx7_sbase_1.rst => gfx7_sbase_382fdf.rst} | 2 +- .../{gfx7_sdst_3.rst => gfx7_sdst_0804b1.rst} | 2 +- .../{gfx7_sdst.rst => gfx7_sdst_2a1d2e.rst} | 2 +- .../{gfx7_sdst_1.rst => gfx7_sdst_313759.rst} | 2 +- .../{gfx7_sdst_4.rst => gfx7_sdst_362c37.rst} | 2 +- .../{gfx7_sdst_7.rst => gfx7_sdst_61ce79.rst} | 2 +- .../{gfx7_sdst_5.rst => gfx7_sdst_6cc8e9.rst} | 2 +- .../{gfx7_sdst_2.rst => gfx7_sdst_9172f3.rst} | 2 +- .../{gfx7_sdst_6.rst => gfx7_sdst_e3bd3f.rst} | 2 +- ...x7_simm32_1.rst => gfx7_simm32_6f0844.rst} | 4 +- ...gfx7_simm32.rst => gfx7_simm32_a3e80c.rst} | 2 +- ..._soffset_1.rst => gfx7_soffset_1bad09.rst} | 2 +- ...x7_soffset.rst => gfx7_soffset_48c95e.rst} | 2 +- .../{gfx7_src_2.rst => gfx7_src_1f730e.rst} | 2 +- .../{gfx7_src_7.rst => gfx7_src_3865f6.rst} | 2 +- .../{gfx7_src_9.rst => gfx7_src_3e3a6b.rst} | 2 +- .../{gfx7_src_3.rst => gfx7_src_516946.rst} | 2 +- .../{gfx7_src_4.rst => gfx7_src_5599b0.rst} | 2 +- .../{gfx7_src_10.rst => gfx7_src_5c4f8d.rst} | 2 +- .../{gfx7_src_6.rst => gfx7_src_8e54a0.rst} | 2 +- .../{gfx7_src_8.rst => gfx7_src_935f3b.rst} | 2 +- .../{gfx7_src_1.rst => gfx7_src_d48e27.rst} | 2 +- .../{gfx7_src_5.rst => gfx7_src_d56c56.rst} | 2 +- .../{gfx7_src.rst => gfx7_src_fa88a6.rst} | 2 +- .../{gfx7_srsrc.rst => gfx7_srsrc_cf7132.rst} | 2 +- ...gfx7_srsrc_1.rst => gfx7_srsrc_e73d16.rst} | 2 +- .../{gfx7_ssrc.rst => gfx7_ssrc_19a078.rst} | 2 +- .../{gfx7_ssrc_5.rst => gfx7_ssrc_2e8313.rst} | 2 +- .../{gfx7_ssrc_1.rst => gfx7_ssrc_6df989.rst} | 2 +- .../{gfx7_ssrc_8.rst => gfx7_ssrc_a778e3.rst} | 2 +- .../{gfx7_ssrc_6.rst => gfx7_ssrc_b0d552.rst} | 2 +- .../{gfx7_ssrc_4.rst => gfx7_ssrc_bdc010.rst} | 2 +- .../{gfx7_ssrc_7.rst => gfx7_ssrc_c5f5de.rst} | 2 +- ...{gfx7_ssrc_10.rst => gfx7_ssrc_d8712d.rst} | 2 +- .../{gfx7_ssrc_9.rst => gfx7_ssrc_dcdeb4.rst} | 2 +- .../{gfx7_ssrc_3.rst => gfx7_ssrc_e471f7.rst} | 2 +- .../{gfx7_ssrc_2.rst => gfx7_ssrc_fdbed3.rst} | 2 +- llvm/docs/AMDGPU/gfx7_tgt.rst | 18 +- ...gfx7_vaddr_1.rst => gfx7_vaddr_9f7133.rst} | 2 +- ...gfx7_vaddr_3.rst => gfx7_vaddr_da1f09.rst} | 2 +- ...gfx7_vaddr_2.rst => gfx7_vaddr_e9b690.rst} | 2 +- .../{gfx7_vaddr.rst => gfx7_vaddr_f20ee4.rst} | 2 +- ...gfx7_vdata0.rst => gfx7_vdata0_6802ce.rst} | 2 +- ...x7_vdata0_1.rst => gfx7_vdata0_fd235e.rst} | 2 +- ...gfx7_vdata1.rst => gfx7_vdata1_6802ce.rst} | 2 +- ...x7_vdata1_1.rst => gfx7_vdata1_fd235e.rst} | 2 +- ...gfx7_vdata_4.rst => gfx7_vdata_325b78.rst} | 2 +- ...gfx7_vdata_5.rst => gfx7_vdata_4d8ecf.rst} | 2 +- ...gfx7_vdata_3.rst => gfx7_vdata_56f215.rst} | 2 +- .../{gfx7_vdata.rst => gfx7_vdata_6802ce.rst} | 2 +- ...gfx7_vdata_9.rst => gfx7_vdata_87fb90.rst} | 2 +- ...gfx7_vdata_8.rst => gfx7_vdata_b2a787.rst} | 2 +- ...gfx7_vdata_6.rst => gfx7_vdata_c08393.rst} | 2 +- ...gfx7_vdata_7.rst => gfx7_vdata_c61803.rst} | 2 +- ...gfx7_vdata_2.rst => gfx7_vdata_e016a1.rst} | 2 +- ...gfx7_vdata_1.rst => gfx7_vdata_fd235e.rst} | 2 +- .../{gfx7_vdst_6.rst => gfx7_vdst_0c25a6.rst} | 2 +- .../{gfx7_vdst_7.rst => gfx7_vdst_3d7dcf.rst} | 2 +- .../{gfx7_vdst_5.rst => gfx7_vdst_463513.rst} | 2 +- .../{gfx7_vdst_3.rst => gfx7_vdst_48e42f.rst} | 2 +- .../{gfx7_vdst_8.rst => gfx7_vdst_5d50a1.rst} | 2 +- .../{gfx7_vdst_2.rst => gfx7_vdst_69a144.rst} | 2 +- ...{gfx7_vdst_12.rst => gfx7_vdst_875645.rst} | 4 +- .../{gfx7_vdst.rst => gfx7_vdst_89680f.rst} | 2 +- ...{gfx7_vdst_10.rst => gfx7_vdst_a49b76.rst} | 2 +- .../{gfx7_vdst_1.rst => gfx7_vdst_bdb32f.rst} | 2 +- .../{gfx7_vdst_4.rst => gfx7_vdst_d0dc43.rst} | 2 +- .../{gfx7_vdst_9.rst => gfx7_vdst_d7c57e.rst} | 2 +- ...{gfx7_vdst_11.rst => gfx7_vdst_f47754.rst} | 2 +- .../{gfx7_vsrc.rst => gfx7_vsrc_533a4e.rst} | 2 +- .../{gfx7_vsrc_1.rst => gfx7_vsrc_6802ce.rst} | 2 +- .../{gfx7_vsrc_2.rst => gfx7_vsrc_e016a1.rst} | 2 +- .../{gfx7_vsrc_3.rst => gfx7_vsrc_fd235e.rst} | 2 +- llvm/docs/AMDGPU/gfx7_waitcnt.rst | 2 +- 83 files changed, 1373 insertions(+), 1379 deletions(-) delete mode 100644 llvm/docs/AMDGPU/gfx7_imm16_2.rst rename llvm/docs/AMDGPU/{gfx7_imm16.rst => gfx7_imm16_73139a.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_imm16_1.rst => gfx7_imm16_a04fb3.rst} (92%) create mode 100644 llvm/docs/AMDGPU/gfx7_opt_0d447d.rst rename llvm/docs/AMDGPU/{gfx7_opt.rst => gfx7_opt_847aed.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_sbase.rst => gfx7_sbase_010ce0.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_sbase_1.rst => gfx7_sbase_382fdf.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_sdst_3.rst => gfx7_sdst_0804b1.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_sdst.rst => gfx7_sdst_2a1d2e.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_sdst_1.rst => gfx7_sdst_313759.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_sdst_4.rst => gfx7_sdst_362c37.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_sdst_7.rst => gfx7_sdst_61ce79.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_sdst_5.rst => gfx7_sdst_6cc8e9.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_sdst_2.rst => gfx7_sdst_9172f3.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_sdst_6.rst => gfx7_sdst_e3bd3f.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_simm32_1.rst => gfx7_simm32_6f0844.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_simm32.rst => gfx7_simm32_a3e80c.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_soffset_1.rst => gfx7_soffset_1bad09.rst} (96%) rename llvm/docs/AMDGPU/{gfx7_soffset.rst => gfx7_soffset_48c95e.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_src_2.rst => gfx7_src_1f730e.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_7.rst => gfx7_src_3865f6.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_9.rst => gfx7_src_3e3a6b.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_3.rst => gfx7_src_516946.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_src_4.rst => gfx7_src_5599b0.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_10.rst => gfx7_src_5c4f8d.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_6.rst => gfx7_src_8e54a0.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_8.rst => gfx7_src_935f3b.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_1.rst => gfx7_src_d48e27.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src_5.rst => gfx7_src_d56c56.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_src.rst => gfx7_src_fa88a6.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_srsrc.rst => gfx7_srsrc_cf7132.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_srsrc_1.rst => gfx7_srsrc_e73d16.rst} (92%) rename llvm/docs/AMDGPU/{gfx7_ssrc.rst => gfx7_ssrc_19a078.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_ssrc_5.rst => gfx7_ssrc_2e8313.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_ssrc_1.rst => gfx7_ssrc_6df989.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_ssrc_8.rst => gfx7_ssrc_a778e3.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_ssrc_6.rst => gfx7_ssrc_b0d552.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_ssrc_4.rst => gfx7_ssrc_bdc010.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_ssrc_7.rst => gfx7_ssrc_c5f5de.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_ssrc_10.rst => gfx7_ssrc_d8712d.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_ssrc_9.rst => gfx7_ssrc_dcdeb4.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_ssrc_3.rst => gfx7_ssrc_e471f7.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_ssrc_2.rst => gfx7_ssrc_fdbed3.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_vaddr_1.rst => gfx7_vaddr_9f7133.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vaddr_3.rst => gfx7_vaddr_da1f09.rst} (97%) rename llvm/docs/AMDGPU/{gfx7_vaddr_2.rst => gfx7_vaddr_e9b690.rst} (95%) rename llvm/docs/AMDGPU/{gfx7_vaddr.rst => gfx7_vaddr_f20ee4.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdata0.rst => gfx7_vdata0_6802ce.rst} (90%) rename llvm/docs/AMDGPU/{gfx7_vdata0_1.rst => gfx7_vdata0_fd235e.rst} (90%) rename llvm/docs/AMDGPU/{gfx7_vdata1.rst => gfx7_vdata1_6802ce.rst} (90%) rename llvm/docs/AMDGPU/{gfx7_vdata1_1.rst => gfx7_vdata1_fd235e.rst} (90%) rename llvm/docs/AMDGPU/{gfx7_vdata_4.rst => gfx7_vdata_325b78.rst} (96%) rename llvm/docs/AMDGPU/{gfx7_vdata_5.rst => gfx7_vdata_4d8ecf.rst} (96%) rename llvm/docs/AMDGPU/{gfx7_vdata_3.rst => gfx7_vdata_56f215.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdata.rst => gfx7_vdata_6802ce.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdata_9.rst => gfx7_vdata_87fb90.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_vdata_8.rst => gfx7_vdata_b2a787.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_vdata_6.rst => gfx7_vdata_c08393.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vdata_7.rst => gfx7_vdata_c61803.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_vdata_2.rst => gfx7_vdata_e016a1.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdata_1.rst => gfx7_vdata_fd235e.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdst_6.rst => gfx7_vdst_0c25a6.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vdst_7.rst => gfx7_vdst_3d7dcf.rst} (94%) rename llvm/docs/AMDGPU/{gfx7_vdst_5.rst => gfx7_vdst_463513.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vdst_3.rst => gfx7_vdst_48e42f.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdst_8.rst => gfx7_vdst_5d50a1.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vdst_2.rst => gfx7_vdst_69a144.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdst_12.rst => gfx7_vdst_875645.rst} (79%) rename llvm/docs/AMDGPU/{gfx7_vdst.rst => gfx7_vdst_89680f.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdst_10.rst => gfx7_vdst_a49b76.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vdst_1.rst => gfx7_vdst_bdb32f.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vdst_4.rst => gfx7_vdst_d0dc43.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vdst_9.rst => gfx7_vdst_d7c57e.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vdst_11.rst => gfx7_vdst_f47754.rst} (93%) rename llvm/docs/AMDGPU/{gfx7_vsrc.rst => gfx7_vsrc_533a4e.rst} (96%) rename llvm/docs/AMDGPU/{gfx7_vsrc_1.rst => gfx7_vsrc_6802ce.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vsrc_2.rst => gfx7_vsrc_e016a1.rst} (91%) rename llvm/docs/AMDGPU/{gfx7_vsrc_3.rst => gfx7_vsrc_fd235e.rst} (91%) diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst index 2456ce359fe7..355623c31335 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst @@ -32,578 +32,576 @@ Instructions DS ------------------------ +-- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_append :ref:`vdst` :ref:`offset` :ref:`gds` - ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` - ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` - ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` - ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` ds_gws_sema_p :ref:`offset` :ref:`gds` ds_gws_sema_release_all :ref:`offset` :ref:`gds` ds_gws_sema_v :ref:`offset` :ref:`gds` - ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` ds_nop - ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` - ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` EXP ------------------------ +--- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` + exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` FLAT ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`glc` :ref:`slc` - flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`glc` :ref:`slc` - flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` - flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` - flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` - flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` - flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` - flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` - flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` - flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` - flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` - flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` - flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` - flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` - flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`glc` :ref:`slc` + flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`glc` :ref:`slc` + flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`glc` :ref:`slc` + flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`glc` :ref:`slc` + flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` + flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` + flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`glc` :ref:`slc` + flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`glc` :ref:`slc` + flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` + flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` + flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`glc` :ref:`slc` + flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`glc` :ref:`slc` + flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`glc` :ref:`slc` + flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`glc` :ref:`slc` + flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`glc` :ref:`slc` + flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` + flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`glc` :ref:`slc` MIMG ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_fcmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_fmax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_fmin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_fcmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_fmax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_fmin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` MTBUF ------------------------ +----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` MUBUF ------------------------ +----- .. parsed-literal:: - **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dword :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_x :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_sbyte :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_sshort :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_ubyte :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_load_ushort :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` + buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`addr64` :ref:`offset12` :ref:`glc` :ref:`slc` buffer_wbinvl1 buffer_wbinvl1_vol SMRD ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` s_dcache_inv s_dcache_inv_vol - s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` - s_memtime :ref:`sdst`::ref:`b64` + s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` + s_memtime :ref:`sdst`::ref:`b64` SOP1 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_abs_i32 :ref:`sdst`, :ref:`ssrc` - s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_brev_b32 :ref:`sdst`, :ref:`ssrc` - s_brev_b64 :ref:`sdst`, :ref:`ssrc` - s_cbranch_join :ref:`ssrc` - s_cmov_b32 :ref:`sdst`, :ref:`ssrc` - s_cmov_b64 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` - s_getpc_b64 :ref:`sdst` - s_mov_b32 :ref:`sdst`, :ref:`ssrc` - s_mov_b64 :ref:`sdst`, :ref:`ssrc` - s_movreld_b32 :ref:`sdst`, :ref:`ssrc` - s_movreld_b64 :ref:`sdst`, :ref:`ssrc` - s_movrels_b32 :ref:`sdst`, :ref:`ssrc` - s_movrels_b64 :ref:`sdst`, :ref:`ssrc` - s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_not_b32 :ref:`sdst`, :ref:`ssrc` - s_not_b64 :ref:`sdst`, :ref:`ssrc` - s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` - s_rfe_b64 :ref:`ssrc` - s_setpc_b64 :ref:`ssrc` - s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` - s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` - s_swappc_b64 :ref:`sdst`, :ref:`ssrc` - s_wqm_b32 :ref:`sdst`, :ref:`ssrc` - s_wqm_b64 :ref:`sdst`, :ref:`ssrc` - s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_abs_i32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_brev_b32 :ref:`sdst`, :ref:`ssrc` + s_brev_b64 :ref:`sdst`, :ref:`ssrc` + s_cbranch_join :ref:`ssrc` + s_cmov_b32 :ref:`sdst`, :ref:`ssrc` + s_cmov_b64 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` + s_getpc_b64 :ref:`sdst` + s_mov_b32 :ref:`sdst`, :ref:`ssrc` + s_mov_b64 :ref:`sdst`, :ref:`ssrc` + s_movreld_b32 :ref:`sdst`, :ref:`ssrc` + s_movreld_b64 :ref:`sdst`, :ref:`ssrc` + s_movrels_b32 :ref:`sdst`, :ref:`ssrc` + s_movrels_b64 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_not_b32 :ref:`sdst`, :ref:`ssrc` + s_not_b64 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` + s_rfe_b64 :ref:`ssrc` + s_setpc_b64 :ref:`ssrc` + s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` + s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` + s_swappc_b64 :ref:`sdst`, :ref:`ssrc` + s_wqm_b32 :ref:`sdst`, :ref:`ssrc` + s_wqm_b64 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` SOP2 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` - s_cbranch_g_fork :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_cbranch_g_fork :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` SOPC ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_setvskip :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_setvskip :ref:`ssrc0`, :ref:`ssrc1` SOPK ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_addk_i32 :ref:`sdst`, :ref:`imm16` - s_cbranch_i_fork :ref:`ssrc`, :ref:`label` - s_cmovk_i32 :ref:`sdst`, :ref:`imm16` - s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` - s_getreg_b32 :ref:`sdst`, :ref:`hwreg` - s_movk_i32 :ref:`sdst`, :ref:`imm16` - s_mulk_i32 :ref:`sdst`, :ref:`imm16` - s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` - s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` + s_addk_i32 :ref:`sdst`, :ref:`imm16` + s_cbranch_i_fork :ref:`ssrc`, :ref:`label` + s_cmovk_i32 :ref:`sdst`, :ref:`imm16` + s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` + s_getreg_b32 :ref:`sdst`, :ref:`hwreg` + s_movk_i32 :ref:`sdst`, :ref:`imm16` + s_mulk_i32 :ref:`sdst`, :ref:`imm16` + s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` + s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` SOPP ------------------------ +---- .. parsed-literal:: @@ -621,736 +619,732 @@ SOPP s_cbranch_scc1 :ref:`label` s_cbranch_vccnz :ref:`label` s_cbranch_vccz :ref:`label` - s_decperflevel :ref:`imm16` + s_decperflevel :ref:`imm16` s_endpgm s_icache_inv - s_incperflevel :ref:`imm16` - s_nop :ref:`imm16` + s_incperflevel :ref:`imm16` + s_nop :ref:`imm16` s_sendmsg :ref:`msg` s_sendmsghalt :ref:`msg` - s_sethalt :ref:`imm16` - s_setkill :ref:`imm16` - s_setprio :ref:`imm16` - s_sleep :ref:`imm16` - s_trap :ref:`imm16` + s_sethalt :ref:`imm16` + s_setkill :ref:`imm16` + s_setprio :ref:`imm16` + s_sleep :ref:`imm16` + s_trap :ref:`imm16` s_ttracedata s_waitcnt :ref:`waitcnt` VINTRP ------------------------ +------ .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` - v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` - v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` + v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` VOP1 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_bfrev_b32 :ref:`vdst`, :ref:`src` - v_ceil_f32 :ref:`vdst`, :ref:`src` - v_ceil_f64 :ref:`vdst`, :ref:`src` + v_bfrev_b32 :ref:`vdst`, :ref:`src` + v_ceil_f32 :ref:`vdst`, :ref:`src` + v_ceil_f64 :ref:`vdst`, :ref:`src` v_clrexcp - v_cos_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_f32 :ref:`vdst`, :ref:`src` - v_cvt_f32_f16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f64 :ref:`vdst`, :ref:`src` - v_cvt_f32_i32 :ref:`vdst`, :ref:`src` - v_cvt_f32_u32 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` - v_cvt_f64_f32 :ref:`vdst`, :ref:`src` - v_cvt_f64_i32 :ref:`vdst`, :ref:`src` - v_cvt_f64_u32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f64 :ref:`vdst`, :ref:`src` - v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` - v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f64 :ref:`vdst`, :ref:`src` - v_exp_f32 :ref:`vdst`, :ref:`src` - v_exp_legacy_f32 :ref:`vdst`, :ref:`src` - v_ffbh_i32 :ref:`vdst`, :ref:`src` - v_ffbh_u32 :ref:`vdst`, :ref:`src` - v_ffbl_b32 :ref:`vdst`, :ref:`src` - v_floor_f32 :ref:`vdst`, :ref:`src` - v_floor_f64 :ref:`vdst`, :ref:`src` - v_fract_f32 :ref:`vdst`, :ref:`src` - v_fract_f64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f32 :ref:`vdst`, :ref:`src` - v_frexp_mant_f64 :ref:`vdst`, :ref:`src` - v_log_clamp_f32 :ref:`vdst`, :ref:`src` - v_log_f32 :ref:`vdst`, :ref:`src` - v_log_legacy_f32 :ref:`vdst`, :ref:`src` - v_mov_b32 :ref:`vdst`, :ref:`src` - v_movreld_b32 :ref:`vdst`, :ref:`src` - v_movrels_b32 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` + v_cos_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_f32 :ref:`vdst`, :ref:`src` + v_cvt_f32_f16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f64 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32 :ref:`vdst`, :ref:`src` + v_cvt_f32_u32 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` + v_cvt_f64_f32 :ref:`vdst`, :ref:`src` + v_cvt_f64_i32 :ref:`vdst`, :ref:`src` + v_cvt_f64_u32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f64 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` + v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f64 :ref:`vdst`, :ref:`src` + v_exp_f32 :ref:`vdst`, :ref:`src` + v_ffbh_i32 :ref:`vdst`, :ref:`src` + v_ffbh_u32 :ref:`vdst`, :ref:`src` + v_ffbl_b32 :ref:`vdst`, :ref:`src` + v_floor_f32 :ref:`vdst`, :ref:`src` + v_floor_f64 :ref:`vdst`, :ref:`src` + v_fract_f32 :ref:`vdst`, :ref:`src` + v_fract_f64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f32 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64 :ref:`vdst`, :ref:`src` + v_log_clamp_f32 :ref:`vdst`, :ref:`src` + v_log_f32 :ref:`vdst`, :ref:`src` + v_mov_b32 :ref:`vdst`, :ref:`src` + v_movreld_b32 :ref:`vdst`, :ref:`src` + v_movrels_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` v_nop - v_not_b32 :ref:`vdst`, :ref:`src` - v_rcp_clamp_f32 :ref:`vdst`, :ref:`src` - v_rcp_clamp_f64 :ref:`vdst`, :ref:`src` - v_rcp_f32 :ref:`vdst`, :ref:`src` - v_rcp_f64 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` - v_rcp_legacy_f32 :ref:`vdst`, :ref:`src` - v_readfirstlane_b32 :ref:`sdst`, :ref:`src` - v_rndne_f32 :ref:`vdst`, :ref:`src` - v_rndne_f64 :ref:`vdst`, :ref:`src` - v_rsq_clamp_f32 :ref:`vdst`, :ref:`src` - v_rsq_clamp_f64 :ref:`vdst`, :ref:`src` - v_rsq_f32 :ref:`vdst`, :ref:`src` - v_rsq_f64 :ref:`vdst`, :ref:`src` - v_rsq_legacy_f32 :ref:`vdst`, :ref:`src` - v_sin_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f64 :ref:`vdst`, :ref:`src` - v_trunc_f32 :ref:`vdst`, :ref:`src` - v_trunc_f64 :ref:`vdst`, :ref:`src` + v_not_b32 :ref:`vdst`, :ref:`src` + v_rcp_clamp_f32 :ref:`vdst`, :ref:`src` + v_rcp_clamp_f64 :ref:`vdst`, :ref:`src` + v_rcp_f32 :ref:`vdst`, :ref:`src` + v_rcp_f64 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` + v_rcp_legacy_f32 :ref:`vdst`, :ref:`src` + v_readfirstlane_b32 :ref:`sdst`, :ref:`src` + v_rndne_f32 :ref:`vdst`, :ref:`src` + v_rndne_f64 :ref:`vdst`, :ref:`src` + v_rsq_clamp_f32 :ref:`vdst`, :ref:`src` + v_rsq_clamp_f64 :ref:`vdst`, :ref:`src` + v_rsq_f32 :ref:`vdst`, :ref:`src` + v_rsq_f64 :ref:`vdst`, :ref:`src` + v_rsq_legacy_f32 :ref:`vdst`, :ref:`src` + v_sin_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f64 :ref:`vdst`, :ref:`src` + v_trunc_f32 :ref:`vdst`, :ref:`src` + v_trunc_f64 :ref:`vdst`, :ref:`src` VOP2 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_ashr_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` - v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`vsrc1`::ref:`i32` - v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1`::ref:`u32` - v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`u32` - v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` - v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i32` - v_lshl_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` - v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_lshr_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` - v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` - v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` - v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` - v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` - v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_ashr_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` + v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`vsrc1`::ref:`i32` + v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1`::ref:`u32` + v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`u32` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i32` + v_lshl_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` + v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_lshr_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`u32` + v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` + v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_i32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` VOP3 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_ashr_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_ashr_i64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_bcnt_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfm_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_ashr_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_ashr_i64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmps_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpsx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_pk_i16_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` - v_cvt_pk_u16_u32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` - v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pkaccum_u8_f32_e64 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` - v_cvt_pknorm_i16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pknorm_u16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` - v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` - v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ldexp_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_lshl_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshl_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshr_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshr_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` - v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` - v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` - v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_hi_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_lo_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mov_b32_e64 :ref:`vdst`, :ref:`src` - v_movreld_b32_e64 :ref:`vdst`, :ref:`src` - v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` - v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` - v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_lo_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmps_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpsx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_pk_i16_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` + v_cvt_pk_u16_u32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pkaccum_u8_f32_e64 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` + v_cvt_pknorm_i16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ldexp_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshl_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshl_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshr_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshr_b64 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_hi_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_movreld_b32_e64 :ref:`vdst`, :ref:`src` + v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_nop_e64 - v_not_b32_e64 :ref:`vdst`, :ref:`src` - v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` - v_rcp_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` - v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` - v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` + v_rcp_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_clamp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_clamp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_i32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOPC ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmps_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpsx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmps_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpsx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` .. |---| unicode:: U+02014 .. em dash @@ -1360,89 +1354,89 @@ VOPC gfx7_attr gfx7_dst gfx7_hwreg - gfx7_imm16 - gfx7_imm16_1 - gfx7_imm16_2 + gfx7_imm16_73139a + gfx7_imm16_a04fb3 gfx7_label gfx7_m gfx7_msg - gfx7_opt + gfx7_opt_0d447d + gfx7_opt_847aed gfx7_param - gfx7_sbase - gfx7_sbase_1 - gfx7_sdst - gfx7_sdst_1 - gfx7_sdst_2 - gfx7_sdst_3 - gfx7_sdst_4 - gfx7_sdst_5 - gfx7_sdst_6 - gfx7_sdst_7 - gfx7_simm32 - gfx7_simm32_1 - gfx7_soffset - gfx7_soffset_1 - gfx7_src - gfx7_src_1 - gfx7_src_10 - gfx7_src_2 - gfx7_src_3 - gfx7_src_4 - gfx7_src_5 - gfx7_src_6 - gfx7_src_7 - gfx7_src_8 - gfx7_src_9 - gfx7_srsrc - gfx7_srsrc_1 + gfx7_sbase_010ce0 + gfx7_sbase_382fdf + gfx7_sdst_0804b1 + gfx7_sdst_2a1d2e + gfx7_sdst_313759 + gfx7_sdst_362c37 + gfx7_sdst_61ce79 + gfx7_sdst_6cc8e9 + gfx7_sdst_9172f3 + gfx7_sdst_e3bd3f + gfx7_simm32_6f0844 + gfx7_simm32_a3e80c + gfx7_soffset_1bad09 + gfx7_soffset_48c95e + gfx7_src_1f730e + gfx7_src_3865f6 + gfx7_src_3e3a6b + gfx7_src_516946 + gfx7_src_5599b0 + gfx7_src_5c4f8d + gfx7_src_8e54a0 + gfx7_src_935f3b + gfx7_src_d48e27 + gfx7_src_d56c56 + gfx7_src_fa88a6 + gfx7_srsrc_cf7132 + gfx7_srsrc_e73d16 gfx7_ssamp - gfx7_ssrc - gfx7_ssrc_1 - gfx7_ssrc_10 - gfx7_ssrc_2 - gfx7_ssrc_3 - gfx7_ssrc_4 - gfx7_ssrc_5 - gfx7_ssrc_6 - gfx7_ssrc_7 - gfx7_ssrc_8 - gfx7_ssrc_9 + gfx7_ssrc_19a078 + gfx7_ssrc_2e8313 + gfx7_ssrc_6df989 + gfx7_ssrc_a778e3 + gfx7_ssrc_b0d552 + gfx7_ssrc_bdc010 + gfx7_ssrc_c5f5de + gfx7_ssrc_d8712d + gfx7_ssrc_dcdeb4 + gfx7_ssrc_e471f7 + gfx7_ssrc_fdbed3 gfx7_tgt gfx7_type_deviation - gfx7_vaddr - gfx7_vaddr_1 - gfx7_vaddr_2 - gfx7_vaddr_3 + gfx7_vaddr_9f7133 + gfx7_vaddr_da1f09 + gfx7_vaddr_e9b690 + gfx7_vaddr_f20ee4 gfx7_vcc - gfx7_vdata - gfx7_vdata0 - gfx7_vdata0_1 - gfx7_vdata1 - gfx7_vdata1_1 - gfx7_vdata_1 - gfx7_vdata_2 - gfx7_vdata_3 - gfx7_vdata_4 - gfx7_vdata_5 - gfx7_vdata_6 - gfx7_vdata_7 - gfx7_vdata_8 - gfx7_vdata_9 - gfx7_vdst - gfx7_vdst_1 - gfx7_vdst_10 - gfx7_vdst_11 - gfx7_vdst_12 - gfx7_vdst_2 - gfx7_vdst_3 - gfx7_vdst_4 - gfx7_vdst_5 - gfx7_vdst_6 - gfx7_vdst_7 - gfx7_vdst_8 - gfx7_vdst_9 - gfx7_vsrc - gfx7_vsrc_1 - gfx7_vsrc_2 - gfx7_vsrc_3 + gfx7_vdata0_6802ce + gfx7_vdata0_fd235e + gfx7_vdata1_6802ce + gfx7_vdata1_fd235e + gfx7_vdata_325b78 + gfx7_vdata_4d8ecf + gfx7_vdata_56f215 + gfx7_vdata_6802ce + gfx7_vdata_87fb90 + gfx7_vdata_b2a787 + gfx7_vdata_c08393 + gfx7_vdata_c61803 + gfx7_vdata_e016a1 + gfx7_vdata_fd235e + gfx7_vdst_0c25a6 + gfx7_vdst_3d7dcf + gfx7_vdst_463513 + gfx7_vdst_48e42f + gfx7_vdst_5d50a1 + gfx7_vdst_69a144 + gfx7_vdst_875645 + gfx7_vdst_89680f + gfx7_vdst_a49b76 + gfx7_vdst_bdb32f + gfx7_vdst_d0dc43 + gfx7_vdst_d7c57e + gfx7_vdst_f47754 + gfx7_vsrc_533a4e + gfx7_vsrc_6802ce + gfx7_vsrc_e016a1 + gfx7_vsrc_fd235e gfx7_waitcnt diff --git a/llvm/docs/AMDGPU/gfx7_hwreg.rst b/llvm/docs/AMDGPU/gfx7_hwreg.rst index 06e65cbf73b8..d36537653516 100644 --- a/llvm/docs/AMDGPU/gfx7_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx7_hwreg.rst @@ -41,17 +41,17 @@ or :ref:`absolute expressions`. Defined register *names* include: - =================== ========================================== - Name Description - =================== ========================================== - HW_REG_MODE Shader writeable mode bits. - HW_REG_STATUS Shader read-only status. - HW_REG_TRAPSTS Trap status. - HW_REG_HW_ID Id of wave, simd, compute unit, etc. - HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. - HW_REG_LDS_ALLOC Per-wave LDS allocation. - HW_REG_IB_STS Counters of outstanding instructions. - =================== ========================================== + ============================== ========================================== + Name Description + ============================== ========================================== + HW_REG_MODE Shader writeable mode bits. + HW_REG_STATUS Shader read-only status. + HW_REG_TRAPSTS Trap status. + HW_REG_HW_ID Id of wave, simd, compute unit, etc. + HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. + HW_REG_LDS_ALLOC Per-wave LDS allocation. + HW_REG_IB_STS Counters of outstanding instructions. + ============================== ========================================== Examples: diff --git a/llvm/docs/AMDGPU/gfx7_imm16_2.rst b/llvm/docs/AMDGPU/gfx7_imm16_2.rst deleted file mode 100644 index 6f69f65d826c..000000000000 --- a/llvm/docs/AMDGPU/gfx7_imm16_2.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid_gfx7_imm16_2: - -imm16 -===== - -A 16-bit :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx7_imm16.rst b/llvm/docs/AMDGPU/gfx7_imm16_73139a.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_imm16.rst rename to llvm/docs/AMDGPU/gfx7_imm16_73139a.rst index 93f34412616e..6b8eb6846267 100644 --- a/llvm/docs/AMDGPU/gfx7_imm16.rst +++ b/llvm/docs/AMDGPU/gfx7_imm16_73139a.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_imm16: +.. _amdgpu_synid_gfx7_imm16_73139a: imm16 ===== diff --git a/llvm/docs/AMDGPU/gfx7_imm16_1.rst b/llvm/docs/AMDGPU/gfx7_imm16_a04fb3.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_imm16_1.rst rename to llvm/docs/AMDGPU/gfx7_imm16_a04fb3.rst index 03eab3747795..0857c9caf2ab 100644 --- a/llvm/docs/AMDGPU/gfx7_imm16_1.rst +++ b/llvm/docs/AMDGPU/gfx7_imm16_a04fb3.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_imm16_1: +.. _amdgpu_synid_gfx7_imm16_a04fb3: imm16 ===== diff --git a/llvm/docs/AMDGPU/gfx7_msg.rst b/llvm/docs/AMDGPU/gfx7_msg.rst index 7f73a24a6e80..58db37680c49 100644 --- a/llvm/docs/AMDGPU/gfx7_msg.rst +++ b/llvm/docs/AMDGPU/gfx7_msg.rst @@ -47,22 +47,22 @@ or :ref:`absolute expressions`. Each message type supports specific operations: - ================= ========== ============================== ============ ========== - Message name Message Id Supported Operations Operation Id Stream Id - ================= ========== ============================== ============ ========== - MSG_INTERRUPT 1 \- \- \- - MSG_GS 2 GS_OP_CUT 1 Optional - \ GS_OP_EMIT 2 Optional - \ GS_OP_EMIT_CUT 3 Optional - MSG_GS_DONE 3 GS_OP_NOP 0 \- - \ GS_OP_CUT 1 Optional - \ GS_OP_EMIT 2 Optional - \ GS_OP_EMIT_CUT 3 Optional - MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \- - \ SYSMSG_OP_REG_RD 2 \- - \ SYSMSG_OP_HOST_TRAP_ACK 3 \- - \ SYSMSG_OP_TTRACE_PC 4 \- - ================= ========== ============================== ============ ========== + ====================== ========== ============================== ============ ========== + Message name Message Id Supported Operations Operation Id Stream Id + ====================== ========== ============================== ============ ========== + MSG_INTERRUPT 1 \- \- \- + MSG_GS 2 GS_OP_CUT 1 Optional + \ GS_OP_EMIT 2 Optional + \ GS_OP_EMIT_CUT 3 Optional + MSG_GS_DONE 3 GS_OP_NOP 0 \- + \ GS_OP_CUT 1 Optional + \ GS_OP_EMIT 2 Optional + \ GS_OP_EMIT_CUT 3 Optional + MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \- + \ SYSMSG_OP_REG_RD 2 \- + \ SYSMSG_OP_HOST_TRAP_ACK 3 \- + \ SYSMSG_OP_TTRACE_PC 4 \- + ====================== ========== ============================== ============ ========== *Sendmsg* arguments are validated depending on how *type* value is specified: diff --git a/llvm/docs/AMDGPU/gfx7_opt_0d447d.rst b/llvm/docs/AMDGPU/gfx7_opt_0d447d.rst new file mode 100644 index 000000000000..4d347b9f2198 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx7_opt_0d447d.rst @@ -0,0 +1,13 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx7_opt_0d447d: + +opt +=== + +This is an optional operand. It must be used if and only if :ref:`lds` is omitted. diff --git a/llvm/docs/AMDGPU/gfx7_opt.rst b/llvm/docs/AMDGPU/gfx7_opt_847aed.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_opt.rst rename to llvm/docs/AMDGPU/gfx7_opt_847aed.rst index 68fa73531f12..fc59c46f47e6 100644 --- a/llvm/docs/AMDGPU/gfx7_opt.rst +++ b/llvm/docs/AMDGPU/gfx7_opt_847aed.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_opt: +.. _amdgpu_synid_gfx7_opt_847aed: opt === diff --git a/llvm/docs/AMDGPU/gfx7_sbase.rst b/llvm/docs/AMDGPU/gfx7_sbase_010ce0.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_sbase.rst rename to llvm/docs/AMDGPU/gfx7_sbase_010ce0.rst index d945b6755ac1..338f2dcab9a9 100644 --- a/llvm/docs/AMDGPU/gfx7_sbase.rst +++ b/llvm/docs/AMDGPU/gfx7_sbase_010ce0.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sbase: +.. _amdgpu_synid_gfx7_sbase_010ce0: sbase ===== diff --git a/llvm/docs/AMDGPU/gfx7_sbase_1.rst b/llvm/docs/AMDGPU/gfx7_sbase_382fdf.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_sbase_1.rst rename to llvm/docs/AMDGPU/gfx7_sbase_382fdf.rst index 4b40f0063244..94bacc4e0de0 100644 --- a/llvm/docs/AMDGPU/gfx7_sbase_1.rst +++ b/llvm/docs/AMDGPU/gfx7_sbase_382fdf.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sbase_1: +.. _amdgpu_synid_gfx7_sbase_382fdf: sbase ===== diff --git a/llvm/docs/AMDGPU/gfx7_sdst_3.rst b/llvm/docs/AMDGPU/gfx7_sdst_0804b1.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_sdst_3.rst rename to llvm/docs/AMDGPU/gfx7_sdst_0804b1.rst index e621ec41a75b..63e32af6bf62 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst_3.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_0804b1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst_3: +.. _amdgpu_synid_gfx7_sdst_0804b1: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_sdst.rst b/llvm/docs/AMDGPU/gfx7_sdst_2a1d2e.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_sdst.rst rename to llvm/docs/AMDGPU/gfx7_sdst_2a1d2e.rst index 088ff959b18e..a07350440f0d 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_2a1d2e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst: +.. _amdgpu_synid_gfx7_sdst_2a1d2e: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_sdst_1.rst b/llvm/docs/AMDGPU/gfx7_sdst_313759.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_sdst_1.rst rename to llvm/docs/AMDGPU/gfx7_sdst_313759.rst index 82b0454680fb..194459cab724 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst_1.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_313759.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst_1: +.. _amdgpu_synid_gfx7_sdst_313759: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_sdst_4.rst b/llvm/docs/AMDGPU/gfx7_sdst_362c37.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_sdst_4.rst rename to llvm/docs/AMDGPU/gfx7_sdst_362c37.rst index ab37adfa92f4..6a0c944a31e2 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst_4.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_362c37.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst_4: +.. _amdgpu_synid_gfx7_sdst_362c37: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_sdst_7.rst b/llvm/docs/AMDGPU/gfx7_sdst_61ce79.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_sdst_7.rst rename to llvm/docs/AMDGPU/gfx7_sdst_61ce79.rst index 20455beaccc5..d0dd37d36d7a 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst_7.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_61ce79.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst_7: +.. _amdgpu_synid_gfx7_sdst_61ce79: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_sdst_5.rst b/llvm/docs/AMDGPU/gfx7_sdst_6cc8e9.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_sdst_5.rst rename to llvm/docs/AMDGPU/gfx7_sdst_6cc8e9.rst index afa7d4322420..976bc0ed4583 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst_5.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_6cc8e9.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst_5: +.. _amdgpu_synid_gfx7_sdst_6cc8e9: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_sdst_2.rst b/llvm/docs/AMDGPU/gfx7_sdst_9172f3.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_sdst_2.rst rename to llvm/docs/AMDGPU/gfx7_sdst_9172f3.rst index cdf6029e77ba..63f0e9b47664 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst_2.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_9172f3.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst_2: +.. _amdgpu_synid_gfx7_sdst_9172f3: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_sdst_6.rst b/llvm/docs/AMDGPU/gfx7_sdst_e3bd3f.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_sdst_6.rst rename to llvm/docs/AMDGPU/gfx7_sdst_e3bd3f.rst index 5fe3d5950b8c..ceebdd419829 100644 --- a/llvm/docs/AMDGPU/gfx7_sdst_6.rst +++ b/llvm/docs/AMDGPU/gfx7_sdst_e3bd3f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_sdst_6: +.. _amdgpu_synid_gfx7_sdst_e3bd3f: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_simm32_1.rst b/llvm/docs/AMDGPU/gfx7_simm32_6f0844.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_simm32_1.rst rename to llvm/docs/AMDGPU/gfx7_simm32_6f0844.rst index bf25074104c9..192175ba6ed8 100644 --- a/llvm/docs/AMDGPU/gfx7_simm32_1.rst +++ b/llvm/docs/AMDGPU/gfx7_simm32_6f0844.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_simm32_1: +.. _amdgpu_synid_gfx7_simm32_6f0844: simm32 ====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. -The value is converted to *f32* as described :ref:`here`. +The value is converted to *f32* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx7_simm32.rst b/llvm/docs/AMDGPU/gfx7_simm32_a3e80c.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_simm32.rst rename to llvm/docs/AMDGPU/gfx7_simm32_a3e80c.rst index 885d77fa0bbb..dfb6849cd9db 100644 --- a/llvm/docs/AMDGPU/gfx7_simm32.rst +++ b/llvm/docs/AMDGPU/gfx7_simm32_a3e80c.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_simm32: +.. _amdgpu_synid_gfx7_simm32_a3e80c: simm32 ====== diff --git a/llvm/docs/AMDGPU/gfx7_soffset_1.rst b/llvm/docs/AMDGPU/gfx7_soffset_1bad09.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx7_soffset_1.rst rename to llvm/docs/AMDGPU/gfx7_soffset_1bad09.rst index 6899bb0b8003..929cbf18450c 100644 --- a/llvm/docs/AMDGPU/gfx7_soffset_1.rst +++ b/llvm/docs/AMDGPU/gfx7_soffset_1bad09.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_soffset_1: +.. _amdgpu_synid_gfx7_soffset_1bad09: soffset ======= diff --git a/llvm/docs/AMDGPU/gfx7_soffset.rst b/llvm/docs/AMDGPU/gfx7_soffset_48c95e.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_soffset.rst rename to llvm/docs/AMDGPU/gfx7_soffset_48c95e.rst index b8c24a5b5be8..47260e27bf9d 100644 --- a/llvm/docs/AMDGPU/gfx7_soffset.rst +++ b/llvm/docs/AMDGPU/gfx7_soffset_48c95e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_soffset: +.. _amdgpu_synid_gfx7_soffset_48c95e: soffset ======= diff --git a/llvm/docs/AMDGPU/gfx7_src_2.rst b/llvm/docs/AMDGPU/gfx7_src_1f730e.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_2.rst rename to llvm/docs/AMDGPU/gfx7_src_1f730e.rst index 58cdec53bcbe..47f2fece3747 100644 --- a/llvm/docs/AMDGPU/gfx7_src_2.rst +++ b/llvm/docs/AMDGPU/gfx7_src_1f730e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_2: +.. _amdgpu_synid_gfx7_src_1f730e: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_7.rst b/llvm/docs/AMDGPU/gfx7_src_3865f6.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_7.rst rename to llvm/docs/AMDGPU/gfx7_src_3865f6.rst index 2087805a2e2e..364449a4eafa 100644 --- a/llvm/docs/AMDGPU/gfx7_src_7.rst +++ b/llvm/docs/AMDGPU/gfx7_src_3865f6.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_7: +.. _amdgpu_synid_gfx7_src_3865f6: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_9.rst b/llvm/docs/AMDGPU/gfx7_src_3e3a6b.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_9.rst rename to llvm/docs/AMDGPU/gfx7_src_3e3a6b.rst index d47c69e94f34..8a8ef9899fc3 100644 --- a/llvm/docs/AMDGPU/gfx7_src_9.rst +++ b/llvm/docs/AMDGPU/gfx7_src_3e3a6b.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_9: +.. _amdgpu_synid_gfx7_src_3e3a6b: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_3.rst b/llvm/docs/AMDGPU/gfx7_src_516946.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_src_3.rst rename to llvm/docs/AMDGPU/gfx7_src_516946.rst index 6d1593c64b97..55c8522419d9 100644 --- a/llvm/docs/AMDGPU/gfx7_src_3.rst +++ b/llvm/docs/AMDGPU/gfx7_src_516946.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_3: +.. _amdgpu_synid_gfx7_src_516946: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_4.rst b/llvm/docs/AMDGPU/gfx7_src_5599b0.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_4.rst rename to llvm/docs/AMDGPU/gfx7_src_5599b0.rst index 9dc4da37aa07..23bf7ce273bb 100644 --- a/llvm/docs/AMDGPU/gfx7_src_4.rst +++ b/llvm/docs/AMDGPU/gfx7_src_5599b0.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_4: +.. _amdgpu_synid_gfx7_src_5599b0: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_10.rst b/llvm/docs/AMDGPU/gfx7_src_5c4f8d.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_10.rst rename to llvm/docs/AMDGPU/gfx7_src_5c4f8d.rst index 4d02fd9f66a6..5cf20abfaaf9 100644 --- a/llvm/docs/AMDGPU/gfx7_src_10.rst +++ b/llvm/docs/AMDGPU/gfx7_src_5c4f8d.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_10: +.. _amdgpu_synid_gfx7_src_5c4f8d: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_6.rst b/llvm/docs/AMDGPU/gfx7_src_8e54a0.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_6.rst rename to llvm/docs/AMDGPU/gfx7_src_8e54a0.rst index 8c81e4c27cfa..a56658ac9d04 100644 --- a/llvm/docs/AMDGPU/gfx7_src_6.rst +++ b/llvm/docs/AMDGPU/gfx7_src_8e54a0.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_6: +.. _amdgpu_synid_gfx7_src_8e54a0: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_8.rst b/llvm/docs/AMDGPU/gfx7_src_935f3b.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_8.rst rename to llvm/docs/AMDGPU/gfx7_src_935f3b.rst index 20cc4ab92a4a..a62e5ee2e0e0 100644 --- a/llvm/docs/AMDGPU/gfx7_src_8.rst +++ b/llvm/docs/AMDGPU/gfx7_src_935f3b.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_8: +.. _amdgpu_synid_gfx7_src_935f3b: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_1.rst b/llvm/docs/AMDGPU/gfx7_src_d48e27.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_1.rst rename to llvm/docs/AMDGPU/gfx7_src_d48e27.rst index dfe7971f0cb4..25b339c7f707 100644 --- a/llvm/docs/AMDGPU/gfx7_src_1.rst +++ b/llvm/docs/AMDGPU/gfx7_src_d48e27.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_1: +.. _amdgpu_synid_gfx7_src_d48e27: src === diff --git a/llvm/docs/AMDGPU/gfx7_src_5.rst b/llvm/docs/AMDGPU/gfx7_src_d56c56.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src_5.rst rename to llvm/docs/AMDGPU/gfx7_src_d56c56.rst index 2b0160614911..e1a7799901a2 100644 --- a/llvm/docs/AMDGPU/gfx7_src_5.rst +++ b/llvm/docs/AMDGPU/gfx7_src_d56c56.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src_5: +.. _amdgpu_synid_gfx7_src_d56c56: src === diff --git a/llvm/docs/AMDGPU/gfx7_src.rst b/llvm/docs/AMDGPU/gfx7_src_fa88a6.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_src.rst rename to llvm/docs/AMDGPU/gfx7_src_fa88a6.rst index eccbf6b712df..a943e2bdee7f 100644 --- a/llvm/docs/AMDGPU/gfx7_src.rst +++ b/llvm/docs/AMDGPU/gfx7_src_fa88a6.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_src: +.. _amdgpu_synid_gfx7_src_fa88a6: src === diff --git a/llvm/docs/AMDGPU/gfx7_srsrc.rst b/llvm/docs/AMDGPU/gfx7_srsrc_cf7132.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_srsrc.rst rename to llvm/docs/AMDGPU/gfx7_srsrc_cf7132.rst index 6579e0343f22..6cf10fc77203 100644 --- a/llvm/docs/AMDGPU/gfx7_srsrc.rst +++ b/llvm/docs/AMDGPU/gfx7_srsrc_cf7132.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_srsrc: +.. _amdgpu_synid_gfx7_srsrc_cf7132: srsrc ===== diff --git a/llvm/docs/AMDGPU/gfx7_srsrc_1.rst b/llvm/docs/AMDGPU/gfx7_srsrc_e73d16.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx7_srsrc_1.rst rename to llvm/docs/AMDGPU/gfx7_srsrc_e73d16.rst index 6a365c3b6f65..eccb5d2ed6c1 100644 --- a/llvm/docs/AMDGPU/gfx7_srsrc_1.rst +++ b/llvm/docs/AMDGPU/gfx7_srsrc_e73d16.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_srsrc_1: +.. _amdgpu_synid_gfx7_srsrc_e73d16: srsrc ===== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc.rst b/llvm/docs/AMDGPU/gfx7_ssrc_19a078.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_ssrc.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_19a078.rst index d06a69b5ab91..f24ca2ecdcc6 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_19a078.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc: +.. _amdgpu_synid_gfx7_ssrc_19a078: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_5.rst b/llvm/docs/AMDGPU/gfx7_ssrc_2e8313.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_ssrc_5.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_2e8313.rst index 09a9a3516d84..75d8602d1d50 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_5.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_2e8313.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_5: +.. _amdgpu_synid_gfx7_ssrc_2e8313: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_1.rst b/llvm/docs/AMDGPU/gfx7_ssrc_6df989.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_ssrc_1.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_6df989.rst index 51e92de67671..b42ed89a3576 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_1.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_6df989.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_1: +.. _amdgpu_synid_gfx7_ssrc_6df989: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_8.rst b/llvm/docs/AMDGPU/gfx7_ssrc_a778e3.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_ssrc_8.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_a778e3.rst index ff277d502ed7..747620a1c9b2 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_8.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_a778e3.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_8: +.. _amdgpu_synid_gfx7_ssrc_a778e3: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_6.rst b/llvm/docs/AMDGPU/gfx7_ssrc_b0d552.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_ssrc_6.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_b0d552.rst index 48371b757b7a..1e9e48888788 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_6.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_b0d552.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_6: +.. _amdgpu_synid_gfx7_ssrc_b0d552: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_4.rst b/llvm/docs/AMDGPU/gfx7_ssrc_bdc010.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_ssrc_4.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_bdc010.rst index 65ffe4ea7285..b72b79e84133 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_4.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_bdc010.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_4: +.. _amdgpu_synid_gfx7_ssrc_bdc010: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_7.rst b/llvm/docs/AMDGPU/gfx7_ssrc_c5f5de.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_ssrc_7.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_c5f5de.rst index 5070fae33bbe..ddbef6904d65 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_7.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_c5f5de.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_7: +.. _amdgpu_synid_gfx7_ssrc_c5f5de: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_10.rst b/llvm/docs/AMDGPU/gfx7_ssrc_d8712d.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_ssrc_10.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_d8712d.rst index cbd9ad6494cf..8c4f4873edfe 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_10.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_d8712d.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_10: +.. _amdgpu_synid_gfx7_ssrc_d8712d: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_9.rst b/llvm/docs/AMDGPU/gfx7_ssrc_dcdeb4.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_ssrc_9.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_dcdeb4.rst index 5c3d3454a39e..4c784a2792ef 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_9.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_dcdeb4.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_9: +.. _amdgpu_synid_gfx7_ssrc_dcdeb4: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_3.rst b/llvm/docs/AMDGPU/gfx7_ssrc_e471f7.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_ssrc_3.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_e471f7.rst index 5ac692aadc81..773d8be8fe8d 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_3.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_e471f7.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_3: +.. _amdgpu_synid_gfx7_ssrc_e471f7: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_ssrc_2.rst b/llvm/docs/AMDGPU/gfx7_ssrc_fdbed3.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_ssrc_2.rst rename to llvm/docs/AMDGPU/gfx7_ssrc_fdbed3.rst index c0e6cb9b952b..532236dd0abb 100644 --- a/llvm/docs/AMDGPU/gfx7_ssrc_2.rst +++ b/llvm/docs/AMDGPU/gfx7_ssrc_fdbed3.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_ssrc_2: +.. _amdgpu_synid_gfx7_ssrc_fdbed3: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_tgt.rst b/llvm/docs/AMDGPU/gfx7_tgt.rst index 2aaf928a1fb9..a8ae43f51243 100644 --- a/llvm/docs/AMDGPU/gfx7_tgt.rst +++ b/llvm/docs/AMDGPU/gfx7_tgt.rst @@ -12,12 +12,12 @@ tgt An export target: - ============== =================================== - Syntax Description - ============== =================================== - pos{0..3} Copy vertex position 0..3. - param{0..31} Copy vertex parameter 0..31. - mrt{0..7} Copy pixel color to the MRTs 0..7. - mrtz Copy pixel depth (Z) data. - null Copy nothing. - ============== =================================== + ================== =================================== + Syntax Description + ================== =================================== + pos{0..3} Copy vertex position 0..3. + param{0..31} Copy vertex parameter 0..31. + mrt{0..7} Copy pixel color to the MRTs 0..7. + mrtz Copy pixel depth (Z) data. + null Copy nothing. + ================== =================================== diff --git a/llvm/docs/AMDGPU/gfx7_vaddr_1.rst b/llvm/docs/AMDGPU/gfx7_vaddr_9f7133.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vaddr_1.rst rename to llvm/docs/AMDGPU/gfx7_vaddr_9f7133.rst index 6cae555658e4..c4bb2c13409c 100644 --- a/llvm/docs/AMDGPU/gfx7_vaddr_1.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr_9f7133.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vaddr_1: +.. _amdgpu_synid_gfx7_vaddr_9f7133: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx7_vaddr_3.rst b/llvm/docs/AMDGPU/gfx7_vaddr_da1f09.rst similarity index 97% rename from llvm/docs/AMDGPU/gfx7_vaddr_3.rst rename to llvm/docs/AMDGPU/gfx7_vaddr_da1f09.rst index f2721b69139f..e3dbce17b96a 100644 --- a/llvm/docs/AMDGPU/gfx7_vaddr_3.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr_da1f09.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vaddr_3: +.. _amdgpu_synid_gfx7_vaddr_da1f09: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx7_vaddr_2.rst b/llvm/docs/AMDGPU/gfx7_vaddr_e9b690.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx7_vaddr_2.rst rename to llvm/docs/AMDGPU/gfx7_vaddr_e9b690.rst index e537a86cecdd..3c6ec6d75167 100644 --- a/llvm/docs/AMDGPU/gfx7_vaddr_2.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr_e9b690.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vaddr_2: +.. _amdgpu_synid_gfx7_vaddr_e9b690: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx7_vaddr.rst b/llvm/docs/AMDGPU/gfx7_vaddr_f20ee4.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vaddr.rst rename to llvm/docs/AMDGPU/gfx7_vaddr_f20ee4.rst index 849fdc6be3f2..34d84ea9dce8 100644 --- a/llvm/docs/AMDGPU/gfx7_vaddr.rst +++ b/llvm/docs/AMDGPU/gfx7_vaddr_f20ee4.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vaddr: +.. _amdgpu_synid_gfx7_vaddr_f20ee4: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata0.rst b/llvm/docs/AMDGPU/gfx7_vdata0_6802ce.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_vdata0.rst rename to llvm/docs/AMDGPU/gfx7_vdata0_6802ce.rst index 42d41a7ad5c7..d9217e300726 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata0.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata0_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata0: +.. _amdgpu_synid_gfx7_vdata0_6802ce: vdata0 ====== diff --git a/llvm/docs/AMDGPU/gfx7_vdata0_1.rst b/llvm/docs/AMDGPU/gfx7_vdata0_fd235e.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_vdata0_1.rst rename to llvm/docs/AMDGPU/gfx7_vdata0_fd235e.rst index 3f4320bb3ef4..3e219aff26b9 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata0_1.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata0_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata0_1: +.. _amdgpu_synid_gfx7_vdata0_fd235e: vdata0 ====== diff --git a/llvm/docs/AMDGPU/gfx7_vdata1.rst b/llvm/docs/AMDGPU/gfx7_vdata1_6802ce.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_vdata1.rst rename to llvm/docs/AMDGPU/gfx7_vdata1_6802ce.rst index 19feb6123cd9..3e528da90267 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata1.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata1_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata1: +.. _amdgpu_synid_gfx7_vdata1_6802ce: vdata1 ====== diff --git a/llvm/docs/AMDGPU/gfx7_vdata1_1.rst b/llvm/docs/AMDGPU/gfx7_vdata1_fd235e.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx7_vdata1_1.rst rename to llvm/docs/AMDGPU/gfx7_vdata1_fd235e.rst index b0c8a73626e0..604e45bef49b 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata1_1.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata1_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata1_1: +.. _amdgpu_synid_gfx7_vdata1_fd235e: vdata1 ====== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_4.rst b/llvm/docs/AMDGPU/gfx7_vdata_325b78.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx7_vdata_4.rst rename to llvm/docs/AMDGPU/gfx7_vdata_325b78.rst index 99cb0406dd40..225ea408f554 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_4.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_325b78.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_4: +.. _amdgpu_synid_gfx7_vdata_325b78: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_5.rst b/llvm/docs/AMDGPU/gfx7_vdata_4d8ecf.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx7_vdata_5.rst rename to llvm/docs/AMDGPU/gfx7_vdata_4d8ecf.rst index e5288b96ef5d..944f1861e6f7 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_5.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_4d8ecf.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_5: +.. _amdgpu_synid_gfx7_vdata_4d8ecf: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_3.rst b/llvm/docs/AMDGPU/gfx7_vdata_56f215.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdata_3.rst rename to llvm/docs/AMDGPU/gfx7_vdata_56f215.rst index 2126739309bb..efc1f00d41e3 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_3.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_56f215.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_3: +.. _amdgpu_synid_gfx7_vdata_56f215: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata.rst b/llvm/docs/AMDGPU/gfx7_vdata_6802ce.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdata.rst rename to llvm/docs/AMDGPU/gfx7_vdata_6802ce.rst index 617ee2a75cef..06b556d0a357 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata: +.. _amdgpu_synid_gfx7_vdata_6802ce: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_9.rst b/llvm/docs/AMDGPU/gfx7_vdata_87fb90.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_vdata_9.rst rename to llvm/docs/AMDGPU/gfx7_vdata_87fb90.rst index aa395f203097..489860be7ef2 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_9.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_87fb90.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_9: +.. _amdgpu_synid_gfx7_vdata_87fb90: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_8.rst b/llvm/docs/AMDGPU/gfx7_vdata_b2a787.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_vdata_8.rst rename to llvm/docs/AMDGPU/gfx7_vdata_b2a787.rst index b555bf5782a5..fca927c1f221 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_8.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_b2a787.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_8: +.. _amdgpu_synid_gfx7_vdata_b2a787: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_6.rst b/llvm/docs/AMDGPU/gfx7_vdata_c08393.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdata_6.rst rename to llvm/docs/AMDGPU/gfx7_vdata_c08393.rst index 33837702f178..45a9ae878532 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_6.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_c08393.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_6: +.. _amdgpu_synid_gfx7_vdata_c08393: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_7.rst b/llvm/docs/AMDGPU/gfx7_vdata_c61803.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_vdata_7.rst rename to llvm/docs/AMDGPU/gfx7_vdata_c61803.rst index ef156bca7125..7842b8e66a4c 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_7.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_c61803.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_7: +.. _amdgpu_synid_gfx7_vdata_c61803: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_2.rst b/llvm/docs/AMDGPU/gfx7_vdata_e016a1.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdata_2.rst rename to llvm/docs/AMDGPU/gfx7_vdata_e016a1.rst index 922d7f5f96cc..2233c27d215e 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_2.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_e016a1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_2: +.. _amdgpu_synid_gfx7_vdata_e016a1: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdata_1.rst b/llvm/docs/AMDGPU/gfx7_vdata_fd235e.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdata_1.rst rename to llvm/docs/AMDGPU/gfx7_vdata_fd235e.rst index dd16f9c54c1d..5d97359f2b75 100644 --- a/llvm/docs/AMDGPU/gfx7_vdata_1.rst +++ b/llvm/docs/AMDGPU/gfx7_vdata_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdata_1: +.. _amdgpu_synid_gfx7_vdata_fd235e: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_6.rst b/llvm/docs/AMDGPU/gfx7_vdst_0c25a6.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdst_6.rst rename to llvm/docs/AMDGPU/gfx7_vdst_0c25a6.rst index 2fa85a24e39d..284b247211fe 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_6.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_0c25a6.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_6: +.. _amdgpu_synid_gfx7_vdst_0c25a6: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_7.rst b/llvm/docs/AMDGPU/gfx7_vdst_3d7dcf.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx7_vdst_7.rst rename to llvm/docs/AMDGPU/gfx7_vdst_3d7dcf.rst index 7d36d7701812..07338f34c6bb 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_7.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_3d7dcf.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_7: +.. _amdgpu_synid_gfx7_vdst_3d7dcf: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_5.rst b/llvm/docs/AMDGPU/gfx7_vdst_463513.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdst_5.rst rename to llvm/docs/AMDGPU/gfx7_vdst_463513.rst index b57b2f7ba2d9..1a0d50e02f61 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_5.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_463513.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_5: +.. _amdgpu_synid_gfx7_vdst_463513: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_3.rst b/llvm/docs/AMDGPU/gfx7_vdst_48e42f.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdst_3.rst rename to llvm/docs/AMDGPU/gfx7_vdst_48e42f.rst index 65810a36797d..8f10048b32b0 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_3.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_48e42f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_3: +.. _amdgpu_synid_gfx7_vdst_48e42f: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_8.rst b/llvm/docs/AMDGPU/gfx7_vdst_5d50a1.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdst_8.rst rename to llvm/docs/AMDGPU/gfx7_vdst_5d50a1.rst index b3361d99ffd7..c6dc1704cbb2 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_8.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_5d50a1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_8: +.. _amdgpu_synid_gfx7_vdst_5d50a1: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_2.rst b/llvm/docs/AMDGPU/gfx7_vdst_69a144.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdst_2.rst rename to llvm/docs/AMDGPU/gfx7_vdst_69a144.rst index 8a4206129c81..45fafa765d35 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_2.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_69a144.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_2: +.. _amdgpu_synid_gfx7_vdst_69a144: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_12.rst b/llvm/docs/AMDGPU/gfx7_vdst_875645.rst similarity index 79% rename from llvm/docs/AMDGPU/gfx7_vdst_12.rst rename to llvm/docs/AMDGPU/gfx7_vdst_875645.rst index 2f8473800f50..e6b006345202 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_12.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_875645.rst @@ -5,14 +5,14 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_12: +.. _amdgpu_synid_gfx7_vdst_875645: vdst ==== Instruction output: data read from a memory buffer. -If :ref:`lds` is specified, this operand is ignored by H/W and data are stored directly into LDS. +This is an optional operand. It must be used if and only if :ref:`lds` is omitted. *Size:* 1 dword by default. :ref:`tfe` adds 1 dword if specified. diff --git a/llvm/docs/AMDGPU/gfx7_vdst.rst b/llvm/docs/AMDGPU/gfx7_vdst_89680f.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdst.rst rename to llvm/docs/AMDGPU/gfx7_vdst_89680f.rst index ec98a49afe0f..3ebf612ce964 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_89680f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst: +.. _amdgpu_synid_gfx7_vdst_89680f: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_10.rst b/llvm/docs/AMDGPU/gfx7_vdst_a49b76.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdst_10.rst rename to llvm/docs/AMDGPU/gfx7_vdst_a49b76.rst index 320d0d0c9849..f9e77ad967c2 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_10.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_a49b76.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_10: +.. _amdgpu_synid_gfx7_vdst_a49b76: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_1.rst b/llvm/docs/AMDGPU/gfx7_vdst_bdb32f.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vdst_1.rst rename to llvm/docs/AMDGPU/gfx7_vdst_bdb32f.rst index 4a3b1c7c0241..028e9ab6c15a 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_1.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_bdb32f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_1: +.. _amdgpu_synid_gfx7_vdst_bdb32f: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_4.rst b/llvm/docs/AMDGPU/gfx7_vdst_d0dc43.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdst_4.rst rename to llvm/docs/AMDGPU/gfx7_vdst_d0dc43.rst index 4aebd9230eec..9c967c7d6106 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_4.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_d0dc43.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_4: +.. _amdgpu_synid_gfx7_vdst_d0dc43: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_9.rst b/llvm/docs/AMDGPU/gfx7_vdst_d7c57e.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdst_9.rst rename to llvm/docs/AMDGPU/gfx7_vdst_d7c57e.rst index 6e036fce65f4..34821c84879f 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_9.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_d7c57e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_9: +.. _amdgpu_synid_gfx7_vdst_d7c57e: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vdst_11.rst b/llvm/docs/AMDGPU/gfx7_vdst_f47754.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx7_vdst_11.rst rename to llvm/docs/AMDGPU/gfx7_vdst_f47754.rst index 3f40c25958ac..225e40df5ef6 100644 --- a/llvm/docs/AMDGPU/gfx7_vdst_11.rst +++ b/llvm/docs/AMDGPU/gfx7_vdst_f47754.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vdst_11: +.. _amdgpu_synid_gfx7_vdst_f47754: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx7_vsrc.rst b/llvm/docs/AMDGPU/gfx7_vsrc_533a4e.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx7_vsrc.rst rename to llvm/docs/AMDGPU/gfx7_vsrc_533a4e.rst index 98e79945379f..8008b886f95d 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc_533a4e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vsrc: +.. _amdgpu_synid_gfx7_vsrc_533a4e: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_vsrc_1.rst b/llvm/docs/AMDGPU/gfx7_vsrc_6802ce.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vsrc_1.rst rename to llvm/docs/AMDGPU/gfx7_vsrc_6802ce.rst index f8ed78a4ccb4..ca8a9a0a51a0 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc_1.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vsrc_1: +.. _amdgpu_synid_gfx7_vsrc_6802ce: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_vsrc_2.rst b/llvm/docs/AMDGPU/gfx7_vsrc_e016a1.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vsrc_2.rst rename to llvm/docs/AMDGPU/gfx7_vsrc_e016a1.rst index 77887d65f102..421804e33117 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc_2.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc_e016a1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vsrc_2: +.. _amdgpu_synid_gfx7_vsrc_e016a1: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_vsrc_3.rst b/llvm/docs/AMDGPU/gfx7_vsrc_fd235e.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx7_vsrc_3.rst rename to llvm/docs/AMDGPU/gfx7_vsrc_fd235e.rst index 8a4533e4cd27..f4926364805f 100644 --- a/llvm/docs/AMDGPU/gfx7_vsrc_3.rst +++ b/llvm/docs/AMDGPU/gfx7_vsrc_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx7_vsrc_3: +.. _amdgpu_synid_gfx7_vsrc_fd235e: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx7_waitcnt.rst b/llvm/docs/AMDGPU/gfx7_waitcnt.rst index 3913770b2b84..03253d7d8208 100644 --- a/llvm/docs/AMDGPU/gfx7_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx7_waitcnt.rst @@ -19,7 +19,7 @@ The bits of this operand have the following meaning: ===== ================================================ ============ 3:0 VM_CNT: vector memory operations count. 0..15 6:4 EXP_CNT: export count. 0..7 - 12:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..31 + 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15 ===== ================================================ ============ This operand may be specified as one of the following: