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[x86] use SETCC_CARRY instead of SBB node for select lowering

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This is a suggested follow-up to D116765.
This removes a clear of the register operand, so it is better
for code size, but it does potentially create a false register
dependency on surrounding code. If that is a problem, it should
be solvable using dependency-breaking code that is used for
other instructions.

Differential Revision: https://reviews.llvm.org/D116804
This commit is contained in:
Sanjay Patel
2022-01-07 13:35:59 -05:00
parent 80e2c58749
commit aab1f55e33
6 changed files with 151 additions and 102 deletions
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16
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@@ -24552,8 +24552,6 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
} else if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
(CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
SDVTList CmpVTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
// 'X - 1' sets the carry flag if X == 0.
@@ -24563,18 +24561,18 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
// select (X == 0), Y, -1 --> 0 - X; or (sbb), Y
// select (X != 0), Y, -1 --> X - 1; or (sbb), Y
// select (X == 0), -1, Y --> X - 1; or (sbb), Y
SDValue Sub;
if (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE)) {
SDValue Zero = DAG.getConstant(0, DL, CmpOp0.getValueType());
Cmp = DAG.getNode(X86ISD::SUB, DL, CmpVTs, Zero, CmpOp0);
Sub = DAG.getNode(X86ISD::SUB, DL, CmpVTs, Zero, CmpOp0);
} else {
SDValue One = DAG.getConstant(1, DL, CmpOp0.getValueType());
Cmp = DAG.getNode(X86ISD::SUB, DL, CmpVTs, CmpOp0, One);
Sub = DAG.getNode(X86ISD::SUB, DL, CmpVTs, CmpOp0, One);
}
// TODO: We don't need "0 - 0" here. This should use X86ISD::SETCC_CARRY.
SDValue Zero = DAG.getConstant(0, DL, Op.getValueType());
SDValue Res = // Res = 0 or -1.
DAG.getNode(X86ISD::SBB, DL, VTs, Zero, Zero, Cmp.getValue(1));
return DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
SDValue SBB = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
DAG.getTargetConstant(X86::COND_B, DL, MVT::i8),
Sub.getValue(1));
return DAG.getNode(ISD::OR, DL, VT, SBB, Y);
} else if (!Subtarget.hasCMov() && CondCode == X86::COND_E &&
Cmp.getOperand(0).getOpcode() == ISD::AND &&
isOneConstant(Cmp.getOperand(0).getOperand(1))) {

1
llvm/test/CodeGen/X86/pr35972.ll
View File

@@ -5,7 +5,6 @@ define void @test3(i32 %c, <64 x i1>* %ptr) {
; CHECK-LABEL: test3:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: sbbl %ecx, %ecx
; CHECK-NEXT: kmovd %ecx, %k0

4
llvm/test/CodeGen/X86/sdiv_fix_sat.ll
View File

@@ -1219,7 +1219,6 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: andl %eax, %ebx
; X86-NEXT: negl %eax
; X86-NEXT: movl $0, %ecx
; X86-NEXT: sbbl %ecx, %ecx
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
@@ -1243,7 +1242,6 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: andl %eax, %edi
; X86-NEXT: negl %eax
; X86-NEXT: movl $0, %eax
; X86-NEXT: sbbl %eax, %eax
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -1270,7 +1268,6 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: andl %eax, %edx
; X86-NEXT: negl %eax
; X86-NEXT: movl $0, %eax
; X86-NEXT: sbbl %eax, %eax
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
@@ -1294,7 +1291,6 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: andl %eax, %edi
; X86-NEXT: negl %eax
; X86-NEXT: movl $0, %eax
; X86-NEXT: sbbl %eax, %eax
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload

199
llvm/test/CodeGen/X86/select.ll
View File

@@ -629,13 +629,21 @@ define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2)
;; Test integer select between values and constants.
define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone {
; CHECK-LABEL: test9:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: retq
; GENERIC-LABEL: test9:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: cmpq $1, %rdi
; GENERIC-NEXT: sbbq %rax, %rax
; GENERIC-NEXT: orq %rsi, %rax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: test9:
; ATOM: ## %bb.0:
; ATOM-NEXT: cmpq $1, %rdi
; ATOM-NEXT: sbbq %rax, %rax
; ATOM-NEXT: orq %rsi, %rax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: test9:
; ATHLON: ## %bb.0:
@@ -669,13 +677,21 @@ define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone {
;; Same as test9
define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
; CHECK-LABEL: test9a:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: retq
; GENERIC-LABEL: test9a:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: cmpq $1, %rdi
; GENERIC-NEXT: sbbq %rax, %rax
; GENERIC-NEXT: orq %rsi, %rax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: test9a:
; ATOM: ## %bb.0:
; ATOM-NEXT: cmpq $1, %rdi
; ATOM-NEXT: sbbq %rax, %rax
; ATOM-NEXT: orq %rsi, %rax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: test9a:
; ATHLON: ## %bb.0:
@@ -790,13 +806,21 @@ define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone {
}
define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone {
; CHECK-LABEL: test11:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: negq %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: retq
; GENERIC-LABEL: test11:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: negq %rdi
; GENERIC-NEXT: sbbq %rax, %rax
; GENERIC-NEXT: orq %rsi, %rax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: test11:
; ATOM: ## %bb.0:
; ATOM-NEXT: negq %rdi
; ATOM-NEXT: sbbq %rax, %rax
; ATOM-NEXT: orq %rsi, %rax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: test11:
; ATHLON: ## %bb.0:
@@ -829,13 +853,21 @@ define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone {
}
define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
; CHECK-LABEL: test11a:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: negq %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: retq
; GENERIC-LABEL: test11a:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: negq %rdi
; GENERIC-NEXT: sbbq %rax, %rax
; GENERIC-NEXT: orq %rsi, %rax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: test11a:
; ATOM: ## %bb.0:
; ATOM-NEXT: negq %rdi
; ATOM-NEXT: sbbq %rax, %rax
; ATOM-NEXT: orq %rsi, %rax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: test11a:
; ATHLON: ## %bb.0:
@@ -867,13 +899,21 @@ define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
}
define i32 @eqzero_const_or_all_ones(i32 %x) {
; CHECK-LABEL: eqzero_const_or_all_ones:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: negl %edi
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: orl $42, %eax
; CHECK-NEXT: retq
; GENERIC-LABEL: eqzero_const_or_all_ones:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: negl %edi
; GENERIC-NEXT: sbbl %eax, %eax
; GENERIC-NEXT: orl $42, %eax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: eqzero_const_or_all_ones:
; ATOM: ## %bb.0:
; ATOM-NEXT: negl %edi
; ATOM-NEXT: sbbl %eax, %eax
; ATOM-NEXT: orl $42, %eax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: eqzero_const_or_all_ones:
; ATHLON: ## %bb.0:
@@ -885,11 +925,9 @@ define i32 @eqzero_const_or_all_ones(i32 %x) {
;
; MCU-LABEL: eqzero_const_or_all_ones:
; MCU: # %bb.0:
; MCU-NEXT: xorl %ecx, %ecx
; MCU-NEXT: negl %eax
; MCU-NEXT: sbbl %ecx, %ecx
; MCU-NEXT: orl $42, %ecx
; MCU-NEXT: movl %ecx, %eax
; MCU-NEXT: sbbl %eax, %eax
; MCU-NEXT: orl $42, %eax
; MCU-NEXT: retl
%z = icmp eq i32 %x, 0
%r = select i1 %z, i32 42, i32 -1
@@ -897,17 +935,24 @@ define i32 @eqzero_const_or_all_ones(i32 %x) {
}
define i32 @nezero_const_or_all_ones(i32 %x) {
; CHECK-LABEL: nezero_const_or_all_ones:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpl $1, %edi
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: orl $42, %eax
; CHECK-NEXT: retq
; GENERIC-LABEL: nezero_const_or_all_ones:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: cmpl $1, %edi
; GENERIC-NEXT: sbbl %eax, %eax
; GENERIC-NEXT: orl $42, %eax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: nezero_const_or_all_ones:
; ATOM: ## %bb.0:
; ATOM-NEXT: cmpl $1, %edi
; ATOM-NEXT: sbbl %eax, %eax
; ATOM-NEXT: orl $42, %eax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: nezero_const_or_all_ones:
; ATHLON: ## %bb.0:
; ATHLON-NEXT: xorl %eax, %eax
; ATHLON-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; ATHLON-NEXT: sbbl %eax, %eax
; ATHLON-NEXT: orl $42, %eax
@@ -915,11 +960,9 @@ define i32 @nezero_const_or_all_ones(i32 %x) {
;
; MCU-LABEL: nezero_const_or_all_ones:
; MCU: # %bb.0:
; MCU-NEXT: xorl %ecx, %ecx
; MCU-NEXT: cmpl $1, %eax
; MCU-NEXT: sbbl %ecx, %ecx
; MCU-NEXT: orl $42, %ecx
; MCU-NEXT: movl %ecx, %eax
; MCU-NEXT: sbbl %eax, %eax
; MCU-NEXT: orl $42, %eax
; MCU-NEXT: retl
%z = icmp ne i32 %x, 0
%r = select i1 %z, i32 42, i32 -1
@@ -927,13 +970,21 @@ define i32 @nezero_const_or_all_ones(i32 %x) {
}
define i64 @eqzero_all_ones_or_const(i64 %x) {
; CHECK-LABEL: eqzero_all_ones_or_const:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: orq $42, %rax
; CHECK-NEXT: retq
; GENERIC-LABEL: eqzero_all_ones_or_const:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: cmpq $1, %rdi
; GENERIC-NEXT: sbbq %rax, %rax
; GENERIC-NEXT: orq $42, %rax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: eqzero_all_ones_or_const:
; ATOM: ## %bb.0:
; ATOM-NEXT: cmpq $1, %rdi
; ATOM-NEXT: sbbq %rax, %rax
; ATOM-NEXT: orq $42, %rax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: eqzero_all_ones_or_const:
; ATHLON: ## %bb.0:
@@ -963,14 +1014,23 @@ define i64 @eqzero_all_ones_or_const(i64 %x) {
}
define i8 @nezero_all_ones_or_const(i8 %x) {
; CHECK-LABEL: nezero_all_ones_or_const:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: negb %dil
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: orb $42, %al
; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
; GENERIC-LABEL: nezero_all_ones_or_const:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: negb %dil
; GENERIC-NEXT: sbbl %eax, %eax
; GENERIC-NEXT: orb $42, %al
; GENERIC-NEXT: ## kill: def $al killed $al killed $eax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: nezero_all_ones_or_const:
; ATOM: ## %bb.0:
; ATOM-NEXT: negb %dil
; ATOM-NEXT: sbbl %eax, %eax
; ATOM-NEXT: orb $42, %al
; ATOM-NEXT: ## kill: def $al killed $al killed $eax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: nezero_all_ones_or_const:
; ATHLON: ## %bb.0:
@@ -983,11 +1043,10 @@ define i8 @nezero_all_ones_or_const(i8 %x) {
;
; MCU-LABEL: nezero_all_ones_or_const:
; MCU: # %bb.0:
; MCU-NEXT: xorl %ecx, %ecx
; MCU-NEXT: negb %al
; MCU-NEXT: sbbl %ecx, %ecx
; MCU-NEXT: orb $42, %cl
; MCU-NEXT: movl %ecx, %eax
; MCU-NEXT: sbbl %eax, %eax
; MCU-NEXT: orb $42, %al
; MCU-NEXT: # kill: def $al killed $al killed $eax
; MCU-NEXT: retl
%z = icmp ne i8 %x, 0
%r = select i1 %z, i8 -1, i8 42

1
llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
View File

@@ -14,7 +14,6 @@ define i32 @PR29058(i8 %x, i32 %y) {
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: movl $2147483646, %eax # imm = 0x7FFFFFFE
; CHECK-NEXT: cmovnel %esi, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpb $1, %dil
; CHECK-NEXT: sbbl %ecx, %ecx
; CHECK-NEXT: orb %sil, %cl

32
llvm/test/CodeGen/X86/umul_fix_sat.ll
View File

@@ -443,30 +443,29 @@ define i64 @func7(i64 %x, i64 %y) nounwind {
; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %esi, %eax
; X86-NEXT: movl %ebx, %eax
; X86-NEXT: mull %ebp
; X86-NEXT: movl %edx, %ecx
; X86-NEXT: movl %eax, %edi
; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull %ebx
; X86-NEXT: addl %edx, %edi
; X86-NEXT: movl %eax, %esi
; X86-NEXT: movl %ebx, %eax
; X86-NEXT: mull %edi
; X86-NEXT: addl %edx, %esi
; X86-NEXT: adcl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull %ebp
; X86-NEXT: movl %edx, %esi
; X86-NEXT: movl %edx, %ebx
; X86-NEXT: movl %eax, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull %ebx
; X86-NEXT: addl %edi, %eax
; X86-NEXT: mull %edi
; X86-NEXT: addl %esi, %eax
; X86-NEXT: adcl %ecx, %edx
; X86-NEXT: adcl $0, %esi
; X86-NEXT: adcl $0, %ebx
; X86-NEXT: addl %ebp, %edx
; X86-NEXT: adcl $0, %esi
; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: negl %esi
; X86-NEXT: adcl $0, %ebx
; X86-NEXT: negl %ebx
; X86-NEXT: sbbl %ecx, %ecx
; X86-NEXT: orl %ecx, %eax
; X86-NEXT: orl %ecx, %edx
@@ -522,12 +521,11 @@ define i64 @func8(i64 %x, i64 %y) nounwind {
; X86-NEXT: shrdl $31, %edx, %eax
; X86-NEXT: movl %edx, %esi
; X86-NEXT: shrl $31, %esi
; X86-NEXT: xorl %edi, %edi
; X86-NEXT: negl %esi
; X86-NEXT: sbbl %edi, %edi
; X86-NEXT: orl %edi, %eax
; X86-NEXT: sbbl %esi, %esi
; X86-NEXT: orl %esi, %eax
; X86-NEXT: shrdl $31, %ecx, %edx
; X86-NEXT: orl %edi, %edx
; X86-NEXT: orl %esi, %edx
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx