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Revert "[LICM] Only create load in pre-header when promoting load."

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This reverts commit 4bf3b7dc92.

This might be causing another buildbot failure.
This commit is contained in:
Florian Hahn
2022-04-13 20:24:28 +02:00
parent 36cb736665
commit ad95255b92
2 changed files with 17 additions and 73 deletions
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35
llvm/lib/Transforms/Scalar/LICM.cpp
View File

@@ -2156,26 +2156,21 @@ bool llvm::promoteLoopAccessesToScalars(
// Set up the preheader to have a definition of the value. It is the live-out
// value from the preheader that uses in the loop will use.
LoadInst *PreheaderLoad = nullptr;
if (FoundLoadToPromote) {
PreheaderLoad =
new LoadInst(AccessTy, SomePtr, SomePtr->getName() + ".promoted",
Preheader->getTerminator());
if (SawUnorderedAtomic)
PreheaderLoad->setOrdering(AtomicOrdering::Unordered);
PreheaderLoad->setAlignment(Alignment);
PreheaderLoad->setDebugLoc(DebugLoc());
if (AATags)
PreheaderLoad->setAAMetadata(AATags);
LoadInst *PreheaderLoad = new LoadInst(
AccessTy, SomePtr, SomePtr->getName() + ".promoted",
Preheader->getTerminator());
if (SawUnorderedAtomic)
PreheaderLoad->setOrdering(AtomicOrdering::Unordered);
PreheaderLoad->setAlignment(Alignment);
PreheaderLoad->setDebugLoc(DebugLoc());
if (AATags)
PreheaderLoad->setAAMetadata(AATags);
SSA.AddAvailableValue(Preheader, PreheaderLoad);
MemoryAccess *PreheaderLoadMemoryAccess = MSSAU.createMemoryAccessInBB(
PreheaderLoad, nullptr, PreheaderLoad->getParent(), MemorySSA::End);
MemoryUse *NewMemUse = cast<MemoryUse>(PreheaderLoadMemoryAccess);
MSSAU.insertUse(NewMemUse, /*RenameUses=*/true);
SSA.AddAvailableValue(Preheader, PreheaderLoad);
} else {
SSA.AddAvailableValue(Preheader, PoisonValue::get(AccessTy));
}
MemoryAccess *PreheaderLoadMemoryAccess = MSSAU.createMemoryAccessInBB(
PreheaderLoad, nullptr, PreheaderLoad->getParent(), MemorySSA::End);
MemoryUse *NewMemUse = cast<MemoryUse>(PreheaderLoadMemoryAccess);
MSSAU.insertUse(NewMemUse, /*RenameUses=*/true);
if (VerifyMemorySSA)
MSSAU.getMemorySSA()->verifyMemorySSA();
@@ -2186,7 +2181,7 @@ bool llvm::promoteLoopAccessesToScalars(
if (VerifyMemorySSA)
MSSAU.getMemorySSA()->verifyMemorySSA();
// If the SSAUpdater didn't use the load in the preheader, just zap it now.
if (PreheaderLoad && PreheaderLoad->use_empty())
if (PreheaderLoad->use_empty())
eraseInstruction(*PreheaderLoad, *SafetyInfo, MSSAU);
return true;

55
llvm/test/Transforms/LICM/scalar-promote.ll
View File

@@ -605,9 +605,10 @@ Out:
define void @test_sink_store_only() writeonly {
; CHECK-LABEL: @test_sink_store_only(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[GLB_PROMOTED:%.*]] = load i8, i8* @glb, align 1
; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
; CHECK: loop.header:
; CHECK-NEXT: [[DIV1:%.*]] = phi i8 [ poison, [[ENTRY:%.*]] ], [ [[DIV:%.*]], [[LOOP_LATCH:%.*]] ]
; CHECK-NEXT: [[DIV1:%.*]] = phi i8 [ [[GLB_PROMOTED]], [[ENTRY:%.*]] ], [ [[DIV:%.*]], [[LOOP_LATCH:%.*]] ]
; CHECK-NEXT: [[I:%.*]] = phi i8 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[LOOP_LATCH]] ]
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[I]], 4
; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_LATCH]], label [[EXIT:%.*]]
@@ -668,58 +669,6 @@ exit:
ret void
}
define void @sink_store_lcssa_phis(i32* %ptr, i1 %c) {
; CHECK-LABEL: @sink_store_lcssa_phis(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]]
; CHECK: loop.1.header:
; CHECK-NEXT: br label [[LOOP_2_HEADER:%.*]]
; CHECK: loop.2.header:
; CHECK-NEXT: br i1 false, label [[LOOP_3_HEADER_PREHEADER:%.*]], label [[LOOP_1_LATCH:%.*]]
; CHECK: loop.3.header.preheader:
; CHECK-NEXT: br label [[LOOP_3_HEADER:%.*]]
; CHECK: loop.3.header:
; CHECK-NEXT: [[I_11:%.*]] = phi i32 [ [[I_1:%.*]], [[LOOP_3_LATCH:%.*]] ], [ poison, [[LOOP_3_HEADER_PREHEADER]] ]
; CHECK-NEXT: [[I_1]] = phi i32 [ 1, [[LOOP_3_LATCH]] ], [ 0, [[LOOP_3_HEADER_PREHEADER]] ]
; CHECK-NEXT: br i1 true, label [[LOOP_3_LATCH]], label [[LOOP_2_LATCH:%.*]]
; CHECK: loop.3.latch:
; CHECK-NEXT: br label [[LOOP_3_HEADER]]
; CHECK: loop.2.latch:
; CHECK-NEXT: [[I_11_LCSSA:%.*]] = phi i32 [ [[I_11]], [[LOOP_3_HEADER]] ]
; CHECK-NEXT: store i32 [[I_11_LCSSA]], i32* [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[LOOP_2_HEADER]]
; CHECK: loop.1.latch:
; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP_1_HEADER]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop.1.header
loop.1.header:
br label %loop.2.header
loop.2.header:
br i1 false, label %loop.3.header, label %loop.1.latch
loop.3.header:
%i.1 = phi i32 [ 1, %loop.3.latch ], [ 0, %loop.2.header ]
br i1 true, label %loop.3.latch, label %loop.2.latch
loop.3.latch:
store i32 %i.1, i32* %ptr, align 4
br label %loop.3.header
loop.2.latch:
br label %loop.2.header
loop.1.latch:
br i1 %c, label %loop.1.header, label %exit
exit:
ret void
}
!0 = !{!4, !4, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}