From b7eee2c3fe953df5f5aa1f543759d9a1e54d5ef7 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 18 Jan 2025 23:36:56 -0800 Subject: [PATCH] [CodeGen] Remove some implict conversions of MCRegister to unsigned by using(). NFC Many of these are indexing BitVectors or something where we can't using MCRegister and need the register number. --- llvm/include/llvm/CodeGen/CallingConvLower.h | 2 +- llvm/include/llvm/CodeGen/LivePhysRegs.h | 2 +- llvm/include/llvm/CodeGen/MachineOperand.h | 5 +++-- llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 4 ++-- llvm/include/llvm/CodeGen/Register.h | 2 +- llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 2 +- llvm/lib/CodeGen/CallingConvLower.cpp | 4 ++-- llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp | 8 ++++---- llvm/lib/CodeGen/ExecutionDomainFix.cpp | 2 +- llvm/lib/CodeGen/InterferenceCache.cpp | 2 +- .../CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 6 +++--- llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp | 4 ++-- llvm/lib/CodeGen/LiveRegMatrix.cpp | 3 ++- llvm/lib/CodeGen/MachineRegisterInfo.cpp | 4 ++-- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 12 ++++++------ llvm/lib/CodeGen/RDFLiveness.cpp | 2 +- llvm/lib/CodeGen/RegAllocGreedy.cpp | 4 ++-- llvm/lib/CodeGen/RegUsageInfoCollector.cpp | 8 ++++---- llvm/lib/CodeGen/RegisterClassInfo.cpp | 3 ++- 19 files changed, 41 insertions(+), 38 deletions(-) diff --git a/llvm/include/llvm/CodeGen/CallingConvLower.h b/llvm/include/llvm/CodeGen/CallingConvLower.h index d5a63c8dd627..85171138d1eb 100644 --- a/llvm/include/llvm/CodeGen/CallingConvLower.h +++ b/llvm/include/llvm/CodeGen/CallingConvLower.h @@ -254,7 +254,7 @@ public: /// isAllocated - Return true if the specified register (or an alias) is /// allocated. bool isAllocated(MCRegister Reg) const { - return UsedRegs[Reg / 32] & (1 << (Reg & 31)); + return UsedRegs[Reg.id() / 32] & (1 << (Reg.id() & 31)); } /// AnalyzeFormalArguments - Analyze an array of argument values, diff --git a/llvm/include/llvm/CodeGen/LivePhysRegs.h b/llvm/include/llvm/CodeGen/LivePhysRegs.h index d315e4ff6f3a..037905119eb2 100644 --- a/llvm/include/llvm/CodeGen/LivePhysRegs.h +++ b/llvm/include/llvm/CodeGen/LivePhysRegs.h @@ -93,7 +93,7 @@ public: assert(TRI && "LivePhysRegs is not initialized."); assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) - LiveRegs.erase(*R); + LiveRegs.erase((*R).id()); } /// Removes physical registers clobbered by the regmask operand \p MO. diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h index 63a172134538..be1b4fb7d54f 100644 --- a/llvm/include/llvm/CodeGen/MachineOperand.h +++ b/llvm/include/llvm/CodeGen/MachineOperand.h @@ -645,8 +645,9 @@ public: /// mask pointers. static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) { // See TargetRegisterInfo.h. - assert(PhysReg < (1u << 30) && "Not a physical register"); - return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); + assert((!PhysReg.isValid() || PhysReg.isPhysical()) && + "Not a physical register"); + return !(RegMask[PhysReg.id() / 32] & (1u << PhysReg.id() % 32)); } /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index 5ee3aef28a4f..91f68581df48 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -938,7 +938,7 @@ public: MCRegAliasIterator R(PhysReg, TRI, true); for (; R.isValid(); ++R) - ReservedRegs.set(*R); + ReservedRegs.set((*R).id()); } /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called @@ -951,7 +951,7 @@ public: /// register. Any register can be reserved before freezeReservedRegs() is /// called. bool canReserveReg(MCRegister PhysReg) const { - return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); + return !reservedRegsFrozen() || ReservedRegs.test(PhysReg.id()); } /// getReservedRegs - Returns a reference to the frozen set of reserved diff --git a/llvm/include/llvm/CodeGen/Register.h b/llvm/include/llvm/CodeGen/Register.h index 3412ea4b2446..fac5f00110ef 100644 --- a/llvm/include/llvm/CodeGen/Register.h +++ b/llvm/include/llvm/CodeGen/Register.h @@ -21,7 +21,7 @@ class Register { public: constexpr Register(unsigned Val = 0) : Reg(Val) {} - constexpr Register(MCRegister Val) : Reg(Val) {} + constexpr Register(MCRegister Val) : Reg(Val.id()) {} // Register numbers can represent physical registers, virtual registers, and // sometimes stack slots. The unsigned values are divided into these ranges: diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index e40248197c7c..2f123c22b330 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -420,7 +420,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction( if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) continue; - DefIndices[*AI] = Count; + DefIndices[(*AI).id()] = Count; } } } diff --git a/llvm/lib/CodeGen/CallingConvLower.cpp b/llvm/lib/CodeGen/CallingConvLower.cpp index b7152587a9fa..cebc9f5c4639 100644 --- a/llvm/lib/CodeGen/CallingConvLower.cpp +++ b/llvm/lib/CodeGen/CallingConvLower.cpp @@ -61,12 +61,12 @@ void CCState::HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, /// Mark a register and all of its aliases as allocated. void CCState::MarkAllocated(MCPhysReg Reg) { for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) - UsedRegs[*AI / 32] |= 1 << (*AI & 31); + UsedRegs[(*AI).id() / 32] |= 1 << ((*AI).id() & 31); } void CCState::MarkUnallocated(MCPhysReg Reg) { for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) - UsedRegs[*AI / 32] &= ~(1 << (*AI & 31)); + UsedRegs[(*AI).id() / 32] &= ~(1 << ((*AI).id() & 31)); } bool CCState::IsShadowAllocatedReg(MCRegister Reg) const { diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp index 106db7c51f27..e4bf77b6563a 100644 --- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -67,7 +67,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { for (const MachineBasicBlock *Succ : BB->successors()) for (const auto &LI : Succ->liveins()) { for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { - unsigned Reg = *AI; + unsigned Reg = (*AI).id(); Classes[Reg] = reinterpret_cast(-1); KillIndices[Reg] = BBSize; DefIndices[Reg] = ~0u; @@ -85,7 +85,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { if (!IsReturnBlock && !Pristine.test(Reg)) continue; for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { - unsigned Reg = *AI; + unsigned Reg = (*AI).id(); Classes[Reg] = reinterpret_cast(-1); KillIndices[Reg] = BBSize; DefIndices[Reg] = ~0u; @@ -200,7 +200,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) { // If an alias of the reg is used during the live range, give up. // Note that this allows us to skip checking if AntiDepReg // overlaps with any of the aliases, among other things. - unsigned AliasReg = *AI; + unsigned AliasReg = (*AI).id(); if (Classes[AliasReg]) { Classes[AliasReg] = reinterpret_cast(-1); Classes[Reg] = reinterpret_cast(-1); @@ -327,7 +327,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) { // It wasn't previously live but now it is, this is a kill. // Repeat for all aliases. for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { - unsigned AliasReg = *AI; + unsigned AliasReg = (*AI).id(); if (KillIndices[AliasReg] == ~0u) { KillIndices[AliasReg] = Count; DefIndices[AliasReg] = ~0u; diff --git a/llvm/lib/CodeGen/ExecutionDomainFix.cpp b/llvm/lib/CodeGen/ExecutionDomainFix.cpp index 21a7d02a320c..8bb5ac5a6de7 100644 --- a/llvm/lib/CodeGen/ExecutionDomainFix.cpp +++ b/llvm/lib/CodeGen/ExecutionDomainFix.cpp @@ -445,7 +445,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) { for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid(); ++AI) - AliasMap[*AI].push_back(i); + AliasMap[(*AI).id()].push_back(i); } // Initialize the MBBOutRegsInfos diff --git a/llvm/lib/CodeGen/InterferenceCache.cpp b/llvm/lib/CodeGen/InterferenceCache.cpp index 73cde07cfd51..ebdf0506bb22 100644 --- a/llvm/lib/CodeGen/InterferenceCache.cpp +++ b/llvm/lib/CodeGen/InterferenceCache.cpp @@ -78,7 +78,7 @@ InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) { continue; } Entries[E].reset(PhysReg, LIUArray, TRI, MF); - PhysRegEntries[PhysReg] = E; + PhysRegEntries[PhysReg.id()] = E; return &Entries[E]; } llvm_unreachable("Ran out of interference cache entries."); diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index ade67bb545d1..012bc37dd767 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -283,7 +283,7 @@ public: if (Reg >= MTracker->NumRegs) return false; for (MCRegAliasIterator RAI(Reg, &TRI, true); RAI.isValid(); ++RAI) - if (CalleeSavedRegs.test(*RAI)) + if (CalleeSavedRegs.test((*RAI).id())) return true; return false; }; @@ -1345,7 +1345,7 @@ bool InstrRefBasedLDV::isCalleeSaved(LocIdx L) const { } bool InstrRefBasedLDV::isCalleeSavedReg(Register R) const { for (MCRegAliasIterator RAI(R, TRI, true); RAI.isValid(); ++RAI) - if (CalleeSavedRegs.test(*RAI)) + if (CalleeSavedRegs.test((*RAI).id())) return true; return false; } @@ -1880,7 +1880,7 @@ void InstrRefBasedLDV::transferRegisterDef(MachineInstr &MI) { // Remove ranges of all aliased registers. for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI) // FIXME: Can we break out of this loop early if no insertion occurs? - DeadRegs.insert(*RAI); + DeadRegs.insert((*RAI).id()); } else if (MO.isRegMask()) { RegMasks.push_back(MO.getRegMask()); RegMaskPtrs.push_back(&MO); diff --git a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp index a5e6bebcd29c..94e7f1b734fd 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp @@ -1606,7 +1606,7 @@ void VarLocBasedLDV::transferRegisterDef(MachineInstr &MI, // Remove ranges of all aliased registers. for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI) // FIXME: Can we break out of this loop early if no insertion occurs? - DeadRegs.insert(*RAI); + DeadRegs.insert((*RAI).id()); RegSetInstrs.erase(MO.getReg()); RegSetInstrs.insert({MO.getReg(), &MI}); } else if (MO.isRegMask()) { @@ -1866,7 +1866,7 @@ void VarLocBasedLDV::transferRegisterCopy(MachineInstr &MI, auto isCalleeSavedReg = [&](Register Reg) { for (MCRegAliasIterator RAI(Reg, TRI, true); RAI.isValid(); ++RAI) - if (CalleeSavedRegs.test(*RAI)) + if (CalleeSavedRegs.test((*RAI).id())) return true; return false; }; diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp index 3367171a1566..83df95e71002 100644 --- a/llvm/lib/CodeGen/LiveRegMatrix.cpp +++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp @@ -165,7 +165,8 @@ bool LiveRegMatrix::checkRegMaskInterference(const LiveInterval &VirtReg, // The BitVector is indexed by PhysReg, not register unit. // Regmask interference is more fine grained than regunits. // For example, a Win64 call can clobber %ymm8 yet preserve %xmm8. - return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg)); + return !RegMaskUsable.empty() && + (!PhysReg || !RegMaskUsable.test(PhysReg.id())); } bool LiveRegMatrix::checkRegUnitInterference(const LiveInterval &VirtReg, diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index 532e537c2549..f058445cc556 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -584,7 +584,7 @@ static bool isNoReturnDef(const MachineOperand &MO) { bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef) const { - if (UsedPhysRegMask.test(PhysReg)) + if (UsedPhysRegMask.test(PhysReg.id())) return true; const TargetRegisterInfo *TRI = getTargetRegisterInfo(); for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { @@ -599,7 +599,7 @@ bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest) const { - if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg)) + if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg.id())) return true; const TargetRegisterInfo *TRI = getTargetRegisterInfo(); for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 34dd79c7b618..51e9a067707e 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1240,9 +1240,9 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { continue; MCRegister Reg = MO.getReg(); - if (AllocatableSet[Reg] && !MO.isImplicit() && + if (AllocatableSet[Reg.id()] && !MO.isImplicit() && (MO.isDef() || MO.isUse())) - UsedRegs.set(Reg); + UsedRegs.set(Reg.id()); } } @@ -1262,20 +1262,20 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { continue; // Want only used registers. - if (OnlyUsed && !UsedRegs[Reg]) + if (OnlyUsed && !UsedRegs[Reg.id()]) continue; // Want only registers used for arguments. if (OnlyArg) { if (OnlyUsed) { - if (!LiveIns[Reg]) + if (!LiveIns[Reg.id()]) continue; } else if (!TRI.isArgumentRegister(MF, Reg)) { continue; } } - RegsToZero.set(Reg); + RegsToZero.set(Reg.id()); } // Don't clear registers that are live when leaving the function. @@ -1328,7 +1328,7 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { for (const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); MCPhysReg CSReg = *CSRegs; ++CSRegs) for (MCRegister Reg : TRI.sub_and_superregs_inclusive(CSReg)) - RegsToZero.reset(Reg); + RegsToZero.reset(Reg.id()); const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering(); for (MachineBasicBlock &MBB : MF) diff --git a/llvm/lib/CodeGen/RDFLiveness.cpp b/llvm/lib/CodeGen/RDFLiveness.cpp index 11f3fedaa5f9..7b4b7fdb3e76 100644 --- a/llvm/lib/CodeGen/RDFLiveness.cpp +++ b/llvm/lib/CodeGen/RDFLiveness.cpp @@ -960,7 +960,7 @@ void Liveness::resetKills(MachineBasicBlock *B) { continue; bool IsLive = false; for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) { - if (!Live[*AR]) + if (!Live[(*AR).id()]) continue; IsLive = true; break; diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 66e9cf546b83..6077cfd514de 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -439,7 +439,7 @@ MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg, } // Try to evict interference from a cheaper alternative. - uint8_t Cost = RegCosts[PhysReg]; + uint8_t Cost = RegCosts[PhysReg.id()]; // Most registers have 0 additional cost. if (!Cost) @@ -559,7 +559,7 @@ RegAllocEvictionAdvisor::getOrderLimit(const LiveInterval &VirtReg, bool RegAllocEvictionAdvisor::canAllocatePhysReg(unsigned CostPerUseLimit, MCRegister PhysReg) const { - if (RegCosts[PhysReg] >= CostPerUseLimit) + if (RegCosts[PhysReg.id()] >= CostPerUseLimit) return false; // The first use of a callee-saved register in a function has cost 1. // Don't start using a CSR when the CostPerUseLimit is low. diff --git a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index f539966fe617..07b4bc7ffd3e 100644 --- a/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -162,12 +162,12 @@ bool RegUsageInfoCollector::run(MachineFunction &MF) { computeCalleeSavedRegs(SavedRegs, MF); const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); - auto SetRegAsDefined = [&RegMask] (unsigned Reg) { - RegMask[Reg / 32] &= ~(1u << Reg % 32); + auto SetRegAsDefined = [&RegMask](MCRegister Reg) { + RegMask[Reg.id() / 32] &= ~(1u << Reg.id() % 32); }; // Don't include $noreg in any regmasks. - SetRegAsDefined(MCRegister::NoRegister); + SetRegAsDefined(MCRegister()); // Some targets can clobber registers "inside" a call, typically in // linker-generated code. @@ -186,7 +186,7 @@ bool RegUsageInfoCollector::run(MachineFunction &MF) { // with all it's unsaved aliases. if (!MRI->def_empty(PReg)) { for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) - if (!SavedRegs.test(*AI)) + if (!SavedRegs.test((*AI).id())) SetRegAsDefined(*AI); continue; } diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index 9312bc03bc52..40fc35a16335 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -95,7 +95,8 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { BitVector CSRHintsForAllocOrder(TRI->getNumRegs()); for (const MCPhysReg *I = CSR; *I; ++I) for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) - CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI); + CSRHintsForAllocOrder[(*AI).id()] = + STI.ignoreCSRForAllocationOrder(mf, *AI); if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) { Update = true; IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;