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[TableGen] Combine the two separate OperandMapping loops in PseudoLoweringEmitter. (#136007)

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Previously we had one loop over the DAG for immediates and registers and
another loop over the destination operands for mapping from the source.

Now we have a single loop over the destination operands that handles immediates,
registers, and named operands. A helper method is added so we can handle
operands and sub-operands specified by a sub-dag.

My goal is to allow a named operand to appear in a sub-dag which wasn't
supported before. This will allow the destination instruction to have an
operand with sub-operands when the source does not have sub operands.

For RISC-V, I'm looking into using an operand with sub-operands to
represent an reg+offset memory address. I need to be able to lower a
pseudo instruction that only has a register operand to an instruction
that has a reg+offset operand. The offset will be filled in with 0
during expansion and the register will be copied from the source.

The expansion would look like this:
def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
                                [(riscv_call GPRJALR:$rs1)]>,
PseudoInstExpansion<(JALR X1, (ops GPR:$rs1, 0))>;
This commit is contained in:
Craig Topper
2025-04-16 15:47:16 -07:00
committed by GitHub
parent d35bf17e8a
commit b9f1de04f6
1 changed files with 98 additions and 96 deletions
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194
llvm/utils/TableGen/PseudoLoweringEmitter.cpp
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@@ -51,10 +51,11 @@ class PseudoLoweringEmitter {
SmallVector<PseudoExpansion, 64> Expansions; SmallVector<PseudoExpansion, 64> Expansions;
unsigned addDagOperandMapping(const Record *Rec, const DagInit *Dag, void addOperandMapping(unsigned MIOpNo, unsigned NumOps, const Record *Rec,
const CodeGenInstruction &Insn, const DagInit *Dag, unsigned DagIdx,
IndexedMap<OpData> &OperandMap, const Record *OpRec, IndexedMap<OpData> &OperandMap,
unsigned BaseIdx); const StringMap<unsigned> &SourceOperands,
const CodeGenInstruction &SourceInsn);
void evaluateExpansion(const Record *Pseudo); void evaluateExpansion(const Record *Pseudo);
void emitLoweringEmitter(raw_ostream &o); void emitLoweringEmitter(raw_ostream &o);
@@ -66,64 +67,67 @@ public:
}; };
} // End anonymous namespace } // End anonymous namespace
// FIXME: This pass currently can only expand a pseudo to a single instruction. void PseudoLoweringEmitter::addOperandMapping(
// The pseudo expansion really should take a list of dags, not just unsigned MIOpNo, unsigned NumOps, const Record *Rec, const DagInit *Dag,
// a single dag, so we can do fancier things. unsigned DagIdx, const Record *OpRec, IndexedMap<OpData> &OperandMap,
unsigned PseudoLoweringEmitter::addDagOperandMapping( const StringMap<unsigned> &SourceOperands,
const Record *Rec, const DagInit *Dag, const CodeGenInstruction &Insn, const CodeGenInstruction &SourceInsn) {
IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { const Init *DagArg = Dag->getArg(DagIdx);
unsigned OpsAdded = 0; if (const DefInit *DI = dyn_cast<DefInit>(DagArg)) {
for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { // Physical register reference. Explicit check for the special case
if (const DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) { // "zero_reg" definition.
// Physical register reference. Explicit check for the special case if (DI->getDef()->isSubClassOf("Register") ||
// "zero_reg" definition. DI->getDef()->getName() == "zero_reg") {
if (DI->getDef()->isSubClassOf("Register") || auto &Entry = OperandMap[MIOpNo];
DI->getDef()->getName() == "zero_reg") { Entry.Kind = OpData::Reg;
auto &Entry = OperandMap[BaseIdx + i]; Entry.Data.Reg = DI->getDef();
Entry.Kind = OpData::Reg; return;
Entry.Data.Reg = DI->getDef(); }
++OpsAdded;
continue;
}
// Normal operands should always have the same type, or we have a if (DI->getDef() != OpRec)
// problem. PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
// FIXME: We probably shouldn't ever get a non-zero BaseIdx here. "', operand type '" + DI->getDef()->getName() +
assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); "' does not match expansion operand type '" +
if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) OpRec->getName() + "'");
PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
"', operand type '" + DI->getDef()->getName() + StringMap<unsigned>::const_iterator SourceOp =
"' does not match expansion operand type '" + SourceOperands.find(Dag->getArgNameStr(DagIdx));
Insn.Operands[BaseIdx + i].Rec->getName() + if (SourceOp == SourceOperands.end())
"'"); PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
// Source operand maps to destination operand. The Data element "', output operand '" +
// will be filled in later, just set the Kind for now. Do it Dag->getArgNameStr(DagIdx) +
// for each corresponding MachineInstr operand, not just the first. "' has no matching source operand");
for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) const auto &SrcOpnd = SourceInsn.Operands[SourceOp->getValue()];
OperandMap[BaseIdx + i + I].Kind = OpData::Operand; if (NumOps != SrcOpnd.MINumOperands)
OpsAdded += Insn.Operands[i].MINumOperands; PrintFatalError(
} else if (const IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) { Rec,
auto &Entry = OperandMap[BaseIdx + i]; "In pseudo instruction '" + Rec->getName() + "', output operand '" +
Entry.Kind = OpData::Imm; OpRec->getName() +
Entry.Data.Imm = II->getValue(); "' has a different number of sub operands than source operand '" +
++OpsAdded; SrcOpnd.Rec->getName() + "'");
} else if (const auto *BI = dyn_cast<BitsInit>(Dag->getArg(i))) {
auto &Entry = OperandMap[BaseIdx + i]; // Source operand maps to destination operand. Do it for each corresponding
Entry.Kind = OpData::Imm; // MachineInstr operand, not just the first.
Entry.Data.Imm = *BI->convertInitializerToInt(); for (unsigned I = 0, E = NumOps; I != E; ++I) {
++OpsAdded; auto &Entry = OperandMap[MIOpNo + I];
} else if (const DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) { Entry.Kind = OpData::Operand;
// Just add the operands recursively. This is almost certainly Entry.Data.Operand = SrcOpnd.MIOperandNo + I;
// a constant value for a complex operand (> 1 MI operand). }
unsigned NewOps =
addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << DagIdx
OpsAdded += NewOps; << "\n");
// Since we added more than one, we also need to adjust the base. } else if (const auto *II = dyn_cast<IntInit>(DagArg)) {
BaseIdx += NewOps - 1; assert(NumOps == 1);
} else auto &Entry = OperandMap[MIOpNo];
llvm_unreachable("Unhandled pseudo-expansion argument type!"); Entry.Kind = OpData::Imm;
} Entry.Data.Imm = II->getValue();
return OpsAdded; } else if (const auto *BI = dyn_cast<BitsInit>(DagArg)) {
assert(NumOps == 1);
auto &Entry = OperandMap[MIOpNo];
Entry.Kind = OpData::Imm;
Entry.Data.Imm = *BI->convertInitializerToInt();
} else
llvm_unreachable("Unhandled pseudo-expansion argument type!");
} }
void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) { void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
@@ -157,14 +161,6 @@ void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
"', result operator '" + Operator->getName() + "', result operator '" + Operator->getName() +
"' has the wrong number of operands"); "' has the wrong number of operands");
unsigned NumMIOperands = 0;
for (const auto &Op : Insn.Operands)
NumMIOperands += Op.MINumOperands;
IndexedMap<OpData> OperandMap;
OperandMap.grow(NumMIOperands);
addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
// If there are more operands that weren't in the DAG, they have to // If there are more operands that weren't in the DAG, they have to
// be operands that have default values, or we have an error. Currently, // be operands that have default values, or we have an error. Currently,
// Operands that are a subclass of OperandWithDefaultOp have default values. // Operands that are a subclass of OperandWithDefaultOp have default values.
@@ -180,37 +176,43 @@ void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) {
for (const auto &[Idx, SrcOp] : enumerate(SourceInsn.Operands)) for (const auto &[Idx, SrcOp] : enumerate(SourceInsn.Operands))
SourceOperands[SrcOp.Name] = Idx; SourceOperands[SrcOp.Name] = Idx;
unsigned NumMIOperands = 0;
for (const auto &Op : Insn.Operands)
NumMIOperands += Op.MINumOperands;
IndexedMap<OpData> OperandMap;
OperandMap.grow(NumMIOperands);
// FIXME: This pass currently can only expand a pseudo to a single
// instruction. The pseudo expansion really should take a list of dags, not
// just a single dag, so we can do fancier things.
LLVM_DEBUG(dbgs() << " Operand mapping:\n"); LLVM_DEBUG(dbgs() << " Operand mapping:\n");
for (const auto &[Idx, Opnd] : enumerate(Insn.Operands)) { for (const auto &[Idx, DstOp] : enumerate(Insn.Operands)) {
// We've already handled constant values. Just map instruction operands unsigned MIOpNo = DstOp.MIOperandNo;
// here.
if (OperandMap[Opnd.MIOperandNo].Kind != OpData::Operand)
continue;
StringMap<unsigned>::iterator SourceOp =
SourceOperands.find(Dag->getArgNameStr(Idx));
if (SourceOp == SourceOperands.end())
PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
"', output operand '" + Dag->getArgNameStr(Idx) +
"' has no matching source operand");
const auto &SrcOpnd = SourceInsn.Operands[SourceOp->getValue()];
if (Opnd.MINumOperands != SrcOpnd.MINumOperands)
PrintFatalError(
Rec,
"In pseudo instruction '" + Rec->getName() + "', output operand '" +
Opnd.Rec->getName() +
"' has a different number of sub operands than source operand '" +
SrcOpnd.Rec->getName() + "'");
// Map the source operand to the destination operand index for each if (const auto *SubDag = dyn_cast<DagInit>(Dag->getArg(Idx))) {
// MachineInstr operand. if (!DstOp.MIOperandInfo || DstOp.MIOperandInfo->getNumArgs() == 0)
for (unsigned I = 0, E = Opnd.MINumOperands; I != E; ++I) PrintFatalError(Rec, "In pseudo instruction '" + Rec->getName() +
OperandMap[Opnd.MIOperandNo + I].Data.Operand = SrcOpnd.MIOperandNo + I; "', operand '" + DstOp.Rec->getName() +
"' does not have suboperands");
LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << Idx if (DstOp.MINumOperands != SubDag->getNumArgs()) {
<< "\n"); PrintFatalError(
Rec, "In pseudo instruction '" + Rec->getName() + "', '" +
SubDag->getAsString() +
"' has wrong number of operands for operand type '" +
DstOp.Rec->getName() + "'");
}
for (unsigned I = 0, E = DstOp.MINumOperands; I != E; ++I) {
auto *OpndRec = cast<DefInit>(DstOp.MIOperandInfo->getArg(I))->getDef();
addOperandMapping(MIOpNo + I, 1, Rec, SubDag, I, OpndRec, OperandMap,
SourceOperands, SourceInsn);
}
} else {
addOperandMapping(MIOpNo, DstOp.MINumOperands, Rec, Dag, Idx, DstOp.Rec,
OperandMap, SourceOperands, SourceInsn);
}
} }
Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap)); Expansions.emplace_back(SourceInsn, Insn, OperandMap);
} }
void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {