[DAGCombiner] Fold pattern for srl-shl-zext (#138290)
Fold `(srl (lop x, (shl (zext y), c1)), c1) -> (lop (srl x, c1), (zext y))` where c1 <= leadingzeros(zext(y)). This is equivalent of existing fold chain `(srl (shl (zext y), c1), c1) -> (and (zext y), mask) -> (zext y)`, but logical op in the middle prevents it from combining. Profit : Allow to reduce the number of instructions. --------- Signed-off-by: Alexander Peskov <apeskov@nvidia.com>
This commit is contained in:
Alexander Peskov
@@ -10972,6 +10972,22 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
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}
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// fold (srl (logic_op x, (shl (zext y), c1)), c1)
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// -> (logic_op (srl x, c1), (zext y))
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// c1 <= leadingzeros(zext(y))
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SDValue X, ZExtY;
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if (N1C && sd_match(N0, m_OneUse(m_BitwiseLogic(
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m_Value(X),
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m_OneUse(m_Shl(m_AllOf(m_Value(ZExtY),
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m_Opc(ISD::ZERO_EXTEND)),
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m_Specific(N1))))))) {
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unsigned NumLeadingZeros = ZExtY.getScalarValueSizeInBits() -
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ZExtY.getOperand(0).getScalarValueSizeInBits();
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if (N1C->getZExtValue() <= NumLeadingZeros)
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return DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
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DAG.getNode(ISD::SRL, SDLoc(N0), VT, X, N1), ZExtY);
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}
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// fold operands of srl based on knowledge that the low bits are not
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// demanded.
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if (SimplifyDemandedBits(SDValue(N, 0)))
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152
llvm/test/CodeGen/NVPTX/shift-opt.ll
Normal file
152
llvm/test/CodeGen/NVPTX/shift-opt.ll
Normal file
@@ -0,0 +1,152 @@
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; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s
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define i64 @test_or(i64 %x, i32 %y) {
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;
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; Fold: srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))
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; c1 <= leadingzeros(zext(y))
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;
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; CHECK-LABEL: test_or
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; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_or_param_0];
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; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_or_param_1];
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; CHECK: shr.u64 %[[SHR:rd[0-9]+]], %[[X]], 5;
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; CHECK: or.b64 %[[LOP:rd[0-9]+]], %[[SHR]], %[[Y]];
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; CHECK: st.param.b64 [func_retval0], %[[LOP]];
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;
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%ext = zext i32 %y to i64
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%shl = shl i64 %ext, 5
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%or = or i64 %x, %shl
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%srl = lshr i64 %or, 5
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ret i64 %srl
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}
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define i64 @test_xor(i64 %x, i32 %y) {
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;
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; Fold: srl (xor (x, shl(zext(y),c1)),c1) -> xor(srl(x,c1), zext(y))
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; c1 <= leadingzeros(zext(y))
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;
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; CHECK-LABEL: test_xor
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; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_xor_param_0];
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; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_xor_param_1];
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; CHECK: shr.u64 %[[SHR:rd[0-9]+]], %[[X]], 5;
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; CHECK: xor.b64 %[[LOP:rd[0-9]+]], %[[SHR]], %[[Y]];
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; CHECK: st.param.b64 [func_retval0], %[[LOP]];
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;
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%ext = zext i32 %y to i64
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%shl = shl i64 %ext, 5
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%or = xor i64 %x, %shl
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%srl = lshr i64 %or, 5
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ret i64 %srl
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}
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define i64 @test_and(i64 %x, i32 %y) {
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;
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; Fold: srl (and (x, shl(zext(y),c1)),c1) -> and(srl(x,c1), zext(y))
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; c1 <= leadingzeros(zext(y))
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;
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; CHECK-LABEL: test_and
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; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_and_param_0];
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; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_and_param_1];
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; CHECK: shr.u64 %[[SHR:rd[0-9]+]], %[[X]], 5;
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; CHECK: and.b64 %[[LOP:rd[0-9]+]], %[[SHR]], %[[Y]];
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; CHECK: st.param.b64 [func_retval0], %[[LOP]];
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;
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%ext = zext i32 %y to i64
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%shl = shl i64 %ext, 5
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%or = and i64 %x, %shl
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%srl = lshr i64 %or, 5
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ret i64 %srl
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}
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define <2 x i16> @test_vec(<2 x i16> %x, <2 x i8> %y) {
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;
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; Fold: srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))
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; c1 <= leadingzeros(zext(y))
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; x, y - vectors
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;
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; CHECK-LABEL: test_vec
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; CHECK: ld.param.u32 %[[X:r[0-9]+]], [test_vec_param_0];
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; CHECK: ld.param.u32 %[[P1:r[0-9]+]], [test_vec_param_1];
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; CHECK: and.b32 %[[Y:r[0-9]+]], %[[P1]], 16711935;
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; CHECK: mov.b32 {%[[X1:rs[0-9]+]], %[[X2:rs[0-9]+]]}, %[[X]];
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; CHECK: shr.u16 %[[SHR2:rs[0-9]+]], %[[X2]], 5;
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; CHECK: shr.u16 %[[SHR1:rs[0-9]+]], %[[X1]], 5;
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; CHECK: mov.b32 %[[SHR:r[0-9]+]], {%[[SHR1]], %[[SHR2]]};
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; CHECK: or.b32 %[[LOP:r[0-9]+]], %[[SHR]], %[[Y]];
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; CHECK: st.param.b32 [func_retval0], %[[LOP]];
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;
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%ext = zext <2 x i8> %y to <2 x i16>
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%shl = shl <2 x i16> %ext, splat(i16 5)
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%or = or <2 x i16> %x, %shl
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%srl = lshr <2 x i16> %or, splat(i16 5)
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ret <2 x i16> %srl
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}
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define i64 @test_negative_c(i64 %x, i32 %y) {
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;
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; Do not fold: srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))
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; Reason: c1 > leadingzeros(zext(y)).
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;
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; CHECK-LABEL: test_negative_c
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; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_negative_c_param_0];
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; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_negative_c_param_1];
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; CHECK: shl.b64 %[[SHL:rd[0-9]+]], %[[Y]], 33;
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; CHECK: or.b64 %[[OR:rd[0-9]+]], %[[X]], %[[SHL]];
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; CHECK: shr.u64 %[[SHR:rd[0-9]+]], %[[OR]], 33;
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; CHECK: st.param.b64 [func_retval0], %[[SHR]];
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;
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%ext = zext i32 %y to i64
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%shl = shl i64 %ext, 33
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%or = or i64 %x, %shl
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%srl = lshr i64 %or, 33
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ret i64 %srl
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}
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declare void @use(i64)
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define i64 @test_negative_use_lop(i64 %x, i32 %y) {
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;
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; Do not fold: srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))
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; Reason: multiple usage of "or"
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;
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; CHECK-LABEL: test_negative_use_lop
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; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_negative_use_lop_param_0];
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; CHECK: ld.param.u32 %[[Y:r[0-9]+]], [test_negative_use_lop_param_1];
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; CHECK: mul.wide.u32 %[[SHL:rd[0-9]+]], %[[Y]], 32;
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; CHECK: or.b64 %[[OR:rd[0-9]+]], %[[X]], %[[SHL]];
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; CHECK: shr.u64 %[[SHR:rd[0-9]+]], %[[OR]], 5;
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; CHECK: { // callseq
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; CHECK: st.param.b64 [param0], %[[OR]];
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; CHECK: } // callseq
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; CHECK: st.param.b64 [func_retval0], %[[SHR]];
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;
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%ext = zext i32 %y to i64
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%shl = shl i64 %ext, 5
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%or = or i64 %x, %shl
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%srl = lshr i64 %or, 5
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call void @use(i64 %or)
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ret i64 %srl
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}
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define i64 @test_negative_use_shl(i64 %x, i32 %y) {
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;
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; Do not fold: srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))
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; Reason: multiple usage of "shl"
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;
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; CHECK-LABEL: test_negative_use_shl
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; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_negative_use_shl_param_0];
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; CHECK: ld.param.u32 %[[Y:r[0-9]+]], [test_negative_use_shl_param_1];
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; CHECK: mul.wide.u32 %[[SHL:rd[0-9]+]], %[[Y]], 32;
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; CHECK: or.b64 %[[OR:rd[0-9]+]], %[[X]], %[[SHL]];
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; CHECK: shr.u64 %[[SHR:rd[0-9]+]], %[[OR]], 5;
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; CHECK: { // callseq
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; CHECK: st.param.b64 [param0], %[[SHL]];
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; CHECK: } // callseq
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; CHECK: st.param.b64 [func_retval0], %[[SHR]];
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;
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%ext = zext i32 %y to i64
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%shl = shl i64 %ext, 5
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%or = or i64 %x, %shl
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%srl = lshr i64 %or, 5
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call void @use(i64 %shl)
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ret i64 %srl
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}
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