From c33770d87fd15cf6433a49f34aa31663726ea196 Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Tue, 12 Apr 2022 15:16:20 +0300 Subject: [PATCH] [AMDGPU][DOC][NFC] Updated GFX10 assembler syntax description The description has been updated to reflect AMDGPU MC changes: - enabled literals for src0 of v_fmaak_f*, v_fmamk_f*, v_madak_f32, v_madmk_f32; - enabled global_atomic_fcmpswap and global_atomic_fcmpswap_x2; - enabled dlc with flat_atomic* and global_atomic_*. Bug fixing and improvements: - enabled s_wait_idle; - enabled s_waitcnt_depctr; - added description of s_waitcnt_depctr syntactic sugar; - disabled SYSMSG_OP_HOST_TRAP_ACK (it is not supported on GFX10); - corrected description of lgkmcnt (accept values from 0 to 63). --- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 4043 +++++++++-------- llvm/docs/AMDGPU/gfx10_hwreg.rst | 42 +- llvm/docs/AMDGPU/gfx10_imm16_2.rst | 13 - ...gfx10_imm16.rst => gfx10_imm16_73139a.rst} | 2 +- ...x10_imm16_1.rst => gfx10_imm16_a04fb3.rst} | 2 +- .../{gfx10_m_1.rst => gfx10_m_254bcb.rst} | 2 +- .../{gfx10_m.rst => gfx10_m_f5d306.rst} | 2 +- llvm/docs/AMDGPU/gfx10_msg.rst | 45 +- ...gfx10_saddr.rst => gfx10_saddr_beaa25.rst} | 4 +- ...x10_saddr_1.rst => gfx10_saddr_da2a8a.rst} | 4 +- ...x10_sbase_1.rst => gfx10_sbase_010ce0.rst} | 2 +- ...gfx10_sbase.rst => gfx10_sbase_020892.rst} | 2 +- ...x10_sbase_2.rst => gfx10_sbase_b2d796.rst} | 2 +- ...gfx10_sdata.rst => gfx10_sdata_3d2ab7.rst} | 2 +- ...x10_sdata_3.rst => gfx10_sdata_6fbc49.rst} | 2 +- ...x10_sdata_5.rst => gfx10_sdata_7cbd60.rst} | 2 +- ...x10_sdata_1.rst => gfx10_sdata_7e874d.rst} | 2 +- ...x10_sdata_4.rst => gfx10_sdata_81ba27.rst} | 2 +- ...x10_sdata_2.rst => gfx10_sdata_c6aec1.rst} | 2 +- ...gfx10_sdst_4.rst => gfx10_sdst_0804b1.rst} | 2 +- ...gfx10_sdst_8.rst => gfx10_sdst_2e4c2a.rst} | 2 +- ...gfx10_sdst_5.rst => gfx10_sdst_362c37.rst} | 2 +- .../{gfx10_sdst.rst => gfx10_sdst_3759f6.rst} | 2 +- ...gfx10_sdst_3.rst => gfx10_sdst_386c33.rst} | 2 +- ...gfx10_sdst_2.rst => gfx10_sdst_3bc700.rst} | 2 +- ...gfx10_sdst_1.rst => gfx10_sdst_54e16e.rst} | 2 +- ...gfx10_sdst_6.rst => gfx10_sdst_8078f5.rst} | 2 +- ...gfx10_sdst_7.rst => gfx10_sdst_ea3f10.rst} | 2 +- ...0_simm32_2.rst => gfx10_simm32_6f0844.rst} | 4 +- ...x10_simm32.rst => gfx10_simm32_a3e80c.rst} | 2 +- ...0_simm32_1.rst => gfx10_simm32_be0c1c.rst} | 4 +- ...soffset_2.rst => gfx10_soffset_59fade.rst} | 2 +- ...0_soffset.rst => gfx10_soffset_b556e6.rst} | 2 +- ...soffset_1.rst => gfx10_soffset_c40a5a.rst} | 2 +- .../{gfx10_src.rst => gfx10_src_37d670.rst} | 2 +- .../{gfx10_src_5.rst => gfx10_src_516946.rst} | 2 +- llvm/docs/AMDGPU/gfx10_src_7.rst | 17 - .../{gfx10_src_2.rst => gfx10_src_823582.rst} | 2 +- .../{gfx10_src_8.rst => gfx10_src_c27036.rst} | 2 +- .../{gfx10_src_6.rst => gfx10_src_cf1cda.rst} | 2 +- .../{gfx10_src_3.rst => gfx10_src_d5cd94.rst} | 2 +- .../{gfx10_src_1.rst => gfx10_src_e0345d.rst} | 2 +- .../{gfx10_src_4.rst => gfx10_src_e9e6db.rst} | 2 +- ...gfx10_srsrc.rst => gfx10_srsrc_cf7132.rst} | 2 +- ...x10_srsrc_1.rst => gfx10_srsrc_e73d16.rst} | 2 +- ...gfx10_ssrc_8.rst => gfx10_ssrc_054e2a.rst} | 2 +- ...gfx10_ssrc_1.rst => gfx10_ssrc_2a042f.rst} | 2 +- ...gfx10_ssrc_5.rst => gfx10_ssrc_3ec588.rst} | 2 +- ...gfx10_ssrc_4.rst => gfx10_ssrc_460c63.rst} | 2 +- ...gfx10_ssrc_7.rst => gfx10_ssrc_48e8e7.rst} | 2 +- ...gfx10_ssrc_2.rst => gfx10_ssrc_6fbc49.rst} | 2 +- .../{gfx10_ssrc.rst => gfx10_ssrc_7da351.rst} | 2 +- ...gfx10_ssrc_3.rst => gfx10_ssrc_81ba27.rst} | 2 +- ...gfx10_ssrc_6.rst => gfx10_ssrc_9a4448.rst} | 2 +- llvm/docs/AMDGPU/gfx10_tgt.rst | 20 +- llvm/docs/AMDGPU/gfx10_vaddr_2.rst | 20 - ...x10_vaddr_3.rst => gfx10_vaddr_76b997.rst} | 4 +- llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst | 20 + ...x10_vaddr_1.rst => gfx10_vaddr_9f7133.rst} | 2 +- ...x10_vaddr_5.rst => gfx10_vaddr_b73dc0.rst} | 2 +- ...x10_vaddr_4.rst => gfx10_vaddr_cdc744.rst} | 2 +- ...gfx10_vaddr.rst => gfx10_vaddr_f20ee4.rst} | 2 +- ...x10_vdata0.rst => gfx10_vdata0_6802ce.rst} | 2 +- ...0_vdata0_1.rst => gfx10_vdata0_fd235e.rst} | 2 +- ...x10_vdata1.rst => gfx10_vdata1_6802ce.rst} | 2 +- ...0_vdata1_1.rst => gfx10_vdata1_fd235e.rst} | 2 +- ...x10_vdata_6.rst => gfx10_vdata_15d255.rst} | 2 +- ...x10_vdata_4.rst => gfx10_vdata_325b78.rst} | 2 +- ...x10_vdata_5.rst => gfx10_vdata_4d8ecf.rst} | 2 +- ...x10_vdata_3.rst => gfx10_vdata_56f215.rst} | 2 +- ...gfx10_vdata.rst => gfx10_vdata_6802ce.rst} | 2 +- ...10_vdata_10.rst => gfx10_vdata_87fb90.rst} | 2 +- ...x10_vdata_9.rst => gfx10_vdata_b2a787.rst} | 2 +- ...x10_vdata_7.rst => gfx10_vdata_c08393.rst} | 2 +- ...x10_vdata_8.rst => gfx10_vdata_c61803.rst} | 2 +- ...x10_vdata_2.rst => gfx10_vdata_e016a1.rst} | 2 +- ...x10_vdata_1.rst => gfx10_vdata_fd235e.rst} | 2 +- ...gfx10_vdst_7.rst => gfx10_vdst_3d7dcf.rst} | 2 +- ...gfx10_vdst_5.rst => gfx10_vdst_463513.rst} | 2 +- ...gfx10_vdst_8.rst => gfx10_vdst_473a69.rst} | 2 +- ...gfx10_vdst_6.rst => gfx10_vdst_48d3a8.rst} | 2 +- ...gfx10_vdst_3.rst => gfx10_vdst_48e42f.rst} | 2 +- ...gfx10_vdst_9.rst => gfx10_vdst_5d50a1.rst} | 2 +- ...gfx10_vdst_2.rst => gfx10_vdst_69a144.rst} | 2 +- ...fx10_vdst_13.rst => gfx10_vdst_719833.rst} | 2 +- .../{gfx10_vdst.rst => gfx10_vdst_89680f.rst} | 2 +- ...fx10_vdst_11.rst => gfx10_vdst_a49b76.rst} | 2 +- ...gfx10_vdst_1.rst => gfx10_vdst_bdb32f.rst} | 2 +- ...gfx10_vdst_4.rst => gfx10_vdst_d0dc43.rst} | 2 +- ...fx10_vdst_10.rst => gfx10_vdst_d7c57e.rst} | 2 +- ...fx10_vdst_12.rst => gfx10_vdst_f47754.rst} | 2 +- ...gfx10_vsrc_1.rst => gfx10_vsrc_533a4e.rst} | 2 +- .../{gfx10_vsrc.rst => gfx10_vsrc_6802ce.rst} | 2 +- ...gfx10_vsrc_2.rst => gfx10_vsrc_e016a1.rst} | 2 +- ...gfx10_vsrc_3.rst => gfx10_vsrc_fd235e.rst} | 2 +- llvm/docs/AMDGPU/gfx10_waitcnt.rst | 2 +- llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst | 39 + 97 files changed, 2228 insertions(+), 2217 deletions(-) delete mode 100644 llvm/docs/AMDGPU/gfx10_imm16_2.rst rename llvm/docs/AMDGPU/{gfx10_imm16.rst => gfx10_imm16_73139a.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_imm16_1.rst => gfx10_imm16_a04fb3.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_m_1.rst => gfx10_m_254bcb.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_m.rst => gfx10_m_f5d306.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_saddr.rst => gfx10_saddr_beaa25.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_saddr_1.rst => gfx10_saddr_da2a8a.rst} (78%) rename llvm/docs/AMDGPU/{gfx10_sbase_1.rst => gfx10_sbase_010ce0.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_sbase.rst => gfx10_sbase_020892.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_sbase_2.rst => gfx10_sbase_b2d796.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_sdata.rst => gfx10_sdata_3d2ab7.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_sdata_3.rst => gfx10_sdata_6fbc49.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_sdata_5.rst => gfx10_sdata_7cbd60.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_sdata_1.rst => gfx10_sdata_7e874d.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_sdata_4.rst => gfx10_sdata_81ba27.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_sdata_2.rst => gfx10_sdata_c6aec1.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_sdst_4.rst => gfx10_sdst_0804b1.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_sdst_8.rst => gfx10_sdst_2e4c2a.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_sdst_5.rst => gfx10_sdst_362c37.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_sdst.rst => gfx10_sdst_3759f6.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_sdst_3.rst => gfx10_sdst_386c33.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_sdst_2.rst => gfx10_sdst_3bc700.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_sdst_1.rst => gfx10_sdst_54e16e.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_sdst_6.rst => gfx10_sdst_8078f5.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_sdst_7.rst => gfx10_sdst_ea3f10.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_simm32_2.rst => gfx10_simm32_6f0844.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_simm32.rst => gfx10_simm32_a3e80c.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_simm32_1.rst => gfx10_simm32_be0c1c.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_soffset_2.rst => gfx10_soffset_59fade.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_soffset.rst => gfx10_soffset_b556e6.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_soffset_1.rst => gfx10_soffset_c40a5a.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_src.rst => gfx10_src_37d670.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_src_5.rst => gfx10_src_516946.rst} (92%) delete mode 100644 llvm/docs/AMDGPU/gfx10_src_7.rst rename llvm/docs/AMDGPU/{gfx10_src_2.rst => gfx10_src_823582.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_src_8.rst => gfx10_src_c27036.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_src_6.rst => gfx10_src_cf1cda.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_src_3.rst => gfx10_src_d5cd94.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_src_1.rst => gfx10_src_e0345d.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_src_4.rst => gfx10_src_e9e6db.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_srsrc.rst => gfx10_srsrc_cf7132.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_srsrc_1.rst => gfx10_srsrc_e73d16.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_ssrc_8.rst => gfx10_ssrc_054e2a.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_ssrc_1.rst => gfx10_ssrc_2a042f.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_ssrc_5.rst => gfx10_ssrc_3ec588.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_ssrc_4.rst => gfx10_ssrc_460c63.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_ssrc_7.rst => gfx10_ssrc_48e8e7.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_ssrc_2.rst => gfx10_ssrc_6fbc49.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_ssrc.rst => gfx10_ssrc_7da351.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_ssrc_3.rst => gfx10_ssrc_81ba27.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_ssrc_6.rst => gfx10_ssrc_9a4448.rst} (94%) delete mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_2.rst rename llvm/docs/AMDGPU/{gfx10_vaddr_3.rst => gfx10_vaddr_76b997.rst} (76%) create mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst rename llvm/docs/AMDGPU/{gfx10_vaddr_1.rst => gfx10_vaddr_9f7133.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vaddr_5.rst => gfx10_vaddr_b73dc0.rst} (96%) rename llvm/docs/AMDGPU/{gfx10_vaddr_4.rst => gfx10_vaddr_cdc744.rst} (96%) rename llvm/docs/AMDGPU/{gfx10_vaddr.rst => gfx10_vaddr_f20ee4.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vdata0.rst => gfx10_vdata0_6802ce.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdata0_1.rst => gfx10_vdata0_fd235e.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdata1.rst => gfx10_vdata1_6802ce.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdata1_1.rst => gfx10_vdata1_fd235e.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdata_6.rst => gfx10_vdata_15d255.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_vdata_4.rst => gfx10_vdata_325b78.rst} (96%) rename llvm/docs/AMDGPU/{gfx10_vdata_5.rst => gfx10_vdata_4d8ecf.rst} (96%) rename llvm/docs/AMDGPU/{gfx10_vdata_3.rst => gfx10_vdata_56f215.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdata.rst => gfx10_vdata_6802ce.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdata_10.rst => gfx10_vdata_87fb90.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_vdata_9.rst => gfx10_vdata_b2a787.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_vdata_7.rst => gfx10_vdata_c08393.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_vdata_8.rst => gfx10_vdata_c61803.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_vdata_2.rst => gfx10_vdata_e016a1.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdata_1.rst => gfx10_vdata_fd235e.rst} (90%) rename llvm/docs/AMDGPU/{gfx10_vdst_7.rst => gfx10_vdst_3d7dcf.rst} (94%) rename llvm/docs/AMDGPU/{gfx10_vdst_5.rst => gfx10_vdst_463513.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_vdst_8.rst => gfx10_vdst_473a69.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_vdst_6.rst => gfx10_vdst_48d3a8.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_vdst_3.rst => gfx10_vdst_48e42f.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vdst_9.rst => gfx10_vdst_5d50a1.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_vdst_2.rst => gfx10_vdst_69a144.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vdst_13.rst => gfx10_vdst_719833.rst} (95%) rename llvm/docs/AMDGPU/{gfx10_vdst.rst => gfx10_vdst_89680f.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vdst_11.rst => gfx10_vdst_a49b76.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_vdst_1.rst => gfx10_vdst_bdb32f.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vdst_4.rst => gfx10_vdst_d0dc43.rst} (93%) rename llvm/docs/AMDGPU/{gfx10_vdst_10.rst => gfx10_vdst_d7c57e.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_vdst_12.rst => gfx10_vdst_f47754.rst} (92%) rename llvm/docs/AMDGPU/{gfx10_vsrc_1.rst => gfx10_vsrc_533a4e.rst} (96%) rename llvm/docs/AMDGPU/{gfx10_vsrc.rst => gfx10_vsrc_6802ce.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vsrc_2.rst => gfx10_vsrc_e016a1.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_vsrc_3.rst => gfx10_vsrc_fd235e.rst} (91%) create mode 100644 llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst index e4207084ee23..ec7ff6da472e 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst @@ -32,1263 +32,1265 @@ Instructions DPP16 ------------------------ +----- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sat_pk_u8_i16_dpp :ref:`vdst`::ref:`u8x4`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` - v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sat_pk_u8_i16_dpp :ref:`vdst`::ref:`u8x4`, :ref:`vsrc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` + v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp16_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` :ref:`fi` DPP8 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`i16` :ref:`dpp8_sel` :ref:`fi` - v_log_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_log_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sat_pk_u8_i16_dpp :ref:`vdst`::ref:`u8x4`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` - v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` - v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` - v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_add_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_norm_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_fmac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`::ref:`i16` :ref:`dpp8_sel` :ref:`fi` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movreld_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrels_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_2_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_movrelsd_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sat_pk_u8_i16_dpp :ref:`vdst`::ref:`u8x4`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_sub_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_sub_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_co_ci_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_subrev_nc_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp8_sel` :ref:`fi` + v_xnor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` + v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp8_sel` :ref:`fi` DS ------------------------ +-- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_append :ref:`vdst` :ref:`offset` :ref:`gds` - ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` - ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` - ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` - ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` - ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_add_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_add_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_and_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_and_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_append :ref:`vdst` :ref:`offset` :ref:`gds` + ds_bpermute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_cmpst_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_f64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_cmpst_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_consume :ref:`vdst` :ref:`offset` :ref:`gds` + ds_dec_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_dec_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_dec_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_barrier :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_init :ref:`vdata` :ref:`offset` :ref:`gds` + ds_gws_sema_br :ref:`vdata` :ref:`offset` :ref:`gds` ds_gws_sema_p :ref:`offset` :ref:`gds` ds_gws_sema_release_all :ref:`offset` :ref:`gds` ds_gws_sema_v :ref:`offset` :ref:`gds` - ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_inc_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_inc_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_inc_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_max_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_max_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_f64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_i64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_f64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_src2_f32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_f64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_i64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_min_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_min_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_mskor_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_mskor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` ds_nop - ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` - ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_read_addtid_b32 :ref:`vdst` :ref:`offset` :ref:`gds` - ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` - ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` - ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_write_addtid_b32 :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` - ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` - ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` - ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_or_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_or_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_ordered_count :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_permute_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` + ds_read2_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read2st64_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_read_addtid_b32 :ref:`vdst` :ref:`offset` :ref:`gds` + ds_read_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_i8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u16_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_read_u8_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_rsub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_rsub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_rtn_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_src2_u32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_src2_u64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_sub_u32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_sub_u64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_swizzle_b32 :ref:`vdst`, :ref:`vaddr` :ref:`pattern` :ref:`gds` + ds_wrap_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset` :ref:`gds` + ds_write2_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b32 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write2st64_b64 :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_write_addtid_b32 :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b128 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b16_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b8_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_b96 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_write_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_write_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_wrxchg2_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b32 :ref:`vdst`::ref:`b32x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg2st64_rtn_b64 :ref:`vdst`::ref:`b64x2`, :ref:`vaddr`, :ref:`vdata0`, :ref:`vdata1` :ref:`offset0` :ref:`offset1` :ref:`gds` + ds_wrxchg_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_wrxchg_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b32 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_b64 :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_rtn_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vdata` :ref:`offset` :ref:`gds` + ds_xor_src2_b32 :ref:`vaddr` :ref:`offset` :ref:`gds` + ds_xor_src2_b64 :ref:`vaddr` :ref:`offset` :ref:`gds` EXP ------------------------ +--- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` + exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` FLAT ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` - flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_short_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_short_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - flat_store_short_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` - global_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` - global_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - global_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` - scratch_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dword :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx2 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx3 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_dwordx4 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sbyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_short_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_short_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_sshort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ubyte :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_load_ushort :ref:`vdst`, :ref:`vaddr` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_byte :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dword :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx2 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx3 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_dwordx4 :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_short :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + flat_store_short_d16_hi :ref:`vaddr`, :ref:`vdata` :ref:`offset11` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_add :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_add_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_and :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_and_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_cmpswap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b32x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_cmpswap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`::ref:`b64x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_dec :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_dec_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_fcmpswap :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_fcmpswap_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64x2`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_fmax :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_fmax_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_fmin :ref:`vdst`::ref:`opt`::ref:`f32`, :ref:`vaddr`, :ref:`vdata`::ref:`f32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_fmin_x2 :ref:`vdst`::ref:`opt`::ref:`f64`, :ref:`vaddr`, :ref:`vdata`::ref:`f64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_inc :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_inc_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_or :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_or_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smax :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smax_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smin :ref:`vdst`::ref:`opt`::ref:`i32`, :ref:`vaddr`, :ref:`vdata`::ref:`i32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_smin_x2 :ref:`vdst`::ref:`opt`::ref:`i64`, :ref:`vaddr`, :ref:`vdata`::ref:`i64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_sub :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_sub_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_swap :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_swap_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umax :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umax_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umin :ref:`vdst`::ref:`opt`::ref:`u32`, :ref:`vaddr`, :ref:`vdata`::ref:`u32`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_umin_x2 :ref:`vdst`::ref:`opt`::ref:`u64`, :ref:`vaddr`, :ref:`vdata`::ref:`u64`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_xor :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_atomic_xor_x2 :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + global_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_byte :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_byte_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dword :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx2 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx3 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_dwordx4 :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_short :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` + scratch_store_short_d16_hi :ref:`vaddr`, :ref:`vdata`, :ref:`saddr` :ref:`offset12s` :ref:`glc` :ref:`slc` :ref:`dlc` MIMG ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_fcmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_fmax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_fmin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` - image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` - image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` - image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` - image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` - image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` - image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` - image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` - image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` - image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` - image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` - image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` - image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` - image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_fcmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_fmax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_fmin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lwe` :ref:`d16` + image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` + image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cd_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_cl_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_d_o_g16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`tfe` :ref:`lwe` :ref:`d16` + image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` :ref:`d16` + image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` + image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`dim` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`a16` :ref:`lwe` MTBUF ------------------------ +----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`ufmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` MUBUF ------------------------ +----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap :ref:`vdata`::ref:`dst`::ref:`f32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fcmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`f64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmax_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin :ref:`vdata`::ref:`dst`::ref:`f32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_fmin_x2 :ref:`vdata`::ref:`dst`::ref:`f64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` buffer_gl0_inv buffer_gl1_inv - buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` - buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` - buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` - buffer_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` - buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` - buffer_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` - buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` - buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_byte_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_short_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dword :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_sbyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_sbyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_sbyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_short_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_short_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_sshort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_ubyte :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_load_ubyte_d16 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_ubyte_d16_hi :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` + buffer_load_ushort :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`dlc` :ref:`lds` + buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_byte_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_short_d16_hi :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` SDWA ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_add_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_and_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_bfrev_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ceil_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cmp_class_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_class_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_eq_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_f_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ge_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_gt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_le_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_lt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ne_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_neq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_neq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ngt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_ngt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nle_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nle_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_nlt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_o_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_o_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_t_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_tru_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_tru_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_u_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmp_u_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_class_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_class_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_eq_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_f_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ge_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_gt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_le_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_lt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ne_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_neq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_neq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ngt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_ngt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nle_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nle_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_nlt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_o_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_o_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_t_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_tru_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_tru_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_u_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cmpx_u_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` - v_cndmask_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cos_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_norm_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_norm_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_exp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbh_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ffbl_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_floor_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_fract_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_log_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_max_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_min_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mov_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movreld_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movrels_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movrelsd_2_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_movrelsd_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_not_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_or_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rndne_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_rsq_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sat_pk_u8_i16_sdwa :ref:`vdst`::ref:`u8x4`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sin_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sqrt_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_sub_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_sub_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_subrev_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_trunc_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` - v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` - v_xor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_and_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_bfrev_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cmp_class_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_class_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_i32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_u32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f16_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f32_sdwa :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_i32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_u32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f16_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f32_sdwa :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cndmask_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_cos_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_norm_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_norm_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_i32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_u32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbl_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ldexp_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_log_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`u32`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_i32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mov_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movreld_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movrels_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movrelsd_2_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_movrelsd_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_mul_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_not_b32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_or_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_rcp_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sat_pk_u8_i16_sdwa :ref:`vdst`::ref:`u8x4`, :ref:`src`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sub_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_co_ci_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f16_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_nc_u32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_trunc_f16_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f32_sdwa :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_xnor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_xor_b32_sdwa :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` SMEM ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_atc_probe :ref:`probe`, :ref:`sbase`, :ref:`soffset` - s_atc_probe_buffer :ref:`probe`, :ref:`sbase`, :ref:`soffset` - s_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smax :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smin :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smax :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smin :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_dcache_discard :ref:`sbase`, :ref:`soffset` - s_dcache_discard_x2 :ref:`sbase`, :ref:`soffset` + s_atc_probe :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_atc_probe_buffer :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smax :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smin :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_add :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_add_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_and :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_and_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_cmpswap :ref:`sdata`::ref:`dst`::ref:`b32x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_cmpswap_x2 :ref:`sdata`::ref:`dst`::ref:`b64x2`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_dec :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_dec_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_inc :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_inc_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_or :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_or_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smax :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smax_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smin :ref:`sdata`::ref:`dst`::ref:`i32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_smin_x2 :ref:`sdata`::ref:`dst`::ref:`i64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_sub :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_sub_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_swap :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_swap_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umax :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umax_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umin :ref:`sdata`::ref:`dst`::ref:`u32`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_umin_x2 :ref:`sdata`::ref:`dst`::ref:`u64`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_xor :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_atomic_xor_x2 :ref:`sdata`::ref:`dst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_dcache_discard :ref:`sbase`, :ref:`soffset` + s_dcache_discard_x2 :ref:`sbase`, :ref:`soffset` s_dcache_inv s_dcache_wb - s_get_waveid_in_workgroup :ref:`sdst` + s_get_waveid_in_workgroup :ref:`sdst` s_gl1_inv - s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_memrealtime :ref:`sdst`::ref:`b64` - s_memtime :ref:`sdst`::ref:`b64` - s_scratch_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_scratch_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_scratch_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` - s_scratch_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_scratch_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_scratch_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_memrealtime :ref:`sdst`::ref:`b64` + s_memtime :ref:`sdst`::ref:`b64` + s_scratch_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_scratch_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_scratch_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` :ref:`dlc` + s_scratch_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_scratch_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_scratch_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` SOP1 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_abs_i32 :ref:`sdst`, :ref:`ssrc` - s_and_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn1_wrexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn1_wrexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_andn2_wrexec_b32 :ref:`sdst`, :ref:`ssrc` - s_andn2_wrexec_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_bitreplicate_b64_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` - s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` - s_brev_b32 :ref:`sdst`, :ref:`ssrc` - s_brev_b64 :ref:`sdst`, :ref:`ssrc` - s_cmov_b32 :ref:`sdst`, :ref:`ssrc` - s_cmov_b64 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` - s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` - s_getpc_b64 :ref:`sdst` - s_mov_b32 :ref:`sdst`, :ref:`ssrc` - s_mov_b64 :ref:`sdst`, :ref:`ssrc` - s_movreld_b32 :ref:`sdst`, :ref:`ssrc` - s_movreld_b64 :ref:`sdst`, :ref:`ssrc` - s_movrels_b32 :ref:`sdst`, :ref:`ssrc` - s_movrels_b64 :ref:`sdst`, :ref:`ssrc` - s_movrelsd_2_b32 :ref:`sdst`, :ref:`ssrc` - s_nand_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_nor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_not_b32 :ref:`sdst`, :ref:`ssrc` - s_not_b64 :ref:`sdst`, :ref:`ssrc` - s_or_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_orn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_orn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_orn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` - s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` - s_rfe_b64 :ref:`ssrc` - s_setpc_b64 :ref:`ssrc` - s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` - s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` - s_swappc_b64 :ref:`sdst`, :ref:`ssrc` - s_wqm_b32 :ref:`sdst`, :ref:`ssrc` - s_wqm_b64 :ref:`sdst`, :ref:`ssrc` - s_xnor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` - s_xor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` - s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_abs_i32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn1_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn1_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_andn2_wrexec_b32 :ref:`sdst`, :ref:`ssrc` + s_andn2_wrexec_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_bitreplicate_b64_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset0_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_bitset1_b32 :ref:`sdst`, :ref:`ssrc` + s_bitset1_b64 :ref:`sdst`, :ref:`ssrc`::ref:`b32` + s_brev_b32 :ref:`sdst`, :ref:`ssrc` + s_brev_b64 :ref:`sdst`, :ref:`ssrc` + s_cmov_b32 :ref:`sdst`, :ref:`ssrc` + s_cmov_b64 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff0_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_ff1_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b32 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_b64 :ref:`sdst`, :ref:`ssrc` + s_flbit_i32_i64 :ref:`sdst`, :ref:`ssrc` + s_getpc_b64 :ref:`sdst` + s_mov_b32 :ref:`sdst`, :ref:`ssrc` + s_mov_b64 :ref:`sdst`, :ref:`ssrc` + s_movreld_b32 :ref:`sdst`, :ref:`ssrc` + s_movreld_b64 :ref:`sdst`, :ref:`ssrc` + s_movrels_b32 :ref:`sdst`, :ref:`ssrc` + s_movrels_b64 :ref:`sdst`, :ref:`ssrc` + s_movrelsd_2_b32 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_not_b32 :ref:`sdst`, :ref:`ssrc` + s_not_b64 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn1_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_orn1_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_orn2_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b32 :ref:`sdst`, :ref:`ssrc` + s_quadmask_b64 :ref:`sdst`, :ref:`ssrc` + s_rfe_b64 :ref:`ssrc` + s_setpc_b64 :ref:`ssrc` + s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc` + s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc` + s_swappc_b64 :ref:`sdst`, :ref:`ssrc` + s_wqm_b32 :ref:`sdst`, :ref:`ssrc` + s_wqm_b64 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b32 :ref:`sdst`, :ref:`ssrc` + s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc` SOP2 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` - s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl1_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl2_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl3_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl4_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_hi_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_hi_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_pack_hh_b32_b16 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` - s_pack_lh_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`b32` - s_pack_ll_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` - s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_addc_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_andn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl1_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl2_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl3_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl4_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_hi_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_hi_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_orn2_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_pack_hh_b32_b16 :ref:`sdst`, :ref:`ssrc0`::ref:`b32`, :ref:`ssrc1`::ref:`b32` + s_pack_lh_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`::ref:`b32` + s_pack_ll_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_sub_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_subb_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` + s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` SOPC ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` - s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` - s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` - s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` + s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1`::ref:`u32` + s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` + s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` SOPK ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_addk_i32 :ref:`sdst`, :ref:`imm16` - s_call_b64 :ref:`sdst`, :ref:`label` - s_cmovk_i32 :ref:`sdst`, :ref:`imm16` - s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` - s_getreg_b32 :ref:`sdst`, :ref:`hwreg` - s_movk_i32 :ref:`sdst`, :ref:`imm16` - s_mulk_i32 :ref:`sdst`, :ref:`imm16` - s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` - s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` - s_subvector_loop_begin :ref:`sdst`, :ref:`label` - s_subvector_loop_end :ref:`sdst`, :ref:`label` - s_version :ref:`imm16` - s_waitcnt_expcnt :ref:`ssrc`, :ref:`imm16` - s_waitcnt_lgkmcnt :ref:`ssrc`, :ref:`imm16` - s_waitcnt_vmcnt :ref:`ssrc`, :ref:`imm16` - s_waitcnt_vscnt :ref:`ssrc`, :ref:`imm16` + s_addk_i32 :ref:`sdst`, :ref:`imm16` + s_call_b64 :ref:`sdst`, :ref:`label` + s_cmovk_i32 :ref:`sdst`, :ref:`imm16` + s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` + s_getreg_b32 :ref:`sdst`, :ref:`hwreg` + s_movk_i32 :ref:`sdst`, :ref:`imm16` + s_mulk_i32 :ref:`sdst`, :ref:`imm16` + s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` + s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` + s_subvector_loop_begin :ref:`sdst`, :ref:`label` + s_subvector_loop_end :ref:`sdst`, :ref:`label` + s_version :ref:`imm16` + s_waitcnt_expcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_lgkmcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_vmcnt :ref:`ssrc`, :ref:`imm16` + s_waitcnt_vscnt :ref:`ssrc`, :ref:`imm16` SOPP ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **SRC** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_barrier s_branch :ref:`label` s_cbranch_cdbgsys :ref:`label` @@ -1301,848 +1303,850 @@ SOPP s_cbranch_scc1 :ref:`label` s_cbranch_vccnz :ref:`label` s_cbranch_vccz :ref:`label` - s_clause :ref:`imm16` + s_clause :ref:`imm16` s_code_end - s_decperflevel :ref:`imm16` - s_denorm_mode :ref:`imm16` + s_decperflevel :ref:`imm16` + s_denorm_mode :ref:`imm16` s_endpgm s_endpgm_ordered_ps_done s_endpgm_saved s_icache_inv - s_incperflevel :ref:`imm16` - s_inst_prefetch :ref:`imm16` - s_nop :ref:`imm16` - s_round_mode :ref:`imm16` + s_incperflevel :ref:`imm16` + s_inst_prefetch :ref:`imm16` + s_nop :ref:`imm16` + s_round_mode :ref:`imm16` s_sendmsg :ref:`msg` s_sendmsghalt :ref:`msg` - s_sethalt :ref:`imm16` - s_setkill :ref:`imm16` - s_setprio :ref:`imm16` - s_sleep :ref:`imm16` - s_trap :ref:`imm16` + s_sethalt :ref:`imm16` + s_setkill :ref:`imm16` + s_setprio :ref:`imm16` + s_sleep :ref:`imm16` + s_trap :ref:`imm16` s_ttracedata - s_ttracedata_imm :ref:`imm16` + s_ttracedata_imm :ref:`imm16` + s_wait_idle s_waitcnt :ref:`waitcnt` + s_waitcnt_depctr :ref:`waitcnt_depctr` s_wakeup VINTRP ------------------------ +------ .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` - v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` - v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + v_interp_mov_f32 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` + v_interp_p1_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` + v_interp_p2_f32 :ref:`vdst`, :ref:`vsrc`, :ref:`attr`::ref:`b32` VOP1 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_bfrev_b32 :ref:`vdst`, :ref:`src` - v_ceil_f16 :ref:`vdst`, :ref:`src` - v_ceil_f32 :ref:`vdst`, :ref:`src` - v_ceil_f64 :ref:`vdst`, :ref:`src` + v_bfrev_b32 :ref:`vdst`, :ref:`src` + v_ceil_f16 :ref:`vdst`, :ref:`src` + v_ceil_f32 :ref:`vdst`, :ref:`src` + v_ceil_f64 :ref:`vdst`, :ref:`src` v_clrexcp - v_cos_f16 :ref:`vdst`, :ref:`src` - v_cos_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_i16 :ref:`vdst`, :ref:`src` - v_cvt_f16_u16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f64 :ref:`vdst`, :ref:`src` - v_cvt_f32_i32 :ref:`vdst`, :ref:`src` - v_cvt_f32_u32 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` - v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` - v_cvt_f64_f32 :ref:`vdst`, :ref:`src` - v_cvt_f64_i32 :ref:`vdst`, :ref:`src` - v_cvt_f64_u32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f64 :ref:`vdst`, :ref:`src` - v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` - v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_u32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f64 :ref:`vdst`, :ref:`src` - v_exp_f16 :ref:`vdst`, :ref:`src` - v_exp_f32 :ref:`vdst`, :ref:`src` - v_ffbh_i32 :ref:`vdst`, :ref:`src` - v_ffbh_u32 :ref:`vdst`, :ref:`src` - v_ffbl_b32 :ref:`vdst`, :ref:`src` - v_floor_f16 :ref:`vdst`, :ref:`src` - v_floor_f32 :ref:`vdst`, :ref:`src` - v_floor_f64 :ref:`vdst`, :ref:`src` - v_fract_f16 :ref:`vdst`, :ref:`src` - v_fract_f32 :ref:`vdst`, :ref:`src` - v_fract_f64 :ref:`vdst`, :ref:`src` - v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` - v_frexp_mant_f16 :ref:`vdst`, :ref:`src` - v_frexp_mant_f32 :ref:`vdst`, :ref:`src` - v_frexp_mant_f64 :ref:`vdst`, :ref:`src` - v_log_f16 :ref:`vdst`, :ref:`src` - v_log_f32 :ref:`vdst`, :ref:`src` - v_mov_b32 :ref:`vdst`, :ref:`src` - v_movreld_b32 :ref:`vdst`, :ref:`src` - v_movrels_b32 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_2_b32 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` + v_cos_f16 :ref:`vdst`, :ref:`src` + v_cos_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_f32 :ref:`vdst`, :ref:`src` + v_cvt_f16_i16 :ref:`vdst`, :ref:`src` + v_cvt_f16_u16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f16 :ref:`vdst`, :ref:`src` + v_cvt_f32_f64 :ref:`vdst`, :ref:`src` + v_cvt_f32_i32 :ref:`vdst`, :ref:`src` + v_cvt_f32_u32 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` + v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` + v_cvt_f64_f32 :ref:`vdst`, :ref:`src` + v_cvt_f64_i32 :ref:`vdst`, :ref:`src` + v_cvt_f64_u32 :ref:`vdst`, :ref:`src` + v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_i32_f64 :ref:`vdst`, :ref:`src` + v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src` + v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` + v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u16_f16 :ref:`vdst`, :ref:`src` + v_cvt_u32_f32 :ref:`vdst`, :ref:`src` + v_cvt_u32_f64 :ref:`vdst`, :ref:`src` + v_exp_f16 :ref:`vdst`, :ref:`src` + v_exp_f32 :ref:`vdst`, :ref:`src` + v_ffbh_i32 :ref:`vdst`, :ref:`src` + v_ffbh_u32 :ref:`vdst`, :ref:`src` + v_ffbl_b32 :ref:`vdst`, :ref:`src` + v_floor_f16 :ref:`vdst`, :ref:`src` + v_floor_f32 :ref:`vdst`, :ref:`src` + v_floor_f64 :ref:`vdst`, :ref:`src` + v_fract_f16 :ref:`vdst`, :ref:`src` + v_fract_f32 :ref:`vdst`, :ref:`src` + v_fract_f64 :ref:`vdst`, :ref:`src` + v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` + v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` + v_frexp_mant_f16 :ref:`vdst`, :ref:`src` + v_frexp_mant_f32 :ref:`vdst`, :ref:`src` + v_frexp_mant_f64 :ref:`vdst`, :ref:`src` + v_log_f16 :ref:`vdst`, :ref:`src` + v_log_f32 :ref:`vdst`, :ref:`src` + v_mov_b32 :ref:`vdst`, :ref:`src` + v_movreld_b32 :ref:`vdst`, :ref:`src` + v_movrels_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_2_b32 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32 :ref:`vdst`, :ref:`vsrc` v_nop - v_not_b32 :ref:`vdst`, :ref:`src` + v_not_b32 :ref:`vdst`, :ref:`src` v_pipeflush - v_rcp_f16 :ref:`vdst`, :ref:`src` - v_rcp_f32 :ref:`vdst`, :ref:`src` - v_rcp_f64 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` - v_readfirstlane_b32 :ref:`sdst`, :ref:`src` - v_rndne_f16 :ref:`vdst`, :ref:`src` - v_rndne_f32 :ref:`vdst`, :ref:`src` - v_rndne_f64 :ref:`vdst`, :ref:`src` - v_rsq_f16 :ref:`vdst`, :ref:`src` - v_rsq_f32 :ref:`vdst`, :ref:`src` - v_rsq_f64 :ref:`vdst`, :ref:`src` - v_sat_pk_u8_i16 :ref:`vdst`::ref:`u8x4`, :ref:`src` - v_sin_f16 :ref:`vdst`, :ref:`src` - v_sin_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f16 :ref:`vdst`, :ref:`src` - v_sqrt_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f64 :ref:`vdst`, :ref:`src` - v_swap_b32 :ref:`vdst`, :ref:`vsrc` - v_swaprel_b32 :ref:`vdst`, :ref:`vsrc` - v_trunc_f16 :ref:`vdst`, :ref:`src` - v_trunc_f32 :ref:`vdst`, :ref:`src` - v_trunc_f64 :ref:`vdst`, :ref:`src` + v_rcp_f16 :ref:`vdst`, :ref:`src` + v_rcp_f32 :ref:`vdst`, :ref:`src` + v_rcp_f64 :ref:`vdst`, :ref:`src` + v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` + v_readfirstlane_b32 :ref:`sdst`, :ref:`src` + v_rndne_f16 :ref:`vdst`, :ref:`src` + v_rndne_f32 :ref:`vdst`, :ref:`src` + v_rndne_f64 :ref:`vdst`, :ref:`src` + v_rsq_f16 :ref:`vdst`, :ref:`src` + v_rsq_f32 :ref:`vdst`, :ref:`src` + v_rsq_f64 :ref:`vdst`, :ref:`src` + v_sat_pk_u8_i16 :ref:`vdst`::ref:`u8x4`, :ref:`src` + v_sin_f16 :ref:`vdst`, :ref:`src` + v_sin_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f16 :ref:`vdst`, :ref:`src` + v_sqrt_f32 :ref:`vdst`, :ref:`src` + v_sqrt_f64 :ref:`vdst`, :ref:`src` + v_swap_b32 :ref:`vdst`, :ref:`vsrc` + v_swaprel_b32 :ref:`vdst`, :ref:`vsrc` + v_trunc_f16 :ref:`vdst`, :ref:`src` + v_trunc_f32 :ref:`vdst`, :ref:`src` + v_trunc_f64 :ref:`vdst`, :ref:`src` VOP2 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` - v_fmaak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` - v_fmaak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` - v_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_fmamk_f16 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` - v_fmamk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` - v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` - v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` - v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` - v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` - v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_pk_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_add_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`f32`, :ref:`vsrc1`::ref:`f32` + v_fmaak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_fmaak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_fmamk_f16 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_fmamk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` + v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` + v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mac_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` + v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` + v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_pk_fmac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_sub_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_co_ci_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` + v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_subrev_nc_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xnor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` + v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` VOP3 ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_add_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_add_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_add_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_add_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` - v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` - v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_add3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_add_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_lshl_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_add_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_add_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_add_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_alignbit_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_alignbyte_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`b16` + v_and_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_and_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_ashrrev_i32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfe_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_bfe_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` + v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_class_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_eq_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_f_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ge_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_gt_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_le_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_lt_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_i16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_u16_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_ne_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_neq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_t_i32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_t_i64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_t_u32_e64 :ref:`src0`, :ref:`src1` - v_cmpx_t_u64_e64 :ref:`src0`, :ref:`src1` - v_cmpx_tru_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`ssrc2` - v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` - v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` - v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` - v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` - v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` :ref:`clamp` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` - v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` - v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` - v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fmac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` - v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` - v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` - v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` - v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` - v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` - v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` - v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` - v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mov_b32_e64 :ref:`vdst`, :ref:`src` - v_movreld_b32_e64 :ref:`vdst`, :ref:`src` - v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_2_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` - v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` - v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` - v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` - v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_lt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` + v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_class_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_eq_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_f_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ge_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_gt_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_le_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_lt_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u16_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_ne_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_neq_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_t_i32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_i64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_u32_e64 :ref:`src0`, :ref:`src1` + v_cmpx_t_u64_e64 :ref:`src0`, :ref:`src1` + v_cmpx_tru_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f16_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f32_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f64_e64 :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`ssrc2` + v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_norm_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_norm_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` + v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` + v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pknorm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f16`, :ref:`src1`::ref:`m`::ref:`f16` :ref:`op_sel` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` :ref:`clamp` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` + v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` + v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` + v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` + v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fmac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` + v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` + v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_lshl_add_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_lshl_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`::ref:`u32`, :ref:`src2` + v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` + v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`op_sel` :ref:`clamp` + v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` + v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`op_sel` :ref:`clamp` + v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` + v_max3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_med3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_med3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`op_sel` :ref:`clamp` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min3_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` + v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_min_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mov_b32_e64 :ref:`vdst`, :ref:`src` + v_movreld_b32_e64 :ref:`vdst`, :ref:`src` + v_movrels_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_2_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_movrelsd_b32_e64 :ref:`vdst`, :ref:`vsrc` + v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` + v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` :ref:`clamp` + v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_mullit_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_nop_e64 - v_not_b32_e64 :ref:`vdst`, :ref:`src` - v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` - v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_permlane16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` - v_permlanex16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` + v_not_b32_e64 :ref:`vdst`, :ref:`src` + v_or3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_pack_b32_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`op_sel` + v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_permlane16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` + v_permlanex16_b32 :ref:`vdst`, :ref:`vdata`, :ref:`ssrc1`, :ref:`ssrc2` :ref:`dpp_op_sel` v_pipeflush_e64 - v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` - v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` - v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` - v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sat_pk_u8_i16_e64 :ref:`vdst`::ref:`u8x4`, :ref:`src` - v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_sub_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` - v_sub_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_sub_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subrev_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` - v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_xor3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` + v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` + v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` + v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` + v_sat_pk_u8_i16_e64 :ref:`vdst`::ref:`u8x4`, :ref:`src` + v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_sub_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_nc_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`clamp` + v_sub_nc_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_nc_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_sub_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_co_ci_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` + v_subrev_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_nc_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` + v_xad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xnor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` + v_xor3_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` + v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` VOP3P ------------------------ +----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` - v_pk_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_fma_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` - v_pk_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` - v_pk_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` - v_pk_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_fma_mix_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixhi_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_fma_mixlo_f16 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`fx`, :ref:`src1`::ref:`m`::ref:`fx`, :ref:`src2`::ref:`m`::ref:`fx` :ref:`m_op_sel` :ref:`m_op_sel_hi` :ref:`clamp` + v_pk_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_add_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_fma_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16x2`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp` + v_pk_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` + v_pk_sub_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` + v_pk_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp` VOPC ------------------------ +---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_class_f16 :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f32 :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f64 :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_eq_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f64 :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f16 :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f32 :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f64 :ref:`src0`, :ref:`vsrc1` + v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` + v_cmpx_class_f16 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f32 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_class_f64 :ref:`src0`, :ref:`vsrc1`::ref:`b32` + v_cmpx_eq_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_eq_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_f_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ge_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_gt_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_le_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lg_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_lt_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ne_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_neq_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nge_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_ngt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nle_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlg_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_nlt_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_o_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_i64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_t_u64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_tru_f64 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f16 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f32 :ref:`src0`, :ref:`vsrc1` + v_cmpx_u_f64 :ref:`src0`, :ref:`vsrc1` .. |---| unicode:: U+02014 .. em dash @@ -2153,103 +2157,102 @@ VOPC gfx10_dst gfx10_fx_operand gfx10_hwreg - gfx10_imm16 - gfx10_imm16_1 - gfx10_imm16_2 + gfx10_imm16_73139a + gfx10_imm16_a04fb3 gfx10_label - gfx10_m - gfx10_m_1 + gfx10_m_254bcb + gfx10_m_f5d306 gfx10_msg gfx10_opt gfx10_param gfx10_probe - gfx10_saddr - gfx10_saddr_1 - gfx10_sbase - gfx10_sbase_1 - gfx10_sbase_2 - gfx10_sdata - gfx10_sdata_1 - gfx10_sdata_2 - gfx10_sdata_3 - gfx10_sdata_4 - gfx10_sdata_5 - gfx10_sdst - gfx10_sdst_1 - gfx10_sdst_2 - gfx10_sdst_3 - gfx10_sdst_4 - gfx10_sdst_5 - gfx10_sdst_6 - gfx10_sdst_7 - gfx10_sdst_8 - gfx10_simm32 - gfx10_simm32_1 - gfx10_simm32_2 - gfx10_soffset - gfx10_soffset_1 - gfx10_soffset_2 - gfx10_src - gfx10_src_1 - gfx10_src_2 - gfx10_src_3 - gfx10_src_4 - gfx10_src_5 - gfx10_src_6 - gfx10_src_7 - gfx10_src_8 - gfx10_srsrc - gfx10_srsrc_1 + gfx10_saddr_beaa25 + gfx10_saddr_da2a8a + gfx10_sbase_010ce0 + gfx10_sbase_020892 + gfx10_sbase_b2d796 + gfx10_sdata_3d2ab7 + gfx10_sdata_6fbc49 + gfx10_sdata_7cbd60 + gfx10_sdata_7e874d + gfx10_sdata_81ba27 + gfx10_sdata_c6aec1 + gfx10_sdst_0804b1 + gfx10_sdst_2e4c2a + gfx10_sdst_362c37 + gfx10_sdst_3759f6 + gfx10_sdst_386c33 + gfx10_sdst_3bc700 + gfx10_sdst_54e16e + gfx10_sdst_8078f5 + gfx10_sdst_ea3f10 + gfx10_simm32_6f0844 + gfx10_simm32_a3e80c + gfx10_simm32_be0c1c + gfx10_soffset_59fade + gfx10_soffset_b556e6 + gfx10_soffset_c40a5a + gfx10_src_37d670 + gfx10_src_516946 + gfx10_src_823582 + gfx10_src_c27036 + gfx10_src_cf1cda + gfx10_src_d5cd94 + gfx10_src_e0345d + gfx10_src_e9e6db + gfx10_srsrc_cf7132 + gfx10_srsrc_e73d16 gfx10_ssamp - gfx10_ssrc - gfx10_ssrc_1 - gfx10_ssrc_2 - gfx10_ssrc_3 - gfx10_ssrc_4 - gfx10_ssrc_5 - gfx10_ssrc_6 - gfx10_ssrc_7 - gfx10_ssrc_8 + gfx10_ssrc_054e2a + gfx10_ssrc_2a042f + gfx10_ssrc_3ec588 + gfx10_ssrc_460c63 + gfx10_ssrc_48e8e7 + gfx10_ssrc_6fbc49 + gfx10_ssrc_7da351 + gfx10_ssrc_81ba27 + gfx10_ssrc_9a4448 gfx10_tgt gfx10_type_deviation - gfx10_vaddr - gfx10_vaddr_1 - gfx10_vaddr_2 - gfx10_vaddr_3 - gfx10_vaddr_4 - gfx10_vaddr_5 + gfx10_vaddr_76b997 + gfx10_vaddr_9aeece + gfx10_vaddr_9f7133 + gfx10_vaddr_b73dc0 + gfx10_vaddr_cdc744 + gfx10_vaddr_f20ee4 gfx10_vcc - gfx10_vdata - gfx10_vdata0 - gfx10_vdata0_1 - gfx10_vdata1 - gfx10_vdata1_1 - gfx10_vdata_1 - gfx10_vdata_10 - gfx10_vdata_2 - gfx10_vdata_3 - gfx10_vdata_4 - gfx10_vdata_5 - gfx10_vdata_6 - gfx10_vdata_7 - gfx10_vdata_8 - gfx10_vdata_9 - gfx10_vdst - gfx10_vdst_1 - gfx10_vdst_10 - gfx10_vdst_11 - gfx10_vdst_12 - gfx10_vdst_13 - gfx10_vdst_2 - gfx10_vdst_3 - gfx10_vdst_4 - gfx10_vdst_5 - gfx10_vdst_6 - gfx10_vdst_7 - gfx10_vdst_8 - gfx10_vdst_9 - gfx10_vsrc - gfx10_vsrc_1 - gfx10_vsrc_2 - gfx10_vsrc_3 + gfx10_vdata0_6802ce + gfx10_vdata0_fd235e + gfx10_vdata1_6802ce + gfx10_vdata1_fd235e + gfx10_vdata_15d255 + gfx10_vdata_325b78 + gfx10_vdata_4d8ecf + gfx10_vdata_56f215 + gfx10_vdata_6802ce + gfx10_vdata_87fb90 + gfx10_vdata_b2a787 + gfx10_vdata_c08393 + gfx10_vdata_c61803 + gfx10_vdata_e016a1 + gfx10_vdata_fd235e + gfx10_vdst_3d7dcf + gfx10_vdst_463513 + gfx10_vdst_473a69 + gfx10_vdst_48d3a8 + gfx10_vdst_48e42f + gfx10_vdst_5d50a1 + gfx10_vdst_69a144 + gfx10_vdst_719833 + gfx10_vdst_89680f + gfx10_vdst_a49b76 + gfx10_vdst_bdb32f + gfx10_vdst_d0dc43 + gfx10_vdst_d7c57e + gfx10_vdst_f47754 + gfx10_vsrc_533a4e + gfx10_vsrc_6802ce + gfx10_vsrc_e016a1 + gfx10_vsrc_fd235e gfx10_waitcnt + gfx10_waitcnt_depctr diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst index 16b5990dadbe..c7c821ab2fff 100644 --- a/llvm/docs/AMDGPU/gfx10_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst @@ -41,27 +41,27 @@ or :ref:`absolute expressions`. Defined register *names* include: - =================== ========================================== - Name Description - =================== ========================================== - HW_REG_MODE Shader writeable mode bits. - HW_REG_STATUS Shader read-only status. - HW_REG_TRAPSTS Trap status. - HW_REG_HW_ID1 Id of wave, simd, compute unit, etc. - HW_REG_HW_ID2 Id of queue, pipeline, etc. - HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. - HW_REG_LDS_ALLOC Per-wave LDS allocation. - HW_REG_IB_STS Counters of outstanding instructions. - HW_REG_SH_MEM_BASES Memory aperture. - HW_REG_TBA_LO tba_lo register. - HW_REG_TBA_HI tba_hi register. - HW_REG_TMA_LO tma_lo register. - HW_REG_TMA_HI tma_hi register. - HW_REG_FLAT_SCR_LO flat_scratch_lo register. - HW_REG_FLAT_SCR_HI flat_scratch_hi register. - HW_REG_XNACK_MASK xnack_mask register. - HW_REG_POPS_PACKER pops_packer register. - =================== ========================================== + ==================== ========================================== + Name Description + ==================== ========================================== + HW_REG_MODE Shader writeable mode bits. + HW_REG_STATUS Shader read-only status. + HW_REG_TRAPSTS Trap status. + HW_REG_HW_ID1 Id of wave, simd, compute unit, etc. + HW_REG_HW_ID2 Id of queue, pipeline, etc. + HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation. + HW_REG_LDS_ALLOC Per-wave LDS allocation. + HW_REG_IB_STS Counters of outstanding instructions. + HW_REG_SH_MEM_BASES Memory aperture. + HW_REG_TBA_LO tba_lo register. + HW_REG_TBA_HI tba_hi register. + HW_REG_TMA_LO tma_lo register. + HW_REG_TMA_HI tma_hi register. + HW_REG_FLAT_SCR_LO flat_scratch_lo register. + HW_REG_FLAT_SCR_HI flat_scratch_hi register. + HW_REG_XNACK_MASK xnack_mask register. + HW_REG_POPS_PACKER pops_packer register. + ==================== ========================================== Examples: diff --git a/llvm/docs/AMDGPU/gfx10_imm16_2.rst b/llvm/docs/AMDGPU/gfx10_imm16_2.rst deleted file mode 100644 index 2500954a77ed..000000000000 --- a/llvm/docs/AMDGPU/gfx10_imm16_2.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid_gfx10_imm16_2: - -imm16 -===== - -A 16-bit :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. diff --git a/llvm/docs/AMDGPU/gfx10_imm16.rst b/llvm/docs/AMDGPU/gfx10_imm16_73139a.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_imm16.rst rename to llvm/docs/AMDGPU/gfx10_imm16_73139a.rst index 22d73ae5ecce..085b8c7a5742 100644 --- a/llvm/docs/AMDGPU/gfx10_imm16.rst +++ b/llvm/docs/AMDGPU/gfx10_imm16_73139a.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_imm16: +.. _amdgpu_synid_gfx10_imm16_73139a: imm16 ===== diff --git a/llvm/docs/AMDGPU/gfx10_imm16_1.rst b/llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_imm16_1.rst rename to llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst index ee2380386d3e..083654bf5431 100644 --- a/llvm/docs/AMDGPU/gfx10_imm16_1.rst +++ b/llvm/docs/AMDGPU/gfx10_imm16_a04fb3.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_imm16_1: +.. _amdgpu_synid_gfx10_imm16_a04fb3: imm16 ===== diff --git a/llvm/docs/AMDGPU/gfx10_m_1.rst b/llvm/docs/AMDGPU/gfx10_m_254bcb.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_m_1.rst rename to llvm/docs/AMDGPU/gfx10_m_254bcb.rst index b3f9d2f22e93..134854f0e8c3 100644 --- a/llvm/docs/AMDGPU/gfx10_m_1.rst +++ b/llvm/docs/AMDGPU/gfx10_m_254bcb.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_m_1: +.. _amdgpu_synid_gfx10_m_254bcb: m = diff --git a/llvm/docs/AMDGPU/gfx10_m.rst b/llvm/docs/AMDGPU/gfx10_m_f5d306.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_m.rst rename to llvm/docs/AMDGPU/gfx10_m_f5d306.rst index 8d4480bcf589..bfef084373c7 100644 --- a/llvm/docs/AMDGPU/gfx10_m.rst +++ b/llvm/docs/AMDGPU/gfx10_m_f5d306.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_m: +.. _amdgpu_synid_gfx10_m_f5d306: m = diff --git a/llvm/docs/AMDGPU/gfx10_msg.rst b/llvm/docs/AMDGPU/gfx10_msg.rst index 2ebd4f00cdf8..d72f53580b2f 100644 --- a/llvm/docs/AMDGPU/gfx10_msg.rst +++ b/llvm/docs/AMDGPU/gfx10_msg.rst @@ -47,29 +47,28 @@ or :ref:`absolute expressions`. Each message type supports specific operations: - =================== ========== ============================== ============ ========== - Message name Message Id Supported Operations Operation Id Stream Id - =================== ========== ============================== ============ ========== - MSG_INTERRUPT 1 \- \- \- - MSG_GS 2 GS_OP_CUT 1 Optional - \ GS_OP_EMIT 2 Optional - \ GS_OP_EMIT_CUT 3 Optional - MSG_GS_DONE 3 GS_OP_NOP 0 \- - \ GS_OP_CUT 1 Optional - \ GS_OP_EMIT 2 Optional - \ GS_OP_EMIT_CUT 3 Optional - MSG_SAVEWAVE 4 \- \- \- - MSG_STALL_WAVE_GEN 5 \- \- \- - MSG_HALT_WAVES 6 \- \- \- - MSG_ORDERED_PS_DONE 7 \- \- \- - MSG_GS_ALLOC_REQ 9 \- \- \- - MSG_GET_DOORBELL 10 \- \- \- - MSG_GET_DDID 11 \- \- \- - MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \- - \ SYSMSG_OP_REG_RD 2 \- - \ SYSMSG_OP_HOST_TRAP_ACK 3 \- - \ SYSMSG_OP_TTRACE_PC 4 \- - =================== ========== ============================== ============ ========== + ====================== ========== ============================== ============ ========== + Message name Message Id Supported Operations Operation Id Stream Id + ====================== ========== ============================== ============ ========== + MSG_INTERRUPT 1 \- \- \- + MSG_GS 2 GS_OP_CUT 1 Optional + \ GS_OP_EMIT 2 Optional + \ GS_OP_EMIT_CUT 3 Optional + MSG_GS_DONE 3 GS_OP_NOP 0 \- + \ GS_OP_CUT 1 Optional + \ GS_OP_EMIT 2 Optional + \ GS_OP_EMIT_CUT 3 Optional + MSG_SAVEWAVE 4 \- \- \- + MSG_STALL_WAVE_GEN 5 \- \- \- + MSG_HALT_WAVES 6 \- \- \- + MSG_ORDERED_PS_DONE 7 \- \- \- + MSG_GS_ALLOC_REQ 9 \- \- \- + MSG_GET_DOORBELL 10 \- \- \- + MSG_GET_DDID 11 \- \- \- + MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \- + \ SYSMSG_OP_REG_RD 2 \- + \ SYSMSG_OP_TTRACE_PC 4 \- + ====================== ========== ============================== ============ ========== *Sendmsg* arguments are validated depending on how *type* value is specified: diff --git a/llvm/docs/AMDGPU/gfx10_saddr.rst b/llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst similarity index 80% rename from llvm/docs/AMDGPU/gfx10_saddr.rst rename to llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst index 27d947ccfe02..7ede26f3665f 100644 --- a/llvm/docs/AMDGPU/gfx10_saddr.rst +++ b/llvm/docs/AMDGPU/gfx10_saddr_beaa25.rst @@ -5,14 +5,14 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_saddr: +.. _amdgpu_synid_gfx10_saddr_beaa25: saddr ===== An optional 64-bit flat global address. Must be specified as :ref:`off` if not used. -See :ref:`vaddr` for description of available addressing modes. +See :ref:`vaddr` for description of available addressing modes. *Size:* 2 dwords. diff --git a/llvm/docs/AMDGPU/gfx10_saddr_1.rst b/llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst similarity index 78% rename from llvm/docs/AMDGPU/gfx10_saddr_1.rst rename to llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst index ba860500d372..8e5e30c47311 100644 --- a/llvm/docs/AMDGPU/gfx10_saddr_1.rst +++ b/llvm/docs/AMDGPU/gfx10_saddr_da2a8a.rst @@ -5,14 +5,14 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_saddr_1: +.. _amdgpu_synid_gfx10_saddr_da2a8a: saddr ===== An optional 32-bit flat scratch offset. Must be specified as :ref:`off` if not used. -Either this operand or :ref:`vaddr` must be set to :ref:`off`. +Either this operand or :ref:`vaddr` must be set to :ref:`off`. *Size:* 1 dword. diff --git a/llvm/docs/AMDGPU/gfx10_sbase_1.rst b/llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_sbase_1.rst rename to llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst index ea58778a4363..3d3f6cee89ed 100644 --- a/llvm/docs/AMDGPU/gfx10_sbase_1.rst +++ b/llvm/docs/AMDGPU/gfx10_sbase_010ce0.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sbase_1: +.. _amdgpu_synid_gfx10_sbase_010ce0: sbase ===== diff --git a/llvm/docs/AMDGPU/gfx10_sbase.rst b/llvm/docs/AMDGPU/gfx10_sbase_020892.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_sbase.rst rename to llvm/docs/AMDGPU/gfx10_sbase_020892.rst index be764564eca4..292a3fad2300 100644 --- a/llvm/docs/AMDGPU/gfx10_sbase.rst +++ b/llvm/docs/AMDGPU/gfx10_sbase_020892.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sbase: +.. _amdgpu_synid_gfx10_sbase_020892: sbase ===== diff --git a/llvm/docs/AMDGPU/gfx10_sbase_2.rst b/llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_sbase_2.rst rename to llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst index 14a9a4bc0496..d22276370357 100644 --- a/llvm/docs/AMDGPU/gfx10_sbase_2.rst +++ b/llvm/docs/AMDGPU/gfx10_sbase_b2d796.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sbase_2: +.. _amdgpu_synid_gfx10_sbase_b2d796: sbase ===== diff --git a/llvm/docs/AMDGPU/gfx10_sdata.rst b/llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_sdata.rst rename to llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst index 3537824b06c7..d43311a68215 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_3d2ab7.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdata: +.. _amdgpu_synid_gfx10_sdata_3d2ab7: sdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_sdata_3.rst b/llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_sdata_3.rst rename to llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst index 38eedc59b338..f1b0f38eaba5 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata_3.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_6fbc49.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdata_3: +.. _amdgpu_synid_gfx10_sdata_6fbc49: sdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_sdata_5.rst b/llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_sdata_5.rst rename to llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst index 153153a2e068..0dee8e899885 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata_5.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_7cbd60.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdata_5: +.. _amdgpu_synid_gfx10_sdata_7cbd60: sdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_sdata_1.rst b/llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_sdata_1.rst rename to llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst index 96dc05038656..873e40c82a45 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata_1.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_7e874d.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdata_1: +.. _amdgpu_synid_gfx10_sdata_7e874d: sdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_sdata_4.rst b/llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_sdata_4.rst rename to llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst index 07fb5ff687a8..8804836bff69 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata_4.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_81ba27.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdata_4: +.. _amdgpu_synid_gfx10_sdata_81ba27: sdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_sdata_2.rst b/llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_sdata_2.rst rename to llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst index 22090af1cd38..70a8b62f1264 100644 --- a/llvm/docs/AMDGPU/gfx10_sdata_2.rst +++ b/llvm/docs/AMDGPU/gfx10_sdata_c6aec1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdata_2: +.. _amdgpu_synid_gfx10_sdata_c6aec1: sdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_4.rst b/llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_sdst_4.rst rename to llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst index 8f3d8da00d04..d82ffffcef68 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_4.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_0804b1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_4: +.. _amdgpu_synid_gfx10_sdst_0804b1: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_8.rst b/llvm/docs/AMDGPU/gfx10_sdst_2e4c2a.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_sdst_8.rst rename to llvm/docs/AMDGPU/gfx10_sdst_2e4c2a.rst index 572446119cd8..105346851f1e 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_8.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_2e4c2a.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_8: +.. _amdgpu_synid_gfx10_sdst_2e4c2a: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_5.rst b/llvm/docs/AMDGPU/gfx10_sdst_362c37.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_sdst_5.rst rename to llvm/docs/AMDGPU/gfx10_sdst_362c37.rst index 042ab9bd88b9..4e471a021669 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_5.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_362c37.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_5: +.. _amdgpu_synid_gfx10_sdst_362c37: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst.rst b/llvm/docs/AMDGPU/gfx10_sdst_3759f6.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_sdst.rst rename to llvm/docs/AMDGPU/gfx10_sdst_3759f6.rst index 18327a8646d1..4f45076cdfc3 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_3759f6.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst: +.. _amdgpu_synid_gfx10_sdst_3759f6: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_3.rst b/llvm/docs/AMDGPU/gfx10_sdst_386c33.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_sdst_3.rst rename to llvm/docs/AMDGPU/gfx10_sdst_386c33.rst index ba5378bd1100..56bf1cd15eb7 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_3.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_386c33.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_3: +.. _amdgpu_synid_gfx10_sdst_386c33: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_2.rst b/llvm/docs/AMDGPU/gfx10_sdst_3bc700.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_sdst_2.rst rename to llvm/docs/AMDGPU/gfx10_sdst_3bc700.rst index 657e8e92581c..d026ae29db42 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_2.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_3bc700.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_2: +.. _amdgpu_synid_gfx10_sdst_3bc700: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_1.rst b/llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_sdst_1.rst rename to llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst index 4fab64c9a16e..5577338f1f47 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_1.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_54e16e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_1: +.. _amdgpu_synid_gfx10_sdst_54e16e: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_6.rst b/llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_sdst_6.rst rename to llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst index 80f18caf85d3..8dbce94afc2a 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_6.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_8078f5.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_6: +.. _amdgpu_synid_gfx10_sdst_8078f5: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_sdst_7.rst b/llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_sdst_7.rst rename to llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst index 09ad3be1b829..dc6ea8aafba9 100644 --- a/llvm/docs/AMDGPU/gfx10_sdst_7.rst +++ b/llvm/docs/AMDGPU/gfx10_sdst_ea3f10.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_sdst_7: +.. _amdgpu_synid_gfx10_sdst_ea3f10: sdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_simm32_2.rst b/llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_simm32_2.rst rename to llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst index 24d3011fd606..7694283c4152 100644 --- a/llvm/docs/AMDGPU/gfx10_simm32_2.rst +++ b/llvm/docs/AMDGPU/gfx10_simm32_6f0844.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_simm32_2: +.. _amdgpu_synid_gfx10_simm32_6f0844: simm32 ====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. -The value is converted to *f32* as described :ref:`here`. +The value is converted to *f32* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx10_simm32.rst b/llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_simm32.rst rename to llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst index 44f1f517349e..5c487018426f 100644 --- a/llvm/docs/AMDGPU/gfx10_simm32.rst +++ b/llvm/docs/AMDGPU/gfx10_simm32_a3e80c.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_simm32: +.. _amdgpu_synid_gfx10_simm32_a3e80c: simm32 ====== diff --git a/llvm/docs/AMDGPU/gfx10_simm32_1.rst b/llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_simm32_1.rst rename to llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst index 54090bfedc8f..70a9acbb9ee7 100644 --- a/llvm/docs/AMDGPU/gfx10_simm32_1.rst +++ b/llvm/docs/AMDGPU/gfx10_simm32_be0c1c.rst @@ -5,10 +5,10 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_simm32_1: +.. _amdgpu_synid_gfx10_simm32_be0c1c: simm32 ====== A :ref:`floating-point_number`, an :ref:`integer_number`, or an :ref:`absolute_expression`. -The value is converted to *f16* as described :ref:`here`. +The value is converted to *f16* as described :ref:`here`. diff --git a/llvm/docs/AMDGPU/gfx10_soffset_2.rst b/llvm/docs/AMDGPU/gfx10_soffset_59fade.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_soffset_2.rst rename to llvm/docs/AMDGPU/gfx10_soffset_59fade.rst index 772d887bf217..1d5de435147e 100644 --- a/llvm/docs/AMDGPU/gfx10_soffset_2.rst +++ b/llvm/docs/AMDGPU/gfx10_soffset_59fade.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_soffset_2: +.. _amdgpu_synid_gfx10_soffset_59fade: soffset ======= diff --git a/llvm/docs/AMDGPU/gfx10_soffset.rst b/llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_soffset.rst rename to llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst index 0154df93ec84..d57506daede0 100644 --- a/llvm/docs/AMDGPU/gfx10_soffset.rst +++ b/llvm/docs/AMDGPU/gfx10_soffset_b556e6.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_soffset: +.. _amdgpu_synid_gfx10_soffset_b556e6: soffset ======= diff --git a/llvm/docs/AMDGPU/gfx10_soffset_1.rst b/llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_soffset_1.rst rename to llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst index b73e114d17d4..a3739bd6c6ed 100644 --- a/llvm/docs/AMDGPU/gfx10_soffset_1.rst +++ b/llvm/docs/AMDGPU/gfx10_soffset_c40a5a.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_soffset_1: +.. _amdgpu_synid_gfx10_soffset_c40a5a: soffset ======= diff --git a/llvm/docs/AMDGPU/gfx10_src.rst b/llvm/docs/AMDGPU/gfx10_src_37d670.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_src.rst rename to llvm/docs/AMDGPU/gfx10_src_37d670.rst index f83c11822c02..8c10a4cd3343 100644 --- a/llvm/docs/AMDGPU/gfx10_src.rst +++ b/llvm/docs/AMDGPU/gfx10_src_37d670.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src: +.. _amdgpu_synid_gfx10_src_37d670: src === diff --git a/llvm/docs/AMDGPU/gfx10_src_5.rst b/llvm/docs/AMDGPU/gfx10_src_516946.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_src_5.rst rename to llvm/docs/AMDGPU/gfx10_src_516946.rst index 44a447193cef..7c71f7713cc9 100644 --- a/llvm/docs/AMDGPU/gfx10_src_5.rst +++ b/llvm/docs/AMDGPU/gfx10_src_516946.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src_5: +.. _amdgpu_synid_gfx10_src_516946: src === diff --git a/llvm/docs/AMDGPU/gfx10_src_7.rst b/llvm/docs/AMDGPU/gfx10_src_7.rst deleted file mode 100644 index dffdab171432..000000000000 --- a/llvm/docs/AMDGPU/gfx10_src_7.rst +++ /dev/null @@ -1,17 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid_gfx10_src_7: - -src -=== - -Instruction input. - -*Size:* 1 dword. - -*Operands:* :ref:`v`, :ref:`s`, :ref:`vcc`, :ref:`ttmp`, :ref:`m0`, :ref:`exec`, :ref:`vccz`, :ref:`execz`, :ref:`scc`, :ref:`lds_direct`, :ref:`constant` diff --git a/llvm/docs/AMDGPU/gfx10_src_2.rst b/llvm/docs/AMDGPU/gfx10_src_823582.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_src_2.rst rename to llvm/docs/AMDGPU/gfx10_src_823582.rst index 9bd53ddb5412..7fd81565e649 100644 --- a/llvm/docs/AMDGPU/gfx10_src_2.rst +++ b/llvm/docs/AMDGPU/gfx10_src_823582.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src_2: +.. _amdgpu_synid_gfx10_src_823582: src === diff --git a/llvm/docs/AMDGPU/gfx10_src_8.rst b/llvm/docs/AMDGPU/gfx10_src_c27036.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_src_8.rst rename to llvm/docs/AMDGPU/gfx10_src_c27036.rst index 25297cfe91bd..9873fe20266d 100644 --- a/llvm/docs/AMDGPU/gfx10_src_8.rst +++ b/llvm/docs/AMDGPU/gfx10_src_c27036.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src_8: +.. _amdgpu_synid_gfx10_src_c27036: src === diff --git a/llvm/docs/AMDGPU/gfx10_src_6.rst b/llvm/docs/AMDGPU/gfx10_src_cf1cda.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_src_6.rst rename to llvm/docs/AMDGPU/gfx10_src_cf1cda.rst index b1b49b168de7..9f8896d5247b 100644 --- a/llvm/docs/AMDGPU/gfx10_src_6.rst +++ b/llvm/docs/AMDGPU/gfx10_src_cf1cda.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src_6: +.. _amdgpu_synid_gfx10_src_cf1cda: src === diff --git a/llvm/docs/AMDGPU/gfx10_src_3.rst b/llvm/docs/AMDGPU/gfx10_src_d5cd94.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_src_3.rst rename to llvm/docs/AMDGPU/gfx10_src_d5cd94.rst index a581d7b4c96c..021d91086e1e 100644 --- a/llvm/docs/AMDGPU/gfx10_src_3.rst +++ b/llvm/docs/AMDGPU/gfx10_src_d5cd94.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src_3: +.. _amdgpu_synid_gfx10_src_d5cd94: src === diff --git a/llvm/docs/AMDGPU/gfx10_src_1.rst b/llvm/docs/AMDGPU/gfx10_src_e0345d.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_src_1.rst rename to llvm/docs/AMDGPU/gfx10_src_e0345d.rst index 67fc1c59cf50..9ebd1627f29b 100644 --- a/llvm/docs/AMDGPU/gfx10_src_1.rst +++ b/llvm/docs/AMDGPU/gfx10_src_e0345d.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src_1: +.. _amdgpu_synid_gfx10_src_e0345d: src === diff --git a/llvm/docs/AMDGPU/gfx10_src_4.rst b/llvm/docs/AMDGPU/gfx10_src_e9e6db.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_src_4.rst rename to llvm/docs/AMDGPU/gfx10_src_e9e6db.rst index 6bbb235dcf5c..f04f555ed7cd 100644 --- a/llvm/docs/AMDGPU/gfx10_src_4.rst +++ b/llvm/docs/AMDGPU/gfx10_src_e9e6db.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_src_4: +.. _amdgpu_synid_gfx10_src_e9e6db: src === diff --git a/llvm/docs/AMDGPU/gfx10_srsrc.rst b/llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_srsrc.rst rename to llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst index 704c2b216512..e9996a2962b6 100644 --- a/llvm/docs/AMDGPU/gfx10_srsrc.rst +++ b/llvm/docs/AMDGPU/gfx10_srsrc_cf7132.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_srsrc: +.. _amdgpu_synid_gfx10_srsrc_cf7132: srsrc ===== diff --git a/llvm/docs/AMDGPU/gfx10_srsrc_1.rst b/llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_srsrc_1.rst rename to llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst index 11546818280d..824713d22444 100644 --- a/llvm/docs/AMDGPU/gfx10_srsrc_1.rst +++ b/llvm/docs/AMDGPU/gfx10_srsrc_e73d16.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_srsrc_1: +.. _amdgpu_synid_gfx10_srsrc_e73d16: srsrc ===== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_8.rst b/llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_ssrc_8.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst index 48a7e71b64ef..031ef2834898 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_8.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_054e2a.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_8: +.. _amdgpu_synid_gfx10_ssrc_054e2a: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_ssrc_1.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst index 96545ffc5767..37d63ed0a030 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_1.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_2a042f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_1: +.. _amdgpu_synid_gfx10_ssrc_2a042f: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_5.rst b/llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_ssrc_5.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst index e36c48f38e96..84d13edb40ac 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_5.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_3ec588.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_5: +.. _amdgpu_synid_gfx10_ssrc_3ec588: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_4.rst b/llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_ssrc_4.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst index f4aef373258b..47c4f9fc0592 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_4.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_460c63.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_4: +.. _amdgpu_synid_gfx10_ssrc_460c63: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_7.rst b/llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_ssrc_7.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst index 3507e8373b08..3c5f34e2a6fc 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_7.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_48e8e7.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_7: +.. _amdgpu_synid_gfx10_ssrc_48e8e7: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_2.rst b/llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_ssrc_2.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst index ee31917115f8..188a89c1cda0 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_2.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_6fbc49.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_2: +.. _amdgpu_synid_gfx10_ssrc_6fbc49: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc.rst b/llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_ssrc.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst index cdcb9e6b3692..2c0178654310 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_7da351.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc: +.. _amdgpu_synid_gfx10_ssrc_7da351: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_3.rst b/llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_ssrc_3.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst index aa4ff88d059a..c4a5e455b457 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_3.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_81ba27.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_3: +.. _amdgpu_synid_gfx10_ssrc_81ba27: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_ssrc_6.rst b/llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_ssrc_6.rst rename to llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst index 15972cf70274..fb5b471e2d61 100644 --- a/llvm/docs/AMDGPU/gfx10_ssrc_6.rst +++ b/llvm/docs/AMDGPU/gfx10_ssrc_9a4448.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_ssrc_6: +.. _amdgpu_synid_gfx10_ssrc_9a4448: ssrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_tgt.rst b/llvm/docs/AMDGPU/gfx10_tgt.rst index 342466a9863f..a8762c493f1c 100644 --- a/llvm/docs/AMDGPU/gfx10_tgt.rst +++ b/llvm/docs/AMDGPU/gfx10_tgt.rst @@ -12,13 +12,13 @@ tgt An export target: - ============== =================================== - Syntax Description - ============== =================================== - pos{0..4} Copy vertex position 0..4. - param{0..31} Copy vertex parameter 0..31. - mrt{0..7} Copy pixel color to the MRTs 0..7. - mrtz Copy pixel depth (Z) data. - prim Copy primitive (connectivity) data. - null Copy nothing. - ============== =================================== + ================== =================================== + Syntax Description + ================== =================================== + pos{0..4} Copy vertex position 0..4. + param{0..31} Copy vertex parameter 0..31. + mrt{0..7} Copy pixel color to the MRTs 0..7. + mrtz Copy pixel depth (Z) data. + prim Copy primitive (connectivity) data. + null Copy nothing. + ================== =================================== diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_2.rst b/llvm/docs/AMDGPU/gfx10_vaddr_2.rst deleted file mode 100644 index 1229618b509c..000000000000 --- a/llvm/docs/AMDGPU/gfx10_vaddr_2.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid_gfx10_vaddr_2: - -vaddr -===== - -A 64-bit flat global address or a 32-bit offset depending on addressing mode: - -* Address = :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 64-bit address. This mode is indicated by :ref:`saddr` set to :ref:`off`. -* Address = :ref:`saddr` + :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 32-bit offset. This mode is used when :ref:`saddr` is not :ref:`off`. - -*Size:* 1 or 2 dwords. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_3.rst b/llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst similarity index 76% rename from llvm/docs/AMDGPU/gfx10_vaddr_3.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst index c866483f5697..41334bb1c023 100644 --- a/llvm/docs/AMDGPU/gfx10_vaddr_3.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_76b997.rst @@ -5,14 +5,14 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vaddr_3: +.. _amdgpu_synid_gfx10_vaddr_76b997: vaddr ===== An optional 32-bit flat scratch offset. Must be specified as :ref:`off` if not used. -Either this operand or :ref:`saddr` must be set to :ref:`off`. +Either this operand or :ref:`saddr` must be set to :ref:`off`. *Size:* 1 dword. diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst b/llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst new file mode 100644 index 000000000000..5155f2cd1f28 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx10_vaddr_9aeece: + +vaddr +===== + +A 64-bit flat global address or a 32-bit offset depending on addressing mode: + +* Address = :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 64-bit address. This mode is indicated by :ref:`saddr` set to :ref:`off`. +* Address = :ref:`saddr` + :ref:`vaddr` + :ref:`offset12s`. :ref:`vaddr` is a 32-bit offset. This mode is used when :ref:`saddr` is not :ref:`off`. + +*Size:* 1 or 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_1.rst b/llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vaddr_1.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst index aca79412fd58..f4d1f3bff0cf 100644 --- a/llvm/docs/AMDGPU/gfx10_vaddr_1.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_9f7133.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vaddr_1: +.. _amdgpu_synid_gfx10_vaddr_9f7133: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_5.rst b/llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx10_vaddr_5.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst index c5c8f6492fa0..321a0eb414fe 100644 --- a/llvm/docs/AMDGPU/gfx10_vaddr_5.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_b73dc0.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vaddr_5: +.. _amdgpu_synid_gfx10_vaddr_b73dc0: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_4.rst b/llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx10_vaddr_4.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst index 3e6d0c8a2db0..1ae91d8e32d5 100644 --- a/llvm/docs/AMDGPU/gfx10_vaddr_4.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_cdc744.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vaddr_4: +.. _amdgpu_synid_gfx10_vaddr_cdc744: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx10_vaddr.rst b/llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vaddr.rst rename to llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst index e87fd388d692..7c4934bc775b 100644 --- a/llvm/docs/AMDGPU/gfx10_vaddr.rst +++ b/llvm/docs/AMDGPU/gfx10_vaddr_f20ee4.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vaddr: +.. _amdgpu_synid_gfx10_vaddr_f20ee4: vaddr ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata0.rst b/llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata0.rst rename to llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst index f660fa6296ef..6db65c6e052f 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata0.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata0_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata0: +.. _amdgpu_synid_gfx10_vdata0_6802ce: vdata0 ====== diff --git a/llvm/docs/AMDGPU/gfx10_vdata0_1.rst b/llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata0_1.rst rename to llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst index 10741bc5f8ed..5f370ebf4a07 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata0_1.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata0_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata0_1: +.. _amdgpu_synid_gfx10_vdata0_fd235e: vdata0 ====== diff --git a/llvm/docs/AMDGPU/gfx10_vdata1.rst b/llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata1.rst rename to llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst index a775bccfb35b..2bcfcad4a0fb 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata1.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata1_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata1: +.. _amdgpu_synid_gfx10_vdata1_6802ce: vdata1 ====== diff --git a/llvm/docs/AMDGPU/gfx10_vdata1_1.rst b/llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata1_1.rst rename to llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst index 1834fce9d807..7015045ae163 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata1_1.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata1_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata1_1: +.. _amdgpu_synid_gfx10_vdata1_fd235e: vdata1 ====== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_6.rst b/llvm/docs/AMDGPU/gfx10_vdata_15d255.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_vdata_6.rst rename to llvm/docs/AMDGPU/gfx10_vdata_15d255.rst index af43d4506924..c925debf162d 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_6.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_15d255.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_6: +.. _amdgpu_synid_gfx10_vdata_15d255: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_4.rst b/llvm/docs/AMDGPU/gfx10_vdata_325b78.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx10_vdata_4.rst rename to llvm/docs/AMDGPU/gfx10_vdata_325b78.rst index 4d922aaf524f..9f638b817e70 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_4.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_325b78.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_4: +.. _amdgpu_synid_gfx10_vdata_325b78: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_5.rst b/llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx10_vdata_5.rst rename to llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst index f23bb6b6ab29..1d8719869ff3 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_5.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_4d8ecf.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_5: +.. _amdgpu_synid_gfx10_vdata_4d8ecf: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_3.rst b/llvm/docs/AMDGPU/gfx10_vdata_56f215.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata_3.rst rename to llvm/docs/AMDGPU/gfx10_vdata_56f215.rst index 9b710c01f170..49083c413756 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_3.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_56f215.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_3: +.. _amdgpu_synid_gfx10_vdata_56f215: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata.rst b/llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata.rst rename to llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst index 38048c66d8ad..18c403d0a523 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata: +.. _amdgpu_synid_gfx10_vdata_6802ce: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_10.rst b/llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_vdata_10.rst rename to llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst index 31de91bc006f..82d8b6996060 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_10.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_87fb90.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_10: +.. _amdgpu_synid_gfx10_vdata_87fb90: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_9.rst b/llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_vdata_9.rst rename to llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst index 0f0be76806d6..d0d533eeada6 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_9.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_b2a787.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_9: +.. _amdgpu_synid_gfx10_vdata_b2a787: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_7.rst b/llvm/docs/AMDGPU/gfx10_vdata_c08393.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_vdata_7.rst rename to llvm/docs/AMDGPU/gfx10_vdata_c08393.rst index e157fb2b98e6..4c1ee2f5abfe 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_7.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_c08393.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_7: +.. _amdgpu_synid_gfx10_vdata_c08393: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_8.rst b/llvm/docs/AMDGPU/gfx10_vdata_c61803.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_vdata_8.rst rename to llvm/docs/AMDGPU/gfx10_vdata_c61803.rst index 83cefb82b62f..07401251683f 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_8.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_c61803.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_8: +.. _amdgpu_synid_gfx10_vdata_c61803: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_2.rst b/llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata_2.rst rename to llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst index 3cf264bea247..c8b2fca60e91 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_2.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_e016a1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_2: +.. _amdgpu_synid_gfx10_vdata_e016a1: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdata_1.rst b/llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst similarity index 90% rename from llvm/docs/AMDGPU/gfx10_vdata_1.rst rename to llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst index 2190149b49db..34cad64f0f6a 100644 --- a/llvm/docs/AMDGPU/gfx10_vdata_1.rst +++ b/llvm/docs/AMDGPU/gfx10_vdata_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdata_1: +.. _amdgpu_synid_gfx10_vdata_fd235e: vdata ===== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_7.rst b/llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst similarity index 94% rename from llvm/docs/AMDGPU/gfx10_vdst_7.rst rename to llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst index 425edaed52e7..d41833cc6555 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_7.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_3d7dcf.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_7: +.. _amdgpu_synid_gfx10_vdst_3d7dcf: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_5.rst b/llvm/docs/AMDGPU/gfx10_vdst_463513.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_vdst_5.rst rename to llvm/docs/AMDGPU/gfx10_vdst_463513.rst index 3aca2c1edc85..58ddf0b019d8 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_5.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_463513.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_5: +.. _amdgpu_synid_gfx10_vdst_463513: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_8.rst b/llvm/docs/AMDGPU/gfx10_vdst_473a69.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_vdst_8.rst rename to llvm/docs/AMDGPU/gfx10_vdst_473a69.rst index 1790e061d945..05832c35d0ef 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_8.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_473a69.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_8: +.. _amdgpu_synid_gfx10_vdst_473a69: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_6.rst b/llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_vdst_6.rst rename to llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst index c0ac63b7d514..70f713fb926b 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_6.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_48d3a8.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_6: +.. _amdgpu_synid_gfx10_vdst_48d3a8: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_3.rst b/llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vdst_3.rst rename to llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst index c910a331c03d..f6dcc3eda6c3 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_3.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_48e42f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_3: +.. _amdgpu_synid_gfx10_vdst_48e42f: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_9.rst b/llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_vdst_9.rst rename to llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst index 3d3cde2c2d6e..c24a7b0e3738 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_9.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_5d50a1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_9: +.. _amdgpu_synid_gfx10_vdst_5d50a1: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_2.rst b/llvm/docs/AMDGPU/gfx10_vdst_69a144.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vdst_2.rst rename to llvm/docs/AMDGPU/gfx10_vdst_69a144.rst index 31ead59c2c72..37b14bd2560d 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_2.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_69a144.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_2: +.. _amdgpu_synid_gfx10_vdst_69a144: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_13.rst b/llvm/docs/AMDGPU/gfx10_vdst_719833.rst similarity index 95% rename from llvm/docs/AMDGPU/gfx10_vdst_13.rst rename to llvm/docs/AMDGPU/gfx10_vdst_719833.rst index 49230f4231ce..2264b747b4b4 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_13.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_719833.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_13: +.. _amdgpu_synid_gfx10_vdst_719833: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst.rst b/llvm/docs/AMDGPU/gfx10_vdst_89680f.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vdst.rst rename to llvm/docs/AMDGPU/gfx10_vdst_89680f.rst index d541d96ba30f..4dc6770fd4f5 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_89680f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst: +.. _amdgpu_synid_gfx10_vdst_89680f: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_11.rst b/llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_vdst_11.rst rename to llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst index 4b63e79402c6..1a5d7028d483 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_11.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_a49b76.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_11: +.. _amdgpu_synid_gfx10_vdst_a49b76: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_1.rst b/llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vdst_1.rst rename to llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst index 45ab7f51b9bc..d34fb048940f 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_1.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_bdb32f.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_1: +.. _amdgpu_synid_gfx10_vdst_bdb32f: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_4.rst b/llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst similarity index 93% rename from llvm/docs/AMDGPU/gfx10_vdst_4.rst rename to llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst index 9f906f683248..5c9086d4b8c4 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_4.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_d0dc43.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_4: +.. _amdgpu_synid_gfx10_vdst_d0dc43: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_10.rst b/llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_vdst_10.rst rename to llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst index 063c5e300452..3cecfb2000cf 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_10.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_d7c57e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_10: +.. _amdgpu_synid_gfx10_vdst_d7c57e: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vdst_12.rst b/llvm/docs/AMDGPU/gfx10_vdst_f47754.rst similarity index 92% rename from llvm/docs/AMDGPU/gfx10_vdst_12.rst rename to llvm/docs/AMDGPU/gfx10_vdst_f47754.rst index 95948c1b2adf..d80d8899af53 100644 --- a/llvm/docs/AMDGPU/gfx10_vdst_12.rst +++ b/llvm/docs/AMDGPU/gfx10_vdst_f47754.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vdst_12: +.. _amdgpu_synid_gfx10_vdst_f47754: vdst ==== diff --git a/llvm/docs/AMDGPU/gfx10_vsrc_1.rst b/llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst similarity index 96% rename from llvm/docs/AMDGPU/gfx10_vsrc_1.rst rename to llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst index 8e6a7ba370c4..b45a62083265 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc_1.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc_533a4e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vsrc_1: +.. _amdgpu_synid_gfx10_vsrc_533a4e: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_vsrc.rst b/llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vsrc.rst rename to llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst index 48af0a29a717..320b97a473f2 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc_6802ce.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vsrc: +.. _amdgpu_synid_gfx10_vsrc_6802ce: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_vsrc_2.rst b/llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vsrc_2.rst rename to llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst index 67ef71bdeb7e..1ba1856f5889 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc_2.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc_e016a1.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vsrc_2: +.. _amdgpu_synid_gfx10_vsrc_e016a1: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_vsrc_3.rst b/llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst similarity index 91% rename from llvm/docs/AMDGPU/gfx10_vsrc_3.rst rename to llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst index 5ea851bf1fe1..50b7bed71716 100644 --- a/llvm/docs/AMDGPU/gfx10_vsrc_3.rst +++ b/llvm/docs/AMDGPU/gfx10_vsrc_fd235e.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx10_vsrc_3: +.. _amdgpu_synid_gfx10_vsrc_fd235e: vsrc ==== diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt.rst b/llvm/docs/AMDGPU/gfx10_waitcnt.rst index 405d94ab93df..982d3bda35bd 100644 --- a/llvm/docs/AMDGPU/gfx10_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx10_waitcnt.rst @@ -19,7 +19,7 @@ The bits of this operand have the following meaning: ========== ========= ================================================ ============ 15:14 3:0 VM_CNT: vector memory operations count. 0..63 \- 6:4 EXP_CNT: export count. 0..7 - \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15 + \- 13:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..63 ========== ========= ================================================ ============ This operand may be specified as one of the following: diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst b/llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst new file mode 100644 index 000000000000..dd0bd8e80666 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst @@ -0,0 +1,39 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx10_waitcnt_depctr: + +waitcnt_depctr +============== + +Dependency counters to wait for. + +This operand may be specified as one of the following: + +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. +* A combination of *symbolic values* described below. + + ======================== ======================== ================ ================= + Syntax Description Valid *N* Values Default *N* Value + ======================== ======================== ================ ================= + depctr_sa_sdst(<*N*>) Wait for SA_SDST <= N 0..1 1 + depctr_va_vdst(<*N*>) Wait for VA_VDST <= N 0..15 15 + depctr_va_sdst(<*N*>) Wait for VA_SDST <= N 0..7 7 + depctr_va_ssrc(<*N*>) Wait for VA_SSRC <= N 0..1 1 + depctr_va_vcc(<*N*>) Wait for VA_VCC <= N 0..1 1 + depctr_vm_vsrc(<*N*>) Wait for VM_VSRC <= N 0..7 7 + ======================== ======================== ================ ================= + + These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators. + +Examples: + +.. parsed-literal:: + + s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) + s_waitcnt_depctr depctr_sa_sdst(1) & depctr_va_vdst(1) + s_waitcnt_depctr depctr_va_vdst(3), depctr_va_sdst(5)