[Hexagon] Add Loop Alignment pass. (#83379)
Inspect a basic block and if its single basic block loop with a small number of instructions, set the Loop Alignment to 32 bytes. This will avoid the cache line break in the first packet of loop which will cause a stall per each execution of loop.
This commit is contained in:
Sumanth Gundapaneni
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8466ab98ca
commit
ca9d2e923b
@@ -1,5 +1,5 @@
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// REQUIRES: hexagon-registered-target
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// RUN: %clang_cc1 -triple hexagon-unknown-elf -target-cpu hexagonv65 -target-feature +hvxv65 -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang_cc1 -triple hexagon-unknown-elf -target-cpu hexagonv65 -target-feature +hvxv65 -target-feature +hvx-length128b -emit-llvm %s -o - | FileCheck %s
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void test() {
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int v64 __attribute__((__vector_size__(64)));
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@@ -43,6 +43,7 @@ add_llvm_target(HexagonCodeGen
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HexagonISelDAGToDAGHVX.cpp
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HexagonISelLowering.cpp
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HexagonISelLoweringHVX.cpp
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HexagonLoopAlign.cpp
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HexagonLoopIdiomRecognition.cpp
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HexagonMachineFunctionInfo.cpp
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HexagonMachineScheduler.cpp
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216
llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
Normal file
216
llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
Normal file
@@ -0,0 +1,216 @@
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//===----- HexagonLoopAlign.cpp - Generate loop alignment directives -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Inspect a basic block and if its single basic block loop with a small
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// number of instructions, set the prefLoopAlignment to 32 bytes (5).
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "hexagon-loop-align"
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#include "HexagonTargetMachine.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableLoopAlign("disable-hexagon-loop-align", cl::Hidden,
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cl::desc("Disable Hexagon loop alignment pass"));
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static cl::opt<uint32_t> HVXLoopAlignLimitUB(
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"hexagon-hvx-loop-align-limit-ub", cl::Hidden, cl::init(16),
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cl::desc("Set hexagon hvx loop upper bound align limit"));
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static cl::opt<uint32_t> TinyLoopAlignLimitUB(
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"hexagon-tiny-loop-align-limit-ub", cl::Hidden, cl::init(16),
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cl::desc("Set hexagon tiny-core loop upper bound align limit"));
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static cl::opt<uint32_t>
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LoopAlignLimitUB("hexagon-loop-align-limit-ub", cl::Hidden, cl::init(8),
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cl::desc("Set hexagon loop upper bound align limit"));
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static cl::opt<uint32_t>
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LoopAlignLimitLB("hexagon-loop-align-limit-lb", cl::Hidden, cl::init(4),
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cl::desc("Set hexagon loop lower bound align limit"));
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static cl::opt<uint32_t>
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LoopBndlAlignLimit("hexagon-loop-bundle-align-limit", cl::Hidden,
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cl::init(4),
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cl::desc("Set hexagon loop align bundle limit"));
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static cl::opt<uint32_t> TinyLoopBndlAlignLimit(
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"hexagon-tiny-loop-bundle-align-limit", cl::Hidden, cl::init(8),
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cl::desc("Set hexagon tiny-core loop align bundle limit"));
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static cl::opt<uint32_t>
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LoopEdgeThreshold("hexagon-loop-edge-threshold", cl::Hidden, cl::init(7500),
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cl::desc("Set hexagon loop align edge theshold"));
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namespace llvm {
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FunctionPass *createHexagonLoopAlign();
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void initializeHexagonLoopAlignPass(PassRegistry &);
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} // namespace llvm
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namespace {
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class HexagonLoopAlign : public MachineFunctionPass {
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const HexagonSubtarget *HST = nullptr;
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const TargetMachine *HTM = nullptr;
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const HexagonInstrInfo *HII = nullptr;
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public:
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static char ID;
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HexagonLoopAlign() : MachineFunctionPass(ID) {
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initializeHexagonLoopAlignPass(*PassRegistry::getPassRegistry());
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}
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bool shouldBalignLoop(MachineBasicBlock &BB, bool AboveThres);
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bool isSingleLoop(MachineBasicBlock &MBB);
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bool attemptToBalignSmallLoop(MachineFunction &MF, MachineBasicBlock &MBB);
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineBranchProbabilityInfo>();
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AU.addRequired<MachineBlockFrequencyInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return "Hexagon LoopAlign pass"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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char HexagonLoopAlign::ID = 0;
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bool HexagonLoopAlign::shouldBalignLoop(MachineBasicBlock &BB,
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bool AboveThres) {
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bool isVec = false;
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unsigned InstCnt = 0;
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unsigned BndlCnt = 0;
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for (MachineBasicBlock::instr_iterator II = BB.instr_begin(),
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IE = BB.instr_end();
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II != IE; ++II) {
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// End if the instruction is endloop.
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if (HII->isEndLoopN(II->getOpcode()))
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break;
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// Count the number of bundles.
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if (II->isBundle()) {
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BndlCnt++;
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continue;
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}
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// Skip over debug instructions.
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if (II->isDebugInstr())
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continue;
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// Check if there are any HVX instructions in loop.
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isVec |= HII->isHVXVec(*II);
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// Count the number of instructions.
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InstCnt++;
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}
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LLVM_DEBUG({
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dbgs() << "Bundle Count : " << BndlCnt << "\n";
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dbgs() << "Instruction Count : " << InstCnt << "\n";
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});
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unsigned LimitUB = 0;
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unsigned LimitBndl = LoopBndlAlignLimit;
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// The conditions in the order of priority.
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if (HST->isTinyCore()) {
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LimitUB = TinyLoopAlignLimitUB;
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LimitBndl = TinyLoopBndlAlignLimit;
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} else if (isVec)
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LimitUB = HVXLoopAlignLimitUB;
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else if (AboveThres)
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LimitUB = LoopAlignLimitUB;
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// if the upper bound is not set to a value, implies we didn't meet
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// the criteria.
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if (LimitUB == 0)
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return false;
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return InstCnt >= LoopAlignLimitLB && InstCnt <= LimitUB &&
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BndlCnt <= LimitBndl;
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}
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bool HexagonLoopAlign::isSingleLoop(MachineBasicBlock &MBB) {
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int Succs = MBB.succ_size();
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return (MBB.isSuccessor(&MBB) && (Succs == 2));
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}
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bool HexagonLoopAlign::attemptToBalignSmallLoop(MachineFunction &MF,
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MachineBasicBlock &MBB) {
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if (!isSingleLoop(MBB))
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return false;
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const MachineBranchProbabilityInfo *MBPI =
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&getAnalysis<MachineBranchProbabilityInfo>();
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const MachineBlockFrequencyInfo *MBFI =
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&getAnalysis<MachineBlockFrequencyInfo>();
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// Compute frequency of back edge,
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BlockFrequency BlockFreq = MBFI->getBlockFreq(&MBB);
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BranchProbability BrProb = MBPI->getEdgeProbability(&MBB, &MBB);
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BlockFrequency EdgeFreq = BlockFreq * BrProb;
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LLVM_DEBUG({
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dbgs() << "Loop Align Pass:\n";
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dbgs() << "\tedge with freq(" << EdgeFreq.getFrequency() << ")\n";
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});
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bool AboveThres = EdgeFreq.getFrequency() > LoopEdgeThreshold;
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if (shouldBalignLoop(MBB, AboveThres)) {
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// We found a loop, change its alignment to be 32 (5).
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MBB.setAlignment(llvm::Align(1 << 5));
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return true;
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}
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return false;
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}
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// Inspect each basic block, and if its a single BB loop, see if it
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// meets the criteria for increasing alignment to 32.
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bool HexagonLoopAlign::runOnMachineFunction(MachineFunction &MF) {
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HST = &MF.getSubtarget<HexagonSubtarget>();
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HII = HST->getInstrInfo();
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HTM = &MF.getTarget();
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if (skipFunction(MF.getFunction()))
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return false;
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if (DisableLoopAlign)
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return false;
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// This optimization is performed at
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// i) -O2 and above, and when the loop has a HVX instruction.
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// ii) -O3
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if (HST->useHVXOps()) {
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if (HTM->getOptLevel() < CodeGenOptLevel::Default)
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return false;
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} else {
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if (HTM->getOptLevel() < CodeGenOptLevel::Aggressive)
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return false;
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}
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bool Changed = false;
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for (MachineFunction::iterator MBBi = MF.begin(), MBBe = MF.end();
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MBBi != MBBe; ++MBBi) {
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MachineBasicBlock &MBB = *MBBi;
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Changed |= attemptToBalignSmallLoop(MF, MBB);
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}
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return Changed;
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}
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} // namespace
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INITIALIZE_PASS(HexagonLoopAlign, "hexagon-loop-align",
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"Hexagon LoopAlign pass", false, false)
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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FunctionPass *llvm::createHexagonLoopAlign() { return new HexagonLoopAlign(); }
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@@ -164,6 +164,7 @@ namespace llvm {
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void initializeHexagonGenMuxPass(PassRegistry&);
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void initializeHexagonHardwareLoopsPass(PassRegistry&);
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void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
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void initializeHexagonLoopAlignPass(PassRegistry &);
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void initializeHexagonNewValueJumpPass(PassRegistry&);
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void initializeHexagonOptAddrModePass(PassRegistry&);
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void initializeHexagonPacketizerPass(PassRegistry&);
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@@ -194,6 +195,7 @@ namespace llvm {
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOptLevel OptLevel);
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FunctionPass *createHexagonLoopAlign();
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FunctionPass *createHexagonLoopRescheduling();
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FunctionPass *createHexagonNewValueJump();
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FunctionPass *createHexagonOptAddrMode();
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@@ -256,8 +258,10 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
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TT, CPU, FS, Options, getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small),
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(HexagonNoOpt ? CodeGenOptLevel::None : OL)),
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TLOF(std::make_unique<HexagonTargetObjectFile>()) {
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TLOF(std::make_unique<HexagonTargetObjectFile>()),
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Subtarget(Triple(TT), CPU, FS, *this) {
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initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
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initializeHexagonLoopAlignPass(*PassRegistry::getPassRegistry());
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initializeHexagonTfrCleanupPass(*PassRegistry::getPassRegistry());
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initAsmInfo();
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}
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@@ -476,6 +480,9 @@ void HexagonPassConfig::addPreEmitPass() {
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// Packetization is mandatory: it handles gather/scatter at all opt levels.
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addPass(createHexagonPacketizer(NoOpt));
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if (!NoOpt)
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addPass(createHexagonLoopAlign());
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if (EnableVectorPrint)
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addPass(createHexagonVectorPrint());
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@@ -23,6 +23,7 @@ namespace llvm {
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class HexagonTargetMachine : public LLVMTargetMachine {
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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HexagonSubtarget Subtarget;
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mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
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public:
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91
llvm/test/CodeGen/Hexagon/loop-balign.ll
Normal file
91
llvm/test/CodeGen/Hexagon/loop-balign.ll
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@@ -0,0 +1,91 @@
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; RUN: llc -march=hexagon -O3 < %s | FileCheck %s -check-prefix=BALIGN
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; BALIGN: .p2align{{.*}}5
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; The test for checking the alignment of 'for.body4.for.body4_crit_edge' basic block
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define dso_local void @foo(i32 %nCol, i32 %nRow, ptr nocapture %resMat) local_unnamed_addr {
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entry:
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%shl = shl i32 %nRow, 2
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%cmp36 = icmp sgt i32 %nRow, 0
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%0 = add i32 %nCol, -1
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%.inv = icmp slt i32 %0, 1
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%1 = select i1 %.inv, i32 1, i32 %nCol
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br label %Outerloop
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Outerloop: ; preds = %for.end7, %entry
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%r12.0 = phi i32 [ 0, %entry ], [ %inc8, %for.end7 ]
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%r7_6.0 = phi i64 [ undef, %entry ], [ %r7_6.1.lcssa, %for.end7 ]
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%r0i.0 = phi i32 [ undef, %entry ], [ %r0i.1.lcssa, %for.end7 ]
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%r5.0 = phi ptr [ %resMat, %entry ], [ %r5.1.lcssa, %for.end7 ]
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%r8.0 = phi i32 [ %shl, %entry ], [ %r8.1.lcssa, %for.end7 ]
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br i1 %cmp36, label %for.body.lr.ph, label %for.end7
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for.body.lr.ph: ; preds = %Outerloop
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%cmp332 = icmp eq i32 %r12.0, 0
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%exitcond.peel = icmp eq i32 %r12.0, 1
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br label %for.body
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for.body: ; preds = %for.end, %for.body.lr.ph
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%r8.141 = phi i32 [ %r8.0, %for.body.lr.ph ], [ %add, %for.end ]
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%r5.140 = phi ptr [ %r5.0, %for.body.lr.ph ], [ %add.ptr, %for.end ]
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%i.039 = phi i32 [ 0, %for.body.lr.ph ], [ %inc6, %for.end ]
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%r0i.138 = phi i32 [ %r0i.0, %for.body.lr.ph ], [ %4, %for.end ]
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%r7_6.137 = phi i64 [ %r7_6.0, %for.body.lr.ph ], [ %r7_6.2.lcssa, %for.end ]
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%add = add nsw i32 %r8.141, %shl
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br i1 %cmp332, label %for.end, label %for.body4.peel
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for.body4.peel: ; preds = %for.body
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%r1i.0.in.peel = inttoptr i32 %r8.141 to ptr
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%r1i.0.peel = load i32, ptr %r1i.0.in.peel, align 4
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%2 = tail call i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64 %r7_6.137, i32 %r1i.0.peel, i32 %r0i.138)
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br i1 %exitcond.peel, label %for.end, label %for.body4.preheader.peel.newph
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for.body4.preheader.peel.newph: ; preds = %for.body4.peel
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%r1i.0.in = inttoptr i32 %add to ptr
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%r1i.0 = load i32, ptr %r1i.0.in, align 4
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br label %for.body4
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for.body4: ; preds = %for.body4.for.body4_crit_edge, %for.body4.preheader.peel.newph
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%inc.phi = phi i32 [ %inc.0, %for.body4.for.body4_crit_edge ], [ 2, %for.body4.preheader.peel.newph ]
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%r7_6.233 = phi i64 [ %3, %for.body4.for.body4_crit_edge ], [ %2, %for.body4.preheader.peel.newph ]
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%3 = tail call i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64 %r7_6.233, i32 %r1i.0, i32 %r0i.138)
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%exitcond = icmp eq i32 %inc.phi, %r12.0
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br i1 %exitcond, label %for.end.loopexit, label %for.body4.for.body4_crit_edge
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for.body4.for.body4_crit_edge: ; preds = %for.body4
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%inc.0 = add nuw nsw i32 %inc.phi, 1
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br label %for.body4
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for.end.loopexit: ; preds = %for.body4
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br label %for.end
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for.end: ; preds = %for.end.loopexit, %for.body4.peel, %for.body
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%r7_6.2.lcssa = phi i64 [ %r7_6.137, %for.body ], [ %2, %for.body4.peel ], [ %3, %for.end.loopexit ]
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%4 = tail call i32 @llvm.hexagon.S2.clbp(i64 %r7_6.2.lcssa)
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store i32 %4, ptr %r5.140, align 4
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%add.ptr = getelementptr inbounds i8, ptr %r5.140, i32 undef
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%inc6 = add nuw nsw i32 %i.039, 1
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%exitcond47 = icmp eq i32 %inc6, %nRow
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br i1 %exitcond47, label %for.end7.loopexit, label %for.body
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for.end7.loopexit: ; preds = %for.end
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br label %for.end7
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for.end7: ; preds = %for.end7.loopexit, %Outerloop
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%r7_6.1.lcssa = phi i64 [ %r7_6.0, %Outerloop ], [ %r7_6.2.lcssa, %for.end7.loopexit ]
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%r0i.1.lcssa = phi i32 [ %r0i.0, %Outerloop ], [ %4, %for.end7.loopexit ]
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%r5.1.lcssa = phi ptr [ %r5.0, %Outerloop ], [ %add.ptr, %for.end7.loopexit ]
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%r8.1.lcssa = phi i32 [ %r8.0, %Outerloop ], [ %add, %for.end7.loopexit ]
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%inc8 = add nuw i32 %r12.0, 1
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%exitcond48 = icmp eq i32 %inc8, %1
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br i1 %exitcond48, label %if.end, label %Outerloop
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if.end: ; preds = %for.end7
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64, i32, i32)
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.clbp(i64)
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115
llvm/test/CodeGen/Hexagon/loop_align_count.ll
Normal file
115
llvm/test/CodeGen/Hexagon/loop_align_count.ll
Normal file
@@ -0,0 +1,115 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv73 -O2 -mattr=+hvxv73,hvx-length64b \
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; RUN: -debug-only=hexagon-loop-align 2>&1 < %s | FileCheck %s
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; Validate that there are 4 bundles in the loop.
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; CHECK: Loop Align Pass:
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; CHECK: Bundle Count : 4
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; CHECK: .p2align{{.*}}5
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; Function Attrs: nounwind
|
||||
define void @ham(ptr noalias nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, ptr noalias nocapture %arg4, i32 %arg5) #0 {
|
||||
bb:
|
||||
%ashr = ashr i32 %arg3, 2
|
||||
%ashr6 = ashr i32 %arg3, 1
|
||||
%add = add nsw i32 %ashr6, %ashr
|
||||
%icmp = icmp sgt i32 %arg2, 0
|
||||
br i1 %icmp, label %bb7, label %bb61
|
||||
|
||||
bb7: ; preds = %bb
|
||||
%sdiv = sdiv i32 %arg1, 64
|
||||
%icmp8 = icmp sgt i32 %arg1, 63
|
||||
br label %bb9
|
||||
|
||||
bb9: ; preds = %bb57, %bb7
|
||||
%phi = phi i32 [ 0, %bb7 ], [ %add58, %bb57 ]
|
||||
%ashr10 = ashr exact i32 %phi, 1
|
||||
%mul = mul nsw i32 %ashr10, %arg3
|
||||
br i1 %icmp8, label %bb11, label %bb57
|
||||
|
||||
bb11: ; preds = %bb9
|
||||
%add12 = add nsw i32 %phi, 1
|
||||
%mul13 = mul nsw i32 %add12, %arg5
|
||||
%mul14 = mul nsw i32 %phi, %arg5
|
||||
%add15 = add i32 %add, %mul
|
||||
%add16 = add i32 %mul, %ashr
|
||||
%add17 = add i32 %mul, %ashr6
|
||||
%getelementptr = getelementptr inbounds i8, ptr %arg4, i32 %mul13
|
||||
%getelementptr18 = getelementptr inbounds i8, ptr %arg4, i32 %mul14
|
||||
%getelementptr19 = getelementptr inbounds i16, ptr %arg, i32 %add15
|
||||
%getelementptr20 = getelementptr inbounds i16, ptr %arg, i32 %add16
|
||||
%getelementptr21 = getelementptr inbounds i16, ptr %arg, i32 %add17
|
||||
%getelementptr22 = getelementptr inbounds i16, ptr %arg, i32 %mul
|
||||
%bitcast = bitcast ptr %getelementptr to ptr
|
||||
%bitcast23 = bitcast ptr %getelementptr18 to ptr
|
||||
%bitcast24 = bitcast ptr %getelementptr19 to ptr
|
||||
%bitcast25 = bitcast ptr %getelementptr20 to ptr
|
||||
%bitcast26 = bitcast ptr %getelementptr21 to ptr
|
||||
%bitcast27 = bitcast ptr %getelementptr22 to ptr
|
||||
br label %bb28
|
||||
|
||||
bb28: ; preds = %bb28, %bb11
|
||||
%phi29 = phi i32 [ 0, %bb11 ], [ %add54, %bb28 ]
|
||||
%phi30 = phi ptr [ %bitcast27, %bb11 ], [ %getelementptr36, %bb28 ]
|
||||
%phi31 = phi ptr [ %bitcast26, %bb11 ], [ %getelementptr37, %bb28 ]
|
||||
%phi32 = phi ptr [ %bitcast25, %bb11 ], [ %getelementptr39, %bb28 ]
|
||||
%phi33 = phi ptr [ %bitcast24, %bb11 ], [ %getelementptr41, %bb28 ]
|
||||
%phi34 = phi ptr [ %bitcast, %bb11 ], [ %getelementptr53, %bb28 ]
|
||||
%phi35 = phi ptr [ %bitcast23, %bb11 ], [ %getelementptr52, %bb28 ]
|
||||
%getelementptr36 = getelementptr inbounds <16 x i32>, ptr %phi30, i32 1
|
||||
%load = load <16 x i32>, ptr %phi30, align 64
|
||||
%getelementptr37 = getelementptr inbounds <16 x i32>, ptr %phi31, i32 1
|
||||
%load38 = load <16 x i32>, ptr %phi31, align 64
|
||||
%getelementptr39 = getelementptr inbounds <16 x i32>, ptr %phi32, i32 1
|
||||
%load40 = load <16 x i32>, ptr %phi32, align 64
|
||||
%getelementptr41 = getelementptr inbounds <16 x i32>, ptr %phi33, i32 1
|
||||
%load42 = load <16 x i32>, ptr %phi33, align 64
|
||||
%call = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %load, <16 x i32> %load38)
|
||||
%call43 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %load, <16 x i32> %load38)
|
||||
%call44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %load40, <16 x i32> %load42)
|
||||
%call45 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %load40, <16 x i32> %load42)
|
||||
%call46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %call, <16 x i32> %call44)
|
||||
%call47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %call, <16 x i32> %call44)
|
||||
%call48 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %call43, <16 x i32> %call45)
|
||||
%call49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %call43, <16 x i32> %call45)
|
||||
%call50 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %call47, <16 x i32> %call46)
|
||||
%call51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %call49, <16 x i32> %call48)
|
||||
%getelementptr52 = getelementptr inbounds <16 x i32>, ptr %phi35, i32 1
|
||||
store <16 x i32> %call50, ptr %phi35, align 64
|
||||
%getelementptr53 = getelementptr inbounds <16 x i32>, ptr %phi34, i32 1
|
||||
store <16 x i32> %call51, ptr %phi34, align 64
|
||||
%add54 = add nsw i32 %phi29, 1
|
||||
%icmp55 = icmp slt i32 %add54, %sdiv
|
||||
br i1 %icmp55, label %bb28, label %bb56
|
||||
|
||||
bb56: ; preds = %bb28
|
||||
br label %bb57
|
||||
|
||||
bb57: ; preds = %bb56, %bb9
|
||||
%add58 = add nsw i32 %phi, 2
|
||||
%icmp59 = icmp slt i32 %add58, %arg2
|
||||
br i1 %icmp59, label %bb9, label %bb60
|
||||
|
||||
bb60: ; preds = %bb57
|
||||
br label %bb61
|
||||
|
||||
bb61: ; preds = %bb60, %bb
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
|
||||
130
llvm/test/CodeGen/Hexagon/loop_align_count.mir
Normal file
130
llvm/test/CodeGen/Hexagon/loop_align_count.mir
Normal file
@@ -0,0 +1,130 @@
|
||||
# RUN: llc -march=hexagon -O3 -run-pass hexagon-loop-align -o - %s\
|
||||
# RUN: -debug-only=hexagon-loop-align -verify-machineinstrs 2>&1 | FileCheck %s
|
||||
|
||||
# Test that we only count til endloop instruction and we align this
|
||||
# loop to 32.
|
||||
# CHECK: Loop Align Pass:
|
||||
# CHECK: Instruction Count : 16
|
||||
# CHECK: bb.5 (align 32)
|
||||
---
|
||||
name: fred
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1(0x50000000), %bb.8(0x30000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r4, $r5
|
||||
|
||||
renamable $p0 = C2_cmpgti renamable $r2, 0
|
||||
J2_jumpf killed renamable $p0, %bb.8, implicit-def dead $pc
|
||||
J2_jump %bb.1, implicit-def dead $pc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r4, $r5
|
||||
|
||||
renamable $r7 = A2_addi killed renamable $r2, 1
|
||||
renamable $r8 = S2_asr_i_r renamable $r1, 31
|
||||
renamable $p0 = C2_cmpgti renamable $r1, 63
|
||||
renamable $r2 = S2_asr_i_r renamable $r3, 2
|
||||
renamable $r6 = S2_asr_i_r renamable $r3, 1
|
||||
renamable $r9 = S2_lsr_i_r killed renamable $r7, 1
|
||||
renamable $r1 = S2_lsr_i_r_acc killed renamable $r1, killed renamable $r8, 26
|
||||
renamable $r7 = A2_tfrsi 0
|
||||
renamable $r1 = S2_asr_i_r killed renamable $r1, 6
|
||||
J2_loop1r %bb.2, killed renamable $r9, implicit-def $lc1, implicit-def $sa1
|
||||
renamable $r8 = nsw A2_add renamable $r6, renamable $r2
|
||||
|
||||
bb.2:
|
||||
successors: %bb.3(0x40000000), %bb.7(0x40000000)
|
||||
liveins: $p0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8
|
||||
|
||||
J2_jumpf renamable $p0, %bb.7, implicit-def dead $pc
|
||||
J2_jump %bb.3, implicit-def dead $pc
|
||||
|
||||
bb.3:
|
||||
successors: %bb.4(0x80000000)
|
||||
liveins: $p0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8
|
||||
|
||||
renamable $r13 = exact S2_asr_i_r renamable $r7, 1
|
||||
renamable $r12 = COPY renamable $r4
|
||||
renamable $r9 = COPY renamable $r4
|
||||
renamable $r14 = nsw A2_addi renamable $r7, 1
|
||||
renamable $r15 = nsw M2_mpyi killed renamable $r13, renamable $r3
|
||||
renamable $r9 = M2_maci killed renamable $r9, killed renamable $r14, renamable $r5
|
||||
renamable $r13 = A2_add renamable $r8, renamable $r15
|
||||
renamable $r28 = A2_add renamable $r15, renamable $r2
|
||||
renamable $r10 = A2_add renamable $r15, renamable $r6
|
||||
renamable $r12 = M2_maci killed renamable $r12, renamable $r7, renamable $r5
|
||||
renamable $r13 = S2_addasl_rrri renamable $r0, killed renamable $r13, 1
|
||||
renamable $r14 = S2_addasl_rrri renamable $r0, killed renamable $r15, 1
|
||||
renamable $r15 = S2_addasl_rrri renamable $r0, killed renamable $r28, 1
|
||||
renamable $r28 = S2_addasl_rrri renamable $r0, killed renamable $r10, 1
|
||||
|
||||
bb.4:
|
||||
successors: %bb.5(0x40000000), %bb.6(0x40000000)
|
||||
liveins: $p0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r13, $r14, $r15, $r28
|
||||
|
||||
renamable $v0, renamable $r14 = V6_vL32b_pi killed renamable $r14, 64
|
||||
renamable $p1 = C2_cmpgtui renamable $r1, 1
|
||||
renamable $r10 = A2_addi renamable $r1, -1
|
||||
renamable $v2, renamable $r28 = V6_vL32b_pi killed renamable $r28, 64
|
||||
renamable $v1 = V6_vaddh renamable $v0, renamable $v2
|
||||
renamable $v3, renamable $r15 = V6_vL32b_pi killed renamable $r15, 64
|
||||
renamable $v0 = V6_vsubh killed renamable $v0, killed renamable $v2
|
||||
J2_loop0r %bb.5, killed renamable $r10, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
|
||||
renamable $v4, renamable $r13 = V6_vL32b_pi killed renamable $r13, 64
|
||||
renamable $v2 = V6_vaddh renamable $v3, renamable $v4
|
||||
J2_jumpf killed renamable $p1, %bb.6, implicit-def $pc
|
||||
J2_jump %bb.5, implicit-def $pc
|
||||
|
||||
bb.5:
|
||||
successors: %bb.5(0x7c000000), %bb.6(0x04000000)
|
||||
liveins: $p0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r13, $r14, $r15, $r28, $v0, $v1, $v2, $v3, $v4
|
||||
|
||||
renamable $v3 = V6_vsubh killed renamable $v3, killed renamable $v4
|
||||
renamable $v4, renamable $r14 = V6_vL32b_pi killed renamable $r14, 64
|
||||
renamable $v5 = V6_vnavgh renamable $v1, renamable $v2
|
||||
renamable $v1 = V6_vavgh killed renamable $v1, killed renamable $v2
|
||||
renamable $v2, renamable $r28 = V6_vL32b_pi killed renamable $r28, 64
|
||||
renamable $v1 = V6_vsathub killed renamable $v5, killed renamable $v1
|
||||
renamable $v5 = V6_vnavgh renamable $v0, renamable $v3
|
||||
renamable $v6 = V6_vavgh killed renamable $v0, killed renamable $v3
|
||||
renamable $r12 = V6_vS32b_pi killed renamable $r12, 64, killed renamable $v1
|
||||
renamable $v1 = V6_vaddh renamable $v4, renamable $v2
|
||||
renamable $v3, renamable $r15 = V6_vL32b_pi killed renamable $r15, 64
|
||||
renamable $v0 = V6_vsubh killed renamable $v4, killed renamable $v2
|
||||
renamable $v4, renamable $r13 = V6_vL32b_pi killed renamable $r13, 64
|
||||
renamable $v2 = V6_vaddh renamable $v3, renamable $v4
|
||||
renamable $v5 = V6_vsathub killed renamable $v5, killed renamable $v6
|
||||
renamable $r9 = V6_vS32b_pi killed renamable $r9, 64, killed renamable $v5
|
||||
ENDLOOP0 %bb.5, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
|
||||
J2_jump %bb.6, implicit-def $pc
|
||||
|
||||
bb.6:
|
||||
successors: %bb.7(0x80000000)
|
||||
liveins: $p0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $v0, $v1, $v2, $v3, $v4
|
||||
|
||||
renamable $v3 = V6_vsubh killed renamable $v3, killed renamable $v4
|
||||
renamable $v4 = V6_vavgh renamable $v1, renamable $v2
|
||||
renamable $v1 = V6_vnavgh killed renamable $v1, killed renamable $v2
|
||||
renamable $v2 = V6_vavgh renamable $v0, renamable $v3
|
||||
renamable $v0 = V6_vnavgh killed renamable $v0, killed renamable $v3
|
||||
renamable $v1 = V6_vsathub killed renamable $v1, killed renamable $v4
|
||||
dead renamable $r12 = V6_vS32b_pi killed renamable $r12, 64, killed renamable $v1
|
||||
renamable $v0 = V6_vsathub killed renamable $v0, killed renamable $v2
|
||||
dead renamable $r9 = V6_vS32b_pi killed renamable $r9, 64, killed renamable $v0
|
||||
J2_jump %bb.7, implicit-def $pc
|
||||
|
||||
bb.7:
|
||||
successors: %bb.2(0x7c000000), %bb.8(0x04000000)
|
||||
liveins: $p0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8
|
||||
|
||||
renamable $r7 = nsw A2_addi killed renamable $r7, 2
|
||||
ENDLOOP1 %bb.2, implicit-def $pc, implicit-def $lc1, implicit $sa1, implicit $lc1
|
||||
J2_jump %bb.8, implicit-def dead $pc
|
||||
|
||||
bb.8:
|
||||
PS_jmpret $r31, implicit-def dead $pc
|
||||
|
||||
...
|
||||
117
llvm/test/CodeGen/Hexagon/v6-haar-balign32.ll
Normal file
117
llvm/test/CodeGen/Hexagon/v6-haar-balign32.ll
Normal file
@@ -0,0 +1,117 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv73 -O2 -mattr=+hvxv73,hvx-length64b < %s | FileCheck %s
|
||||
; CHECK: .p2align{{.*}}5
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @wobble(ptr noalias nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, ptr noalias nocapture %arg4, i32 %arg5) #0 {
|
||||
bb:
|
||||
%ashr = ashr i32 %arg3, 2
|
||||
%ashr6 = ashr i32 %arg3, 1
|
||||
%add = add nsw i32 %ashr6, %ashr
|
||||
%icmp = icmp sgt i32 %arg2, 0
|
||||
br i1 %icmp, label %bb7, label %bb61
|
||||
|
||||
bb7: ; preds = %bb
|
||||
%sdiv = sdiv i32 %arg1, 64
|
||||
%icmp8 = icmp sgt i32 %arg1, 63
|
||||
br label %bb9
|
||||
|
||||
bb9: ; preds = %bb57, %bb7
|
||||
%phi = phi i32 [ 0, %bb7 ], [ %add58, %bb57 ]
|
||||
%ashr10 = ashr exact i32 %phi, 1
|
||||
%mul = mul nsw i32 %ashr10, %arg3
|
||||
br i1 %icmp8, label %bb11, label %bb57
|
||||
|
||||
bb11: ; preds = %bb9
|
||||
%add12 = add nsw i32 %phi, 1
|
||||
%mul13 = mul nsw i32 %add12, %arg5
|
||||
%mul14 = mul nsw i32 %phi, %arg5
|
||||
%add15 = add i32 %add, %mul
|
||||
%add16 = add i32 %mul, %ashr
|
||||
%add17 = add i32 %mul, %ashr6
|
||||
%getelementptr = getelementptr inbounds i8, ptr %arg4, i32 %mul13
|
||||
%getelementptr18 = getelementptr inbounds i8, ptr %arg4, i32 %mul14
|
||||
%getelementptr19 = getelementptr inbounds i16, ptr %arg, i32 %add15
|
||||
%getelementptr20 = getelementptr inbounds i16, ptr %arg, i32 %add16
|
||||
%getelementptr21 = getelementptr inbounds i16, ptr %arg, i32 %add17
|
||||
%getelementptr22 = getelementptr inbounds i16, ptr %arg, i32 %mul
|
||||
%bitcast = bitcast ptr %getelementptr to ptr
|
||||
%bitcast23 = bitcast ptr %getelementptr18 to ptr
|
||||
%bitcast24 = bitcast ptr %getelementptr19 to ptr
|
||||
%bitcast25 = bitcast ptr %getelementptr20 to ptr
|
||||
%bitcast26 = bitcast ptr %getelementptr21 to ptr
|
||||
%bitcast27 = bitcast ptr %getelementptr22 to ptr
|
||||
br label %bb28
|
||||
|
||||
bb28: ; preds = %bb28, %bb11
|
||||
%phi29 = phi i32 [ 0, %bb11 ], [ %add54, %bb28 ]
|
||||
%phi30 = phi ptr [ %bitcast27, %bb11 ], [ %getelementptr36, %bb28 ]
|
||||
%phi31 = phi ptr [ %bitcast26, %bb11 ], [ %getelementptr37, %bb28 ]
|
||||
%phi32 = phi ptr [ %bitcast25, %bb11 ], [ %getelementptr39, %bb28 ]
|
||||
%phi33 = phi ptr [ %bitcast24, %bb11 ], [ %getelementptr41, %bb28 ]
|
||||
%phi34 = phi ptr [ %bitcast, %bb11 ], [ %getelementptr53, %bb28 ]
|
||||
%phi35 = phi ptr [ %bitcast23, %bb11 ], [ %getelementptr52, %bb28 ]
|
||||
%getelementptr36 = getelementptr inbounds <16 x i32>, ptr %phi30, i32 1
|
||||
%load = load <16 x i32>, ptr %phi30, align 64, !tbaa !1
|
||||
%getelementptr37 = getelementptr inbounds <16 x i32>, ptr %phi31, i32 1
|
||||
%load38 = load <16 x i32>, ptr %phi31, align 64, !tbaa !1
|
||||
%getelementptr39 = getelementptr inbounds <16 x i32>, ptr %phi32, i32 1
|
||||
%load40 = load <16 x i32>, ptr %phi32, align 64, !tbaa !1
|
||||
%getelementptr41 = getelementptr inbounds <16 x i32>, ptr %phi33, i32 1
|
||||
%load42 = load <16 x i32>, ptr %phi33, align 64, !tbaa !1
|
||||
%call = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %load, <16 x i32> %load38)
|
||||
%call43 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %load, <16 x i32> %load38)
|
||||
%call44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %load40, <16 x i32> %load42)
|
||||
%call45 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %load40, <16 x i32> %load42)
|
||||
%call46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %call, <16 x i32> %call44)
|
||||
%call47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %call, <16 x i32> %call44)
|
||||
%call48 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %call43, <16 x i32> %call45)
|
||||
%call49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %call43, <16 x i32> %call45)
|
||||
%call50 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %call47, <16 x i32> %call46)
|
||||
%call51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %call49, <16 x i32> %call48)
|
||||
%getelementptr52 = getelementptr inbounds <16 x i32>, ptr %phi35, i32 1
|
||||
store <16 x i32> %call50, ptr %phi35, align 64, !tbaa !1
|
||||
%getelementptr53 = getelementptr inbounds <16 x i32>, ptr %phi34, i32 1
|
||||
store <16 x i32> %call51, ptr %phi34, align 64, !tbaa !1
|
||||
%add54 = add nsw i32 %phi29, 1
|
||||
%icmp55 = icmp slt i32 %add54, %sdiv
|
||||
br i1 %icmp55, label %bb28, label %bb56
|
||||
|
||||
bb56: ; preds = %bb28
|
||||
br label %bb57
|
||||
|
||||
bb57: ; preds = %bb56, %bb9
|
||||
%add58 = add nsw i32 %phi, 2
|
||||
%icmp59 = icmp slt i32 %add58, %arg2
|
||||
br i1 %icmp59, label %bb9, label %bb60
|
||||
|
||||
bb60: ; preds = %bb57
|
||||
br label %bb61
|
||||
|
||||
bb61: ; preds = %bb60, %bb
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
|
||||
declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
|
||||
|
||||
!llvm.ident = !{!0}
|
||||
|
||||
!0 = !{!"Clang 3.1"}
|
||||
!1 = !{!2, !2, i64 0}
|
||||
!2 = !{!"omnipotent char", !3, i64 0}
|
||||
!3 = !{!"Simple C/C++ TBAA"}
|
||||
Reference in New Issue
Block a user