caio/clang-p2996
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<rdar://problem/13020634>

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Fixed the 32, 16, and 8 bit pseudo regs for x86_64 (real reg of "rax" which subvalues "eax", "ax", etc...) to correctly get updated when stepping. Also fixed it so actual registers can specify what other registers must be invalidated when a register is modified. Previously, only pseudo registers could invalidate other registers.

Modified the LLDB qRegisterInfo extension to the GDB remote interface to support specifying the containing registers with the new "container-regs" key whose value is a comma separated list of register numbers. Also added a "invalidate-regs" key whose value is also a comma separated list of register numbers. 

Removed the hack GDBRemoteDynamicRegisterInfo::Addx86_64ConvenienceRegisters() function and modified "debugserver" to specify the registers correctly using the new "container-regs" and "invalidate-regs" keys.

llvm-svn: 173096
This commit is contained in:
Greg Clayton
2013-01-21 22:17:50 +00:00
parent 304f6f0a59
commit ce1ffcf8a2
6 changed files with 409 additions and 250 deletions
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44
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
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@@ -280,6 +280,8 @@ ProcessGDBRemote::BuildDynamicRegisterInfo (bool force)
ConstString reg_name;
ConstString alt_name;
ConstString set_name;
std::vector<uint32_t> value_regs;
std::vector<uint32_t> invalidate_regs;
RegisterInfo reg_info = { NULL, // Name
NULL, // Alt name
0, // byte size
@@ -371,11 +373,48 @@ ProcessGDBRemote::BuildDynamicRegisterInfo (bool force)
{
reg_info.kinds[eRegisterKindGeneric] = Args::StringToGenericRegister (value.c_str());
}
else if (name.compare("container-regs") == 0)
{
std::pair<llvm::StringRef, llvm::StringRef> value_pair;
value_pair.second = value;
do
{
value_pair = value_pair.second.split(',');
if (!value_pair.first.empty())
{
value_regs.push_back (Args::StringToUInt32 (value_pair.first.str().c_str()));
}
} while (!value_pair.second.empty());
}
else if (name.compare("invalidate-regs") == 0)
{
std::pair<llvm::StringRef, llvm::StringRef> value_pair;
value_pair.second = value;
do
{
value_pair = value_pair.second.split(',');
if (!value_pair.first.empty())
{
invalidate_regs.push_back (Args::StringToUInt32 (value_pair.first.str().c_str()));
}
} while (!value_pair.second.empty());
}
}
reg_info.byte_offset = reg_offset;
assert (reg_info.byte_size != 0);
reg_offset += reg_info.byte_size;
if (!value_regs.empty())
{
value_regs.push_back(LLDB_INVALID_REGNUM);
reg_info.value_regs = value_regs.data();
}
if (!invalidate_regs.empty())
{
invalidate_regs.push_back(LLDB_INVALID_REGNUM);
reg_info.invalidate_regs = invalidate_regs.data();
}
m_register_info.AddRegister(reg_info, reg_name, alt_name, set_name);
}
}
@@ -415,11 +454,6 @@ ProcessGDBRemote::BuildDynamicRegisterInfo (bool force)
m_register_info.HardcodeARMRegisters(from_scratch);
}
// Add some convenience registers (eax, ebx, ecx, edx, esi, edi, ebp, esp) to x86_64.
if ((target_arch.IsValid() && target_arch.GetMachine() == llvm::Triple::x86_64)
|| (remote_arch.IsValid() && remote_arch.GetMachine() == llvm::Triple::x86_64))
m_register_info.Addx86_64ConvenienceRegisters();
// At this point, we can finalize our register info.
m_register_info.Finalize ();
}