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[RISCV] Fix an inconsistency with compatible load/store handling

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Once we've computed the incoming predecessor state, we should use the same compatibility check with knowledge of MI as we did in phase 2 in order to be consistent across all phases.

Differential Revision: https://reviews.llvm.org/D126574
This commit is contained in:
Philip Reames
2022-06-02 07:56:06 -07:00
committed by Philip Reames
parent 6423a9f0ec
commit dcdb0bf25b
3 changed files with 29 additions and 4 deletions
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2
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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@@ -1123,7 +1123,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
// use the predecessor information.
CurInfo = BlockInfo[MBB.getNumber()].Pred;
assert(CurInfo.isValid() && "Expected a valid predecessor state.");
if (needVSETVLI(NewInfo, CurInfo)) {
if (needVSETVLI(MI, NewInfo, CurInfo)) {
// If this is the first implicit state change, and the state change
// requested can be proven to produce the same register contents, we
// can skip emitting the actual state change and continue as if we

29
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
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@@ -505,8 +505,8 @@ define <vscale x 2 x i32> @test_vsetvli_x0_x0(<vscale x 2 x i32>* %x, <vscale x
; CHECK-NEXT: andi a0, a3, 1
; CHECK-NEXT: beqz a0, .LBB9_2
; CHECK-NEXT: # %bb.1: # %if
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v10, (a1)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vwcvt.x.x.v v8, v10
; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
@@ -544,8 +544,8 @@ define <vscale x 2 x i32> @test_vsetvli_x0_x0_2(<vscale x 2 x i32>* %x, <vscale
; CHECK-NEXT: andi a0, a4, 1
; CHECK-NEXT: beqz a0, .LBB10_2
; CHECK-NEXT: # %bb.1: # %if
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v10, (a1)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vwadd.wv v9, v9, v10
; CHECK-NEXT: .LBB10_2: # %if.end
; CHECK-NEXT: andi a0, a5, 1
@@ -862,6 +862,31 @@ if.end:
ret <vscale x 2 x i32> %b
}
define <vscale x 1 x double> @compat_store_consistency(i1 %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x double>* %p1, <vscale x 1 x float> %c, <vscale x 1 x float>* %p2) {
; CHECK-LABEL: compat_store_consistency:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a3, zero, e64, m1, ta, mu
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vs1r.v v8, (a1)
; CHECK-NEXT: beqz a0, .LBB19_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vse32.v v10, (a2)
; CHECK-NEXT: .LBB19_2: # %if.end
; CHECK-NEXT: ret
entry:
%res = fadd <vscale x 1 x double> %a, %b
store <vscale x 1 x double> %res, <vscale x 1 x double>* %p1
br i1 %cond, label %if.then, label %if.end
if.then: ; preds = %entry
store <vscale x 1 x float> %c, <vscale x 1 x float>* %p2
br label %if.end
if.end: ; preds = %if.else, %if.then
ret <vscale x 1 x double> %res
}
declare i64 @llvm.riscv.vsetvlimax.i64(i64, i64)
declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, i64)

2
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
View File

@@ -941,8 +941,8 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[PHI]]
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 killed [[ADD1]], -1, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 [[PseudoVLE8_V_MF8_]], 4, -1, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[PHI]]
; CHECK-NEXT: PseudoVSE8_V_MF8 killed [[PseudoVADD_VI_MF8_]], killed [[ADD2]], -1, 3 /* e8 */, implicit $vl, implicit $vtype