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[PowerPC] Do not attempt to combine fptoui without FPCVT

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Commit 8064caf83f added a call
to a function that performs this combine without checking whether
the target supports FPCVT. This caused asserts to trip on BE bots
as the default target does not have this feature.
This commit is contained in:
Nemanja Ivanovic
2023-05-24 11:12:19 -05:00
parent 81fb5a0e1c
commit de681d53ba
2 changed files with 79 additions and 1 deletions
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4
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@@ -15515,8 +15515,10 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
EVT Op1VT = N->getOperand(1).getValueType();
unsigned Opcode = N->getOperand(1).getOpcode();
bool NeedsFPCVT = Opcode == ISD::FP_TO_UINT && Op1VT == MVT::i64;
if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) {
if ((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) &&
(!NeedsFPCVT || Subtarget.hasFPCVT())) {
SDValue Val= combineStoreFPToInt(N, DCI);
if (Val)
return Val;

76
llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll Normal file
View File

@@ -0,0 +1,76 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
define dso_local void @calc_buffer() local_unnamed_addr #0 {
; CHECK-LABEL: calc_buffer:
; CHECK: # %bb.0:
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: sradi r5, r3, 53
; CHECK-NEXT: rldicl r6, r3, 63, 1
; CHECK-NEXT: clrldi r7, r3, 63
; CHECK-NEXT: clrldi r4, r3, 53
; CHECK-NEXT: addi r5, r5, 1
; CHECK-NEXT: or r7, r7, r6
; CHECK-NEXT: cmpldi r5, 1
; CHECK-NEXT: clrldi r5, r7, 53
; CHECK-NEXT: addi r4, r4, 2047
; CHECK-NEXT: addi r5, r5, 2047
; CHECK-NEXT: or r5, r5, r6
; CHECK-NEXT: rldicl r6, r3, 10, 54
; CHECK-NEXT: or r4, r4, r3
; CHECK-NEXT: addi r6, r6, 1
; CHECK-NEXT: rldicl r5, r5, 53, 11
; CHECK-NEXT: cmpldi cr1, r6, 1
; CHECK-NEXT: rldicr r4, r4, 0, 52
; CHECK-NEXT: rldicl r5, r5, 11, 1
; CHECK-NEXT: bc 12, gt, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ori r4, r3, 0
; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: bc 12, 4*cr1+gt, .LBB0_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: ori r5, r7, 0
; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: cmpdi r3, 0
; CHECK-NEXT: std r4, -32(r1)
; CHECK-NEXT: std r5, -24(r1)
; CHECK-NEXT: bc 12, lt, .LBB0_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: lfd f0, -32(r1)
; CHECK-NEXT: fcfid f0, f0
; CHECK-NEXT: frsp f0, f0
; CHECK-NEXT: b .LBB0_7
; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: lfd f0, -24(r1)
; CHECK-NEXT: fcfid f0, f0
; CHECK-NEXT: frsp f0, f0
; CHECK-NEXT: fadds f0, f0, f0
; CHECK-NEXT: .LBB0_7:
; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: li r4, 1
; CHECK-NEXT: lfs f1, .LCPI0_0@toc@l(r3)
; CHECK-NEXT: rldic r4, r4, 63, 0
; CHECK-NEXT: fsubs f2, f0, f1
; CHECK-NEXT: fctidz f2, f2
; CHECK-NEXT: stfd f2, -8(r1)
; CHECK-NEXT: fctidz f2, f0
; CHECK-NEXT: stfd f2, -16(r1)
; CHECK-NEXT: ld r3, -8(r1)
; CHECK-NEXT: ld r5, -16(r1)
; CHECK-NEXT: fcmpu cr0, f0, f1
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: bc 12, lt, .LBB0_8
; CHECK-NEXT: b .LBB0_9
; CHECK-NEXT: .LBB0_8:
; CHECK-NEXT: addi r3, r5, 0
; CHECK-NEXT: .LBB0_9:
; CHECK-NEXT: std r3, 0(r3)
%load_initial = load i64, ptr poison, align 8
%conv39 = uitofp i64 %load_initial to float
%add48 = fadd float 0.000000e+00, %conv39
%conv49 = fptoui float %add48 to i64
store i64 %conv49, ptr poison, align 8
unreachable
}