From fa42e7b6bc430941f42cf50b5c4e55b3c19ccc08 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 1 May 2023 13:00:05 -0700 Subject: [PATCH] [RISCV] Merge RISCV::parseCPUKind and RISCV::checkCPUKind. Similar for RISCV::parseTuneCPU and RISCV::checkTuneCPUKind. This makes the CPUKind enum no longer part of the API. It wasn't providing much value. It was only used to pass between the two functions. By removing it, we can remove a dependency on a tablegen generated file from the RISCVTargetParser.h file. Then we can remove a dependency from several CMakeLists.txt. --- clang/lib/Basic/CMakeLists.txt | 1 - clang/lib/Basic/Targets/RISCV.cpp | 5 +-- clang/lib/Driver/CMakeLists.txt | 1 - clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 8 ++-- clang/lib/Sema/CMakeLists.txt | 1 - llvm/docs/ReleaseNotes.rst | 4 ++ .../llvm/TargetParser/RISCVTargetParser.h | 12 +----- llvm/lib/TargetParser/RISCVTargetParser.cpp | 42 +++++++++++-------- 8 files changed, 36 insertions(+), 38 deletions(-) diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt index c05036a216c7..caa1b6002e6f 100644 --- a/clang/lib/Basic/CMakeLists.txt +++ b/clang/lib/Basic/CMakeLists.txt @@ -125,7 +125,6 @@ add_clang_library(clangBasic DEPENDS omp_gen - RISCVTargetParserTableGen ) target_link_libraries(clangBasic diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index dd99d96b5f4d..6720fcd567ac 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -325,7 +325,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector &Features, bool RISCVTargetInfo::isValidCPUName(StringRef Name) const { bool Is64Bit = getTriple().isArch64Bit(); - return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), Is64Bit); + return llvm::RISCV::parseCPU(Name, Is64Bit); } void RISCVTargetInfo::fillValidCPUList( @@ -336,8 +336,7 @@ void RISCVTargetInfo::fillValidCPUList( bool RISCVTargetInfo::isValidTuneCPUName(StringRef Name) const { bool Is64Bit = getTriple().isArch64Bit(); - return llvm::RISCV::checkTuneCPUKind( - llvm::RISCV::parseTuneCPUKind(Name, Is64Bit), Is64Bit); + return llvm::RISCV::parseTuneCPU(Name, Is64Bit); } void RISCVTargetInfo::fillValidTuneCPUList( diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt index 3d83c86100be..a6bd2d41e797 100644 --- a/clang/lib/Driver/CMakeLists.txt +++ b/clang/lib/Driver/CMakeLists.txt @@ -95,7 +95,6 @@ add_clang_library(clangDriver DEPENDS ClangDriverOptions - RISCVTargetParserTableGen LINK_LIBS clangBasic diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 7cf01ad8a72b..a26c9caf64c7 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -54,11 +54,11 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A, StringRef Mcpu, std::vector &Features) { bool Is64Bit = Triple.isRISCV64(); - llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu); - if (!llvm::RISCV::checkCPUKind(CPUKind, Is64Bit)) { + if (!llvm::RISCV::parseCPU(Mcpu, Is64Bit)) { // Try inverting Is64Bit in case the CPU is valid, but for the wrong target. - if (llvm::RISCV::checkCPUKind(CPUKind, !Is64Bit)) - D.Diag(clang::diag::err_drv_invalid_riscv_cpu_name_for_target) << Mcpu << Is64Bit; + if (llvm::RISCV::parseCPU(Mcpu, !Is64Bit)) + D.Diag(clang::diag::err_drv_invalid_riscv_cpu_name_for_target) + << Mcpu << Is64Bit; else D.Diag(clang::diag::err_drv_unsupported_option_argument) << A->getSpelling() << Mcpu; diff --git a/clang/lib/Sema/CMakeLists.txt b/clang/lib/Sema/CMakeLists.txt index 843a269dac72..629fafadcf9f 100644 --- a/clang/lib/Sema/CMakeLists.txt +++ b/clang/lib/Sema/CMakeLists.txt @@ -71,7 +71,6 @@ add_clang_library(clangSema DEPENDS ClangOpenCLBuiltinsImpl omp_gen - RISCVTargetParserTableGen LINK_LIBS clangAST diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 334365fa0a8a..c764a50f88b2 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -171,6 +171,10 @@ Changes to the RISC-V Backend * Updated support experimental vector crypto extensions to version 0.5.1 of the specification. * Removed N extension (User-Level Interrupts) CSR names in the assembler. +* ``RISCV::parseCPUKind`` and ``RISCV::checkCPUKind`` were merged into a single + ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the + RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and + ``checkTuneCPUKind``. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index 993f653455a0..a4cb7988eb39 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -26,16 +26,8 @@ namespace RISCV { // We use 64 bits as the known part in the scalable vector types. static constexpr unsigned RVVBitsPerBlock = 64; -enum CPUKind : unsigned { -#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM, -#define TUNE_PROC(ENUM, NAME) CK_##ENUM, -#include "llvm/TargetParser/RISCVTargetParserDef.inc" -}; - -bool checkCPUKind(CPUKind Kind, bool IsRV64); -bool checkTuneCPUKind(CPUKind Kind, bool IsRV64); -CPUKind parseCPUKind(StringRef CPU); -CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64); +bool parseCPU(StringRef CPU, bool IsRV64); +bool parseTuneCPU(StringRef CPU, bool IsRV64); StringRef getMArchFromMcpu(StringRef CPU); void fillValidCPUArchList(SmallVectorImpl &Values, bool IsRV64); void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64); diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index ac726cdbb797..9e1a805503ab 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -19,6 +19,12 @@ namespace llvm { namespace RISCV { +enum CPUKind : unsigned { +#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM, +#define TUNE_PROC(ENUM, NAME) CK_##ENUM, +#include "llvm/TargetParser/RISCVTargetParserDef.inc" +}; + struct CPUInfo { StringLiteral Name; CPUKind Kind; @@ -33,13 +39,28 @@ constexpr CPUInfo RISCVCPUInfo[] = { #include "llvm/TargetParser/RISCVTargetParserDef.inc" }; -bool checkCPUKind(CPUKind Kind, bool IsRV64) { +static CPUKind getCPUByName(StringRef CPU) { + return llvm::StringSwitch(CPU) +#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) +#include "llvm/TargetParser/RISCVTargetParserDef.inc" + .Default(CK_INVALID); +} + +bool parseCPU(StringRef CPU, bool IsRV64) { + CPUKind Kind = getCPUByName(CPU); + if (Kind == CK_INVALID) return false; return RISCVCPUInfo[static_cast(Kind)].is64Bit() == IsRV64; } -bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) { +bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) { + CPUKind Kind = llvm::StringSwitch(TuneCPU) +#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) +#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM) +#include "llvm/TargetParser/RISCVTargetParserDef.inc" + .Default(CK_INVALID); + if (Kind == CK_INVALID) return false; #define TUNE_PROC(ENUM, NAME) \ @@ -49,23 +70,8 @@ bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) { return RISCVCPUInfo[static_cast(Kind)].is64Bit() == IsRV64; } -CPUKind parseCPUKind(StringRef CPU) { - return llvm::StringSwitch(CPU) -#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) -#include "llvm/TargetParser/RISCVTargetParserDef.inc" - .Default(CK_INVALID); -} - -CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) { - return llvm::StringSwitch(TuneCPU) -#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) -#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM) -#include "llvm/TargetParser/RISCVTargetParserDef.inc" - .Default(CK_INVALID); -} - StringRef getMArchFromMcpu(StringRef CPU) { - CPUKind Kind = parseCPUKind(CPU); + CPUKind Kind = getCPUByName(CPU); return RISCVCPUInfo[static_cast(Kind)].DefaultMarch; }