diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
index 0d75ab7ac8a9..019220e3a527 100644
--- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
@@ -408,6 +408,11 @@ bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) {
                          O.getReg() != CmpReg;
                 }))
               continue;
+
+            // Don't remove a move immediate that implicitly defines the upper
+            // bits as different.
+            if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0)
+              continue;
           }
 
           if (IsCopy)
diff --git a/llvm/test/CodeGen/AArch64/machine-copy-remove.mir b/llvm/test/CodeGen/AArch64/machine-copy-remove.mir
index 4e3cb3c12806..b2fc40a4d255 100644
--- a/llvm/test/CodeGen/AArch64/machine-copy-remove.mir
+++ b/llvm/test/CodeGen/AArch64/machine-copy-remove.mir
@@ -536,13 +536,13 @@ body:             |
   bb.2:
     RET_ReallyLR
 ...
-# Eliminate redundant MOVi32imm -1 in bb.1
+# Don't eliminate redundant MOVi32imm -1 in bb.1: the upper bits are nonzero.
 # Note: 64-bit compare/32-bit move imm
 # Kill marker should be removed from compare.
 # CHECK-LABEL: name: test21
-# CHECK: ADDSXri $x0, 1, 0, implicit-def $nzcv
+# CHECK: ADDSXri killed $x0, 1, 0, implicit-def $nzcv
 # CHECK: bb.1:
-# CHECK-NOT: MOVi32imm
+# CHECK: MOVi32imm
 name:            test21
 tracksRegLiveness: true
 body:             |