Commit Graph

1649 Commits

Author SHA1 Message Date
Brad Smith
f70d17fc2c [LoongArch] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros

Reviewed By: SixWeining, MaskRay

Differential Revision: https://reviews.llvm.org/D141070
2023-01-05 20:21:22 -05:00
Freddy Ye
27b8f54f51 [X86] Support -march=emeraldrapids
Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D140950
2023-01-05 20:27:32 +08:00
Brad Smith
d227c3b68c [Hexagon][VE][WebAssembly] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros

Reviewed By: kparzysz, aheejin, MaskRay

Differential Revision: https://reviews.llvm.org/D140757
2023-01-05 04:45:07 -05:00
Corentin Jabot
0d6b26b4d3 [Clang] Fix a crash when encountering an ill-formed delimited UCN.
\u<DIGIT>{...} was incorrectly parsed as a valid UCN instead
of emitting a diagnostic, causing an assertion failure.

Reviewed By: tahonermann

Differential Revision: https://reviews.llvm.org/D139889
2023-01-03 20:57:52 +01:00
Brad Smith
2784b243e3 [M68k] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros

Fixes #58974

Reviewed By: myhsu, glaubitz, 0x59616e

Differential Revision: https://reviews.llvm.org/D140695
2022-12-29 05:07:35 -05:00
Yeting Kuo
bd9c0f082b [RISCV] Add Svpbmt extension support.
Spec of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D140692
2022-12-28 23:57:54 -08:00
Pavel Iliin
fe5cf480ee Reland "[AArch64] FMV support and necessary target features dependencies."
This relands commits e43924a751,
a43f36142c,
bf94eac6a3 with MSan buildbot
https://lab.llvm.org/buildbot/#/builders/5/builds/30139
use-of-uninitialized-value errors fixed.

Differential Revision: https://reviews.llvm.org/D127812
2022-12-27 19:18:07 +00:00
Jojo R
54752f3ff6 [RISCV] Implement assembler support for XTHeadVdot
This patch implements the T-Head vendor extensions (XTHeadVdot),
which is documented here, it's based on standard vector extension v1.0:
  https://github.com/T-head-Semi/thead-extension-spec
2022-12-26 19:05:22 +08:00
Mitch Phillips
744486ec21 Revert "[AArch64] FMV support and necessary target features dependencies."
This reverts commit e43924a751.

Reason: Patch broke the MSan buildbots. More information is available on
the original phabricator review: https://reviews.llvm.org/D127812
2022-12-20 17:16:32 -08:00
Pavel Iliin
e43924a751 [AArch64] FMV support and necessary target features dependencies.
This is Function Multi Versioning (FMV) implementation for AArch64 target in
accordance with Beta Arm C Language Extensions specification
https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning
It supports new "target_version" function attribute and extends existing
"target_clones" one. Also missing dependencies for target features were added.

Differential Revision: https://reviews.llvm.org/D127812
2022-12-20 15:42:25 +00:00
Ganesh Gopalasubramanian
1f057e365f [X86] AMD Zen 4 Initial enablement
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D139073
2022-12-17 16:15:22 +05:30
Corentin Jabot
dbfe446ef3 [Clang] Implement CWG2640 Allow more characters in an n-char sequence
Reviewed By: #clang-language-wg, aaron.ballman, tahonermann

Differential Revision: https://reviews.llvm.org/D138861
2022-12-13 09:02:52 +01:00
Sylvain Audi
822c274477 [clang-cl] Ignore #pragma managed/unmanaged
Those 2 pragmas are ignored by MSVC when not compiling with /CLR, which clang doesn't support.
Ignore them in clang -fms-extensions, to avoid -Wunknown-pragma warnings

Differential Revision: https://reviews.llvm.org/D139632
2022-12-12 10:01:24 -05:00
Haojian Wu
23e1078a2f Add distinguished content to the empty test headers.
To make the lit test print-header-json.c passed on a file-content-hash
file system.
2022-12-08 16:27:04 +01:00
Akira Hatanaka
abc87ad4ed Remove slash in check string to fix the test that is failng on windows 2022-12-07 16:17:29 -08:00
Akira Hatanaka
3738ce05a7 Add support for a backdoor driver option that enables emitting header
usage information in JSON to a file

Each line in the file is a JSON object that has the name of the main
source file followed by the list of system header files included
directly or indirectly from that file.

For example:

{"source":"/tmp/foo.c",
 "includes":["/usr/include/stdio.h", "/usr/include/stdlib.h"]}

To reduce the amount of data written to the file, only the system
headers that are directly included from a non-system header file are
recorded.

In order to emit the header information in JSON, it is necessary to set
the following environment variables:

CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILTERING=only-direct-system

The following combination is equivalent to setting CC_PRINT_HEADERS=1:

CC_PRINT_HEADERS_FORMAT=textual CC_PRINT_HEADERS_FILTERING=none

Differential Revision: https://reviews.llvm.org/D137996
2022-12-07 15:30:19 -08:00
Daniel Kiss
7d40baa82b [AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH
Macros are added to ACLE[1] and already added to ARM but these two are missing from AArch64.

[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#changes-between-acle-q3-2021-and-acle-q4-2021

Reviewed By: chill

Differential Revision: https://reviews.llvm.org/D139445
2022-12-07 16:30:16 +01:00
Daniel Kiss
7925e2828e Revert "[AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH"
This reverts commit cfd44221e3.
2022-12-07 15:19:31 +01:00
Daniel Kiss
cfd44221e3 [AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH
Macros are added to ACLE[1] and already added to ARM but these two are missing from AArch64.

[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#changes-between-acle-q3-2021-and-acle-q4-2021

Reviewed By: chill

Differential Revision: https://reviews.llvm.org/D139445
2022-12-07 14:52:55 +01:00
Archibald Elliott
83b3304dd2 [AArch64] Implement __arm_rsr128/__arm_wsr128
This only contains the SelectionDAG implementation. GlobalISel to
follow.

The broad approach is:
- Introduce new builtins for 128-bit wide instructions.
- Lower these to @llvm.read_register.i128/@llvm.write_register.i128
- Introduce target-specific ISD nodes which have legal operands (two
  i64s rather than an i128). These are named AArch64::{MRRS, MSRR} to
  match the instructions they are for. These are a little complex as
  they need to match the "shape" of what they're replacing or the
  legaliser complains.
- Select these using the existing tryReadRegister/tryWriteRegister to
  share the MDString parsing code, and introduce additional code to
  ensure these are selected into the right MRRS/MSRR instructions. What
  makes this hard is ensuring that the two i64s end up in an XSeqPair
  register pair, because SelectionDAG doesn't care that much about
  register classes if it can avoid doing so.

The main change to existing code is the reorganisation of
tryReadRegister and tryWriteRegister to try to keep the string parsing
code separate from the instruction creating code.

This also includes the changes to clang to define and use the ACLE
feature macro named `__ARM_FEATURE_SYSREG128`.

Contributors:
  Sam Elliott
  Lucas Prates

Differential Revision: https://reviews.llvm.org/D139086
2022-12-06 11:39:05 +00:00
Freddy Ye
def720726b [X86][clang] Lift _BitInt() supported max width.
Reviewed By: mgehre-amd

Differential Revision: https://reviews.llvm.org/D139170
2022-12-06 11:02:27 +08:00
Paul Robinson
aa149687dc [PS4/PS5] Canonicalize tests to use 'target=.*-(ps4|ps5)'
This allows grepping for ps4 or ps5 to continue to work.
2022-12-01 07:21:07 -08:00
eopXD
482b8b493b [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version
According to version_macro.adoc under rvv-intrinsic-doc, the compiler
should have a macro to imply such availability.

Link: https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/version_macro.adoc

Reviewed By: kito-cheng, asb

Differential Revision: https://reviews.llvm.org/D138930
2022-11-30 08:35:53 -08:00
Paul Robinson
dee009d3b5 [lit] UNSUPPORTED ps4/ps5 => target={{.*-ps(4|5)}}
Part of the project to eliminate special handling for triples in lit expressions.
2022-11-29 09:07:59 -08:00
Paul Robinson
f19c2720e3 [PS4] Remove an UNSUPPORTED, this test seems to work now 2022-11-29 08:59:09 -08:00
WuXinlong
0dbc52a0ab Add MC support of RISCV Zcd Extension
This patch add the instructions of Zcd extension.

Zcd is a subset of C Ext which include the double-precision floating-point instructions (c.fld, c.fldsp, c.fsd, c.fsdsp).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134177
2022-11-24 05:48:06 +08:00
WuXinlong
16bf359a3f Add MC support of RISCV Zcf Extension
This patch add the instructions of Zcf extension.

Zcf is a subset of C Ext which include the single-precision floating-point instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134176
2022-11-23 15:09:02 +08:00
Fangrui Song
987b49395c [PPC] Undefine __ppc64__ to match GCC
GCC only defines `__ppc64__` for darwin while the darwin support has been
removed from llvm-project. The existence of `__ppc64__` makes some software
think we are compiling for big-endian PowerPC Mac; also it lures users to write
code which is not portable to GCC.

It is straightforward if a distro wants to keep the macro: add
`-D__ppc64__=1` to a Clang configuration file.

Reviewed By: thesamesam, nemanjai

Differential Revision: https://reviews.llvm.org/D137511
2022-11-22 17:01:39 -08:00
Ayke van Laethem
a8efcb96e6 [AVR][Clang] Implement __AVR_HAVE_*__ macros
These macros are defined in avr-gcc and are useful when working with
assembly. For example, startup code needs to copy the contents of .data
from flash to RAM, but should use elpm (instead of lpm) on devices with
more than 64kB flash. Without __AVR_HAVE_ELPM__, there is no way to know
whether the elpm instruction is supported.

This partially fixes https://github.com/llvm/llvm-project/issues/56157.

Differential Revision: https://reviews.llvm.org/D137572
2022-11-23 01:21:09 +01:00
Krzysztof Parzyszek
7c476697e2 [Hexagon] Add clang flags for v71, v71t, v73 2022-11-18 09:39:47 -08:00
Brad Smith
6536a67338 [Linux] Revert 1e56821bac
The glibc issue mentioned in #47994 has been fixed upstream.
2022-11-17 19:48:01 -05:00
Ties Stuij
983f63f7f0 [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support
For both ARM and AArch64 add support for specifying -march=armv8.9a/armv9.4a to
clang. Add backend plumbing like target parser and predicate support.

For a summary of Amv8.9/Armv9.4 features, see:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022

For detailed information, consult the Arm Architecture Reference Manual for
A-profile architecture:
https://developer.arm.com/documentation/ddi0487/latest/

People who contributed to this patch:
- Keith Walker
- Ties Stuij

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D138010
2022-11-16 10:20:14 +00:00
Ayke van Laethem
09ab9d4d11 [AVR][Clang] Implement __AVR_ARCH__ macro
This macro is defined in avr-gcc, and is very useful especially in
assembly code to check whether particular instructions are supported. It
is also the basis for other macros like __AVR_HAVE_ELPM__.

Differential Revision: https://reviews.llvm.org/D137521
2022-11-15 15:29:37 +01:00
Philip Reames
780c539844 [RISCV] Implement assembler support for XVentanaCondOps
This change provides an implementation of the XVentanaCondOps vendor extension. This extension is defined in version 1.0.0 of the VTx-family custom instructions specification (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) by Ventana Micro Systems.

In addition to the technical contribution, this change is intended to be a test case for our vendor extension policy.

Once this lands, I plan to use this extension to prototype selection lowering to conditional moves. There's an RVI proposal in flight, and the expectation is that lowering to these and the new RVI instructions is likely to be substantially similar.

Differential Revision: https://reviews.llvm.org/D137350
2022-11-14 09:01:54 -08:00
Weining Lu
60e5cfe2a4 [Clang][LoongArch] Define more LoongArch specific built-in macros
Define below macros according to LoongArch toolchain conventions [1].

* `__loongarch_grlen`
* `__loongarch_frlen`
* `__loongarch_lp64`
* `__loongarch_hard_float`
* `__loongarch_soft_float`
* `__loongarch_single_float`
* `__loongarch_double_float`

Note:
1. `__loongarch__` has been defined in earlier patch.
2. `__loongarch_arch` is not defined because I don't know how `TargetInfo` can get the arch name specified by `-march`.
3. `__loongarch_tune` will be defined in future.

[1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-toolchain-conventions-EN.html

Depends on D136146

Differential Revision: https://reviews.llvm.org/D136413
2022-11-10 17:27:29 +08:00
Freddy Ye
84a18a260e [X86] Support -march=sierraforest, grandridge, graniterapids.
Reviewed By: skan, pengfei, MaskRay

Differential Revision: https://reviews.llvm.org/D137153
2022-11-09 16:56:03 +08:00
Freddy Ye
a806fc2767 [X86] Support -march=raptorlake, meteorlake
Reviewed By: pengfei, skan, MaskRay

Differential Revision: https://reviews.llvm.org/D135937
2022-11-04 09:32:17 +08:00
Manoj Gupta
2497d5aa77 Define _GNU_SOURCE for arm baremetal in C++ mode.
This matches other C++ drivers e.g. Linux that define
_GNU_SOURCE. This lets clang compiler more code by default
without explicitly passing _GNU_SOURCE on command line.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D136712
2022-11-03 13:58:47 -07:00
Alex Lorenz
f4be5ed6a3 [clang][pp] only __is_target_environment(unknown) should match unknown target triple environment 2022-11-02 13:49:04 -07:00
Freddy Ye
aee2a35ac4 [X86] Add AVX-NE-CONVERT instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D135930
2022-10-31 23:39:38 +08:00
Freddy Ye
23f02693ec [X86] Add AVX-VNNI-INT8 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135938
2022-10-28 10:39:54 +08:00
Freddy Ye
0e720e6ada [X86] Add AVX-IFMA instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135932
2022-10-28 09:42:30 +08:00
Phoebe Wang
b51b90d6e2 [X86][1/2] SUPPORT RAO-INT
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Initial authored by Liu Chen (@LiuChen3)

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D135951
2022-10-27 17:20:07 +08:00
Ben Langmuir
211f5af38a [clang] Move getenv call for SOURCE_DATE_EPOCH out of frontend NFC
Move the check for SOURCE_DATE_EPOCH to the driver and use a cc1 option
to pass it to the frontend. This avoids hidden state in the cc1
invocation and makes this env variable behave more like other env
variables that clang handles in the driver.

Differential Revision: https://reviews.llvm.org/D136717
2022-10-26 12:42:56 -07:00
Piyou Chen
7d7940fd77 [RISCV] add svinval extension
1. Add the svinval extension support
2. Add the svinval Predicates for its instruction

Note: the svinval instructions defined in https://reviews.llvm.org/D117654

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136571
2022-10-26 09:45:30 -07:00
Freddy Ye
fdac4c4e92 [X86] Add CMPCCXADD instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135933
2022-10-25 14:33:39 +08:00
Piyou Chen
f8b8426861 [RISCV] Add Svnapot extension
Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D136570
2022-10-24 01:27:04 -07:00
Xiang1 Zhang
661881d436 [X86] Add AMX-FP16 instructions.
Differential Revision: https://reviews.llvm.org/D135941
2022-10-22 08:05:22 +08:00
Evgeny Shulgin
5b567637e2 [Clang] Add __has_constexpr_builtin support
The `__has_constexpr_builtin` macro can be used to check
whether the builtin in constant-evaluated by Clang frontend.

Reviewed By: aaron.ballman, shafik

Differential Revision: https://reviews.llvm.org/D136036
2022-10-21 11:23:10 +00:00
Ties Stuij
95bbe9a193 [clang][ARM] follow GCC behavior for defining __SOFTFP__
GCC behavior regarding defining __SOFTFP__ when (implicitly) specifying
-mfloat-abi=softfp:
- compile without (implicit) FP: define __SOFTFP__
- compile with (implicit) FP: don't define __SOFTFP__

Currently Clang doesn't define __SOFTFP__ when softfp is specified, either with
or without FP. This patch brings Clang in line with GCC behavior.

This was raised by itaig1 over on Github:
https://github.com/llvm/llvm-project/issues/55755

Reviewed By: pratlucas

Differential Revision: https://reviews.llvm.org/D135680
2022-10-18 14:38:03 +01:00