Commit Graph

9768 Commits

Author SHA1 Message Date
Matt Arsenault
270e96f435 Revert "AMDGPU: Invert handling of enqueued block detection"
This reverts commit 47288cc977.

The runtime is having trouble with this at -O0 when the inputs are
always enabled.
2023-01-07 21:48:07 -05:00
Matt Arsenault
47288cc977 AMDGPU: Invert handling of enqueued block detection
Invert the sense of the attribute and let the attributor figure this
out like everything else. If needed we can have the not-OpenCL
languages set amdgpu-no-default-queue and amdgpu-no-completion-action
up front so they never have to pay the cost.

There are also so many of these now, the offset use API should
probably consider all of them at once. Maybe they should merge into
one attribute with used fields. Having separate functions for each
field in AMDGPUBaseInfo is also not the greatest API (might as well
fix this when the patch to get the object version from the module
lands).
2023-01-06 21:16:08 -05:00
Alexandre Ganea
e66500c774 [Support] On Windows 11 and Windows Server 2022, fix an affinity mask issue on large core count machines
Before Windows 11 and Windows Server 2022, only one 'processor group' is assigned by default to a starting process, then the program is responsible for dispatching its own threads on more 'processor groups'. That is what 8404aeb56a was doing, allowing LLVM tools to automatically use all hardware threads in the machine.

After Windows 11 and Windows Server 2022, the OS takes care of that. This has an adverse effect reported in #56618 which is that using `GetProcessAffinityMask()` API in some edge cases seems buggy now. That API is used to detect if an affinity mask was set, and adjust accordingly the available threads for a ThreadPool.

With this patch, on one hand, we let the OS dispatch threads on all 'processor groups', but only for Windows 11 & Windows Server 2022 and after. We retain the old behavior for older OS versions. On the other hand, a workaround was added to mitigate the `GetProcessAffinityMask()` issue described above (see Threading.inc, L226).

Differential Revision: https://reviews.llvm.org/D138747
2023-01-06 17:03:43 -05:00
Stephen Tozer
c383f4d655 [DebugInfo] Allow non-stack_value variadic expressions and use in DBG_INSTR_REF
Prior to this patch, variadic DIExpressions (i.e. ones that contain
DW_OP_LLVM_arg) could only be created by salvaging debug values to create
stack value expressions, resulting in a DBG_VALUE_LIST being created. As of
the previous patch in this patch stack, DBG_INSTR_REF's syntax has been
changed to match DBG_VALUE_LIST in preparation for supporting variadic
expressions. This patch adds some minor changes needed to allow variadic
expressions that aren't stack values to exist, and allows variadic expressions
that are trivially reduceable to non-variadic expressions to be handled
similarly to non-variadic expressions.

Reviewed by: jmorse

Differential Revision: https://reviews.llvm.org/D133926
2023-01-06 19:31:10 +00:00
Stephen Tozer
85bff00c73 Fix: Title underline too short in D129372
This patch fixes an error in commit e10e9363 in which the
added documentation contained an incorrectly-styled underline
for the title "Debug Instruction Reference Operands".
2023-01-06 18:22:02 +00:00
Stephen Tozer
e10e936315 [DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
This patch makes two notable changes to the MIR debug info representation,
which result in different MIR output but identical final DWARF output (NFC
w.r.t. the full compilation). The two changes are:

  * The introduction of a new MachineOperand type, MO_DbgInstrRef, which
    consists of two unsigned numbers that are used to index an instruction
    and an output operand within that instruction, having a meaning
    identical to first two operands of the current DBG_INSTR_REF
    instruction. This operand is only used in DBG_INSTR_REF (see below).
  * A change in syntax for the DBG_INSTR_REF instruction, shuffling the
    operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE,
    and replacing the first two operands with a single MO_DbgInstrRef-type
    operand.

This patch is the first of a set that will allow DBG_INSTR_REF
instructions to refer to multiple machine locations in the same manner
as DBG_VALUE_LIST.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D129372
2023-01-06 18:03:48 +00:00
Nikita Popov
c8ec751d88 Revert "CodingStandards: restrict CamelCase variable names guideline to llvm/clang/clang-tools-extra/polly/bolt"
This reverts commit ee9ccb1103.

See https://reviews.llvm.org/D140585#4019417 and following.
Multiple people requested a revert of this change pending further
discussion.
2023-01-06 09:44:27 +01:00
Yeting Kuo
5a57ebcc43 [VP][RISCV] Add vp.abs and RISC-V support.
RISC-V uses ISD::ABS lower method (abs x) -> (smax_vl x (sub_vl 0, x)) for ISD::VP_ABS.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D141033
2023-01-06 15:18:12 +08:00
Vang Thao
25d72330ff [AMDGPU] Add .uniform_work_group_size metadata to v5
Amdgpu kernel with function attribute "uniform-work-group-size"="true" requires
uniform work group size (i.e. each dimension of global size is a multiple of
corresponding dimension of work group size). hipExtModuleLaunchKernel allows to
launch HIP kernel with non-uniform workgroup size, which makes it necessary for
runtime to check and enforce uniform workgroup size if kernel requires it. To
let runtime be able to enforce that, this metadata is needed to indicate that
the kernel requires uniform workgroup size.

Reviewed By: kzhuravl, arsenm

Differential Revision: https://reviews.llvm.org/D141012
2023-01-05 21:29:56 +00:00
Aaron Ballman
b4993bea29 Remove documentation about the Go bindings
We removed the Go bindings in https://reviews.llvm.org/D135436 but
missed documentation that talks about the bindings.
2023-01-05 14:49:28 -05:00
Roman Lebedev
e0ad2af691 [exegesis] "Skip codegen" dry-run mode
While "skip measurements mode" is super useful for test coverage,
i've come to discover it's trade-offs. It still calls back-end
to actually codegen the target assembly, and that is what is taking
80%+ of the time regardless of whether or not we skip the measurements.

On the other hand, just being able to see that exegesis can come up
with a snippet to measure something, is already very useful,
and takes maybe a second for a all-opcode sweep.

Reviewed By: gchatelet

Differential Revision: https://reviews.llvm.org/D140702
2023-01-05 17:47:17 +03:00
serge-sans-paille
38818b60c5 Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part
Use deduction guides instead of helper functions.

The only non-automatic changes have been:

1. ArrayRef(some_uint8_pointer, 0) needs to be changed into ArrayRef(some_uint8_pointer, (size_t)0) to avoid an ambiguous call with ArrayRef((uint8_t*), (uint8_t*))
2. CVSymbol sym(makeArrayRef(symStorage)); needed to be rewritten as CVSymbol sym{ArrayRef(symStorage)}; otherwise the compiler is confused and thinks we have a (bad) function prototype. There was a few similar situation across the codebase.
3. ADL doesn't seem to work the same for deduction-guides and functions, so at some point the llvm namespace must be explicitly stated.
4. The "reference mode" of makeArrayRef(ArrayRef<T> &) that acts as no-op is not supported (a constructor cannot achieve that).

Per reviewers' comment, some useless makeArrayRef have been removed in the process.

This is a follow-up to https://reviews.llvm.org/D140896 that introduced
the deduction guides.

Differential Revision: https://reviews.llvm.org/D140955
2023-01-05 14:11:08 +01:00
Freddy Ye
27b8f54f51 [X86] Support -march=emeraldrapids
Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D140950
2023-01-05 20:27:32 +08:00
Piyou Chen
20a1dcf572 [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension
Note: Support Svnapot extension in https://reviews.llvm.org/D136570

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D136816
2023-01-04 18:44:41 -08:00
Roman Lebedev
6a67b633b9 [exegesis] Analysis: filtering for benchmark results
By default, all benchmark results are analysed, but sometimes it may be useful
to only look at those that to not involve memory, or vice versa. This option
allows to either keep all benchmarks, or filter out (ignore) either all the
ones that do involve memory (involve instructions that may read or write to
memory), or the opposite, to only keep such benchmarks.

Personally, so far i have found the benchmarks that do involve memory
to have dubious results. But the ones that do not involve memory,
are generally actionable. So i would like to have a toggle to declutter results.

Reviewed By: courbet

Differential Revision: https://reviews.llvm.org/D140734
2023-01-04 21:16:11 +03:00
Aaron Ballman
5b216320ab Fix the LLVM sphinx build
This should address the issue found in:
https://lab.llvm.org/buildbot/#/builders/30/builds/30330
2023-01-04 10:30:48 -05:00
Yeting Kuo
1e9e1b9cf8 [VP][RISCV] Add vp.ctlz/cttz and RISC-V support.
The patch also adds expandVPCTLZ and expandVPCTTZ to expand vp.ctlz/cttz nodes
and the cost model of vp.ctlz/cttz.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140370
2023-01-04 15:15:01 +08:00
Tony Tye
817f64e7ce [AMDGPU][NFC] DWARF extensions minor update
1. Minor editorial corrections.
2. Allow different call frames to be associated with different target
   architectures in a single thread.

Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D140646
2023-01-03 23:49:12 +00:00
Jie Fu
902614d254 [docs] TestingGuide.rst: Fix incorrect description
This patch fixes two incorrect descriptions in TestingGuide.rst.

1. test/lit.site.cfg --> test/lit.site.cfg.py
   After https://reviews.llvm.org/D37838 , the `test/lit.site.cfg` had been added a .py extension.
   So it should be `test/lit.site.cfg.py`.

2. $(LLVM_OBJ_ROOT)/$(BuildMode)/bin --> $(LLVM_OBJ_ROOT)/bin
   The current build system doesn't create a $(BuildMode) directory any more.
   So it should be removed.

Reviewed By: mehdi_amini, MaskRay

Differential Revision: https://reviews.llvm.org/D140780
2022-12-30 23:31:33 -08:00
Yeting Kuo
bd9c0f082b [RISCV] Add Svpbmt extension support.
Spec of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D140692
2022-12-28 23:57:54 -08:00
Fangrui Song
ee9ccb1103 CodingStandards: restrict CamelCase variable names guideline to llvm/clang/clang-tools-extra/polly/bolt
See https://discourse.llvm.org/t/top-level-clang-tidy-options-and-variablename-suggestion-on-codingstandards/58783 ,
the CamelCase variable names guideline does not reflect the truth:
flang, libc, libclc, libcxx, libcxxabi, libunwind, lld, mlir, openmp,
and pstl use camelCase. lldb uses snake_case.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D140585
2022-12-28 12:48:13 -08:00
Jie Fu
00926c30be [RISCV] Fix typos in RISCVUsage.rst
Fix typos `riscv-toolchai-convention` --> `riscv-toolchain-convention`

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140717
2022-12-28 16:33:41 +08:00
tlattner
bb778cf36d Commit changes to the Code of Conduct that make it more clear regarding behavior outside of LLVM spaces that impact the safety of our community members. Discussion may be found here: https://discourse.llvm.org/t/code-of-conduct-changes-related-to-llvm-project-policy-changes/64197 2022-12-26 11:31:42 -08:00
Florian Hahn
60359f56aa Revert "[IPSCCP] Enable specialization of functions."
This reverts commit 2656572d48.

It looks like CINT2017rate/502.gcc_r gets mis-compiled with LTO + PGO on
AArch64 with function specialization.
2022-12-26 16:02:59 +00:00
Jojo R
54752f3ff6 [RISCV] Implement assembler support for XTHeadVdot
This patch implements the T-Head vendor extensions (XTHeadVdot),
which is documented here, it's based on standard vector extension v1.0:
  https://github.com/T-head-Semi/thead-extension-spec
2022-12-26 19:05:22 +08:00
Alexandros Lamprineas
2656572d48 [IPSCCP] Enable specialization of functions.
This patch enables Function Specialization by default at all
optimization levels except Os, Oz.

Compilation Time Overhead:
--------------------------
Measured the Instruction Count increase (Geomean) for CTMark from
the llvm-testsuite as in https://llvm-compile-time-tracker.com.
 * {-O3, Non-LTO}: +0.136% Instruction Count
 * {-O3, LTO}: +0.346% Instruction Count

Performance Uplift:
-------------------
Measured +9.121% score increase for 505.mcf_r from SPEC Int 2017
(Tested on Neoverse N1 with -O3 + LTO)

Correctness Testing:
--------------------
 * Passes bootstrap Clang with ASAN + LTO + FuncSpec aggressive options:
   { MaxClonesThreshold=10,
     SmallFunctionThreshold=10,
     AvgLoopIterationCount=30,
     SpecializeOnAddresses=true,
     EnableSpecializationForLiteralConstant=true,
     FuncSpecializationMaxIters=10 }
 * Builds Chromium and passes its unittests with the above options + ThinLTO.

For more info please refer to
https://discourse.llvm.org/t/rfc-should-we-enable-function-specialization/61518

Differential Revision: https://reviews.llvm.org/D140210
2022-12-25 10:05:21 +02:00
eopXD
40dd8ff331 [Doc] Replace PYTHON_EXECUTABLE with Python3_EXECUTABLE
As topic, the variable to specify the python executable now should be this.
This is probably something that was left out in D78762.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D140652
2022-12-24 23:38:58 -08:00
Nikita Popov
7d1ceb02d2 [Docs] Clarify typed pointers support timeline
As there have been a couple of questions about this recently, this
gives a hard timeline on typed pointers support.

Given that we are about a month away from LLVM 16 branching, I think
we should retain best-effort typed pointer support in LLVM 16 even
if we get all tests migrated before that point.

Conversely, regardless of what the actual test migration state will
be at that point, I believe we should un-support typed pointers as
a matter of policy immediately after branching. Once release/16.x
has been branched, typed pointers on main will no longer be
supported (and can be actively broken). We only need to keep
not-yet-migrated tests working, if there are any left at that point.

Differential Revision: https://reviews.llvm.org/D140487
2022-12-23 10:07:59 +01:00
Gulfem Savrun Yeniceri
70792cd4f8 [LangRef] Add description for nocallback attribute
This patch adds the description for nocallback attribute
that is implemented in https://reviews.llvm.org/D90275.

Differential Revision: https://reviews.llvm.org/D131628
2022-12-22 21:11:59 +00:00
Jessica Paquette
e0f5307f63 Fix indentation in LangRef.rst
Sphinx build was broken.
2022-12-22 11:44:46 -08:00
Jessica Paquette
7ef8f9c972 [IR/MachineOutliner] Add a "nooutline" function attr and respect it
Add `nooutline` + update LangRef to say it exists.

This makes it possible to say "don't outline from this function ever."

We want to be able to toggle whether or not a function should be in the search
set regardless of default behaviour.

Add testcases for the IR Outliner + Machine Outliner.

Also remove an unnecessary check for an empty function in the Machine Outliner.

Differential Revision: https://reviews.llvm.org/D140438
2022-12-22 10:22:08 -08:00
Paul Robinson
088b5d1ad3 [docs] Update an example 2022-12-21 08:41:38 -08:00
Paul Robinson
2549b8bdae [docs] Add tips on writing test constraints 2022-12-21 08:32:04 -08:00
Paul Robinson
566e34829f [lit] Document the 'target=<triple>' feature
Differential Revision: https://reviews.llvm.org/D139869
2022-12-21 06:10:48 -08:00
Dmitry Preobrazhensky
b8e1071a29 [AMDGPU][GFX11][DOC][NFC] Add GFX11 assembler syntax description 2022-12-21 12:49:48 +03:00
Phoebe Wang
e746a9a600 [Clang] Emit "min-legal-vector-width" attribute for X86 only
This is an alternative way of D139627 suggested by Craig. Creently only X86 backend uses this attribute. Let's just emit for X86 only.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139701
2022-12-21 11:54:05 +08:00
Joshua Cranmer
e6b02214c6 [IR] Add a target extension type to LLVM.
Target-extension types represent types that need to be preserved through
optimization, but otherwise are not introspectable by target-independent
optimizations. This patch doesn't add any uses of these types by an existing
backend, it only provides basic infrastructure such that these types would work
correctly.

Reviewed By: nikic, barannikov88

Differential Revision: https://reviews.llvm.org/D135202
2022-12-20 11:02:11 -05:00
Dmitry Preobrazhensky
d9daee5a66 [AMDGPU][DOC][NFC] Update assembler syntax description
Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Small improvements and clarifications.
- Correct typos.
2022-12-20 14:03:46 +03:00
Sameer Sahasrabuddhe
475ce4c200 RFC: Uniformity Analysis for Irreducible Control Flow
Uniformity analysis is a generalization of divergence analysis to
include irreducible control flow:

  1. The proposed spec presents a notion of "maximal convergence" that
     captures the existing convention of converging threads at the
     headers of natual loops.

  2. Maximal convergence is then extended to irreducible cycles. The
     identity of irreducible cycles is determined by the choices made
     in a depth-first traversal of the control flow graph. Uniformity
     analysis uses criteria that depend only on closed paths and not
     cycles, to determine maximal convergence. This makes it a
     conservative analysis that is independent of the effect of DFS on
     CycleInfo.

  3. The analysis is implemented as a template that can be
     instantiated for both LLVM IR and Machine IR.

Validation:
  - passes existing tests for divergence analysis
  - passes new tests with irreducible control flow
  - passes equivalent tests in MIR and GMIR

Based on concepts originally outlined by
Nicolai Haehnle <nicolai.haehnle@amd.com>

With contributions from Ruiling Song <ruiling.song@amd.com> and
Jay Foad <jay.foad@amd.com>.

Support for GMIR and lit tests for GMIR/MIR added by
Yashwant Singh <yashwant.singh@amd.com>.

Differential Revision: https://reviews.llvm.org/D130746
2022-12-20 07:22:24 +05:30
Qiu Chaofan
6cad2a95fb Fix 'underline too short' failure 2022-12-19 15:29:40 +08:00
Qiu Chaofan
a40ef656d8 [Intrinsic] Rename flt.rounds intrinsic to get.rounding
Address the inconsistency between FLT_ROUNDS_ and SET_ROUNDING SDAG
node. Rename FLT_ROUNDS_ to GET_ROUNDING and add llvm.get.rounding
intrinsic to replace flt.rounds.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D139507
2022-12-19 15:22:39 +08:00
David Goldblatt
61042d2806 [AA][Intrinsics] Add separate_storage assumptions.
This operand bundle on an assume informs alias analysis that the
arguments point to regions of memory that were allocated separately
(i.e. different heap allocations, different allocas, or different
globals).

As a safety measure, we leave the analysis flag-disabled by default.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D136514
2022-12-16 11:05:00 -08:00
Sprite
a9f9f3dff4 Correct typos (NFC)
Just found some typos while reading the llvm/circt project.

compliment -> complement
emitsd -> emits
2022-12-16 10:51:26 -08:00
Vasileios Porpodas
12c55eb66d [docs] Update docs since getBasicBlockList() is now private
Differential Revision: https://reviews.llvm.org/D140163
2022-12-15 21:41:24 -08:00
Vasileios Porpodas
32b38d248f [NFC] Rename Instruction::insertAt() to Instruction::insertInto(), to be consistent with BasicBlock::insertInto()
Differential Revision: https://reviews.llvm.org/D140085
2022-12-15 12:27:45 -08:00
Vasileios Porpodas
bc63a39326 [docs] Updates ProgrammersManual to reflect the change that BasicBlock::getInstList() is private.
Differential Revision: https://reviews.llvm.org/D140054
2022-12-14 14:07:15 -08:00
zhijian
a274d62fec [XCOFF] Decode the relocation entries of loader section of xcoff for llvm-readobj
Summary:

support decoding the relocation entries of loader section of xcoff for llvm-readobj

https://www.ibm.com/docs/en/aix/7.2?topic=formats-xcoff-object-file-format#XCOFF__vra3i31ejbau

Reviewers: James Henderson, Esme Yi
Differential Revision: https://reviews.llvm.org/D136787
2022-12-14 11:16:20 -05:00
Phoebe Wang
08b8adc656 [Docs] Added my office hours 2022-12-14 21:54:20 +08:00
Nikita Popov
e45cf47923 [Bitcode] Remove auto-detection for typed pointers
Always read bitcode according to the -opaque-pointers mode. Do not
perform auto-detection to implicitly switch to typed pointers.

This is a step towards removing typed pointer support, and also
eliminates the class of problems where linking may fail if a typed
pointer module is loaded before an opaque pointer module. (The
latest place where this was encountered is D139924, but this has
previously been fixed in other places doing bitcode linking as well.)

Differential Revision: https://reviews.llvm.org/D139940
2022-12-14 13:38:20 +01:00
Yeting Kuo
ad68586a37 [VP][RISCV] Add vp.ctpop and RISC-V support.
The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139920
2022-12-14 09:47:44 +08:00