Commit Graph

6 Commits

Author SHA1 Message Date
Aditya Nandakumar
cf85f31172 [GISel]: Fix base case for m_any_of PatternMatcher.
The base case for any_of was incorrectly returning true. Also add test
case which uses m_any_of(preds...) where none of the predicates are
true.

llvm-svn: 325848
2018-02-23 01:01:59 +00:00
Aditya Nandakumar
bab2d3e2b9 [GISel]: Add pattern matchers for G_BITCAST/PTRTOINT/INTTOPTR
Adds pattern matchers for the above along with unit tests for the same.
https://reviews.llvm.org/D43479

llvm-svn: 325542
2018-02-19 23:11:53 +00:00
Volkan Keles
02bb1747a3 GlobalISel: Add templated functions and pattern matcher support for some more opcodes
Summary:
This patch adds templated functions to MachineIRBuilder for some opcodes
and adds pattern matcher support for G_AND and G_OR.

Reviewers: aditya_nandakumar

Reviewed By: aditya_nandakumar

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D43309

llvm-svn: 325162
2018-02-14 19:58:36 +00:00
Aditya Nandakumar
6250b18831 [GISel]: Add Pattern Matcher for G_FMUL.
https://reviews.llvm.org/D43206

llvm-svn: 325044
2018-02-13 20:09:13 +00:00
Puyan Lotfi
43e94b15ea Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00
Aditya Nandakumar
2036f44654 Add support for pattern matching MachineInsts.
https://reviews.llvm.org/D42439

Add Instcombine like matchers for MachineInstructions. There are only
globalISel matchers for now.

llvm-svn: 323400
2018-01-25 02:53:06 +00:00