Commit Graph

320 Commits

Author SHA1 Message Date
Craig Topper
31aa7d2de0 [RISCV] Use riscv_bitmanip.h in zbb.c. NFC
I missed this when converting other scalar bitmanip/crypto tests
to use intrinsics intead of builtins.
2023-12-22 20:10:37 -08:00
Eric Biggers
09058654f6 [RISCV] Remove experimental from Vector Crypto extensions (#74213)
The RISC-V vector crypto extensions have been ratified. This patch
updates the Clang and LLVM support for these extensions to be
non-experimental, while leaving the C intrinsics as experimental since
the C intrinsics are not yet standardized.

Co-authored-by: Brandon Wu <brandon.wu@sifive.com>
2023-12-18 22:04:22 -08:00
Kazu Hirata
8f1accfb35 Revert "[RISCV] Update the interface of sifive vqmaccqoq (#74284)"
This reverts commit dc55703196.

Several bots seem to be failing:

https://lab.llvm.org/buildbot/#/builders/10/builds/34651
https://lab.llvm.org/buildbot/#/builders/178/builds/6320
https://lab.llvm.org/buildbot/#/builders/77/builds/32918
2023-12-11 22:46:43 -08:00
Brandon Wu
dc55703196 [RISCV] Update the interface of sifive vqmaccqoq (#74284)
The
spec(https://sifive.cdn.prismic.io/sifive/60d5a660-3af0-49a3-a904-d2bbb1a21517_int8-matmul-spec.pdf)
is updated.
2023-12-12 13:17:47 +08:00
Craig Topper
0d44c9f99a [RISCV] Shorten diagnostic a bit.
The "to be enabled" seemed unnecessary.
2023-12-11 12:45:27 -08:00
Philip Reames
99c0a3ea98 [RISCV] Enable target attribute when invoked through clang driver (#74889)
d80e46d added support for the target function attribute. However, it
turns out that commit has a nasty bug/oversight. As the tests in that
revision show, everything works if clang -cc1 is directly invoked. I was
suprised to learn this morning that compiling with clang (i.e. the
typical user workflow) did not work.

The bug is that if a set of explicit negative extensions is passed to
cc1 at the command line (as the clang driver always does), we were
copying these negative extensions to the end of the rewritten extension
list. When this was later parsed, this had the effect of turning back
off any extension that the target attribute had enabled.

This patch updates the logic to only propagate the features from the
input which don't appear in the rewritten form in either positive or
negative form.

Note that this code structure is still highly suspect. In particular I'm
fairly sure that mixing extension versions with this code will result in
odd results. However, I figure its better to have something which mostly
works than something which doesn't work at all.
2023-12-11 08:55:21 -08:00
Craig Topper
1a3b14d261 [RISCV] Add C intrinsics for scalar bitmanip and crypto
This adds riscv_bitmanip and riscv_crypto.h

This is based on the proposed spec here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

Tests that previously used builtins directly now use the intrinsics.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155647
2023-11-24 16:17:22 -08:00
Piyou Chen
d80e46da7d [RISCV] Support target attribute for function
The proposal of target attribute is https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35

This patch implements it by emitting .option arch during codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D151730
2023-11-23 23:05:21 -08:00
Ramkumar Ramachandra
083a539717 clang/CodeGen/RISCV: test lowering of math builtins (#71399)
Ever since 98c90a1 (ISel: introduce vector ISD::LRINT, ISD::LLRINT;
custom RISCV lowering) landed, there have been several discussions on
how the lrint and llrint libcalls would lower to LLVM IR via clang on
RV32 and RV64, in an effort to enable vectorization of lrint and llrint
via SLPVectorizer and LoopVectorize. This patch adds a new
math-builtins.c test to the RISC-V target to test the lowering of all
math libcalls, including lrint and llrint.
2023-11-23 07:39:32 +00:00
Brandon Wu
2749f52ec4 [RISCV] Convert all floating point vector type operands to integer vector type (#69559) 2023-11-21 23:19:10 +08:00
Yueh-Ting (eop) Chen
1c93781918 Recommit "[Clang][RISCV] Introduce tuple types for RVV bfloat16 #72216" (#72370)
This PR attempts to recommit the PR (#72216) with a safe-bounded TypeID
that will not cause indeterminate results for the compiler.
2023-11-16 08:25:54 +08:00
Yueh-Ting (eop) Chen
5107a47fee Revert "[Clang][RISCV] Introduce tuple types for RVV bfloat16 (#72216)" (#72367)
This reverts commit 8434b0b9d3. #72216 

This commit broke the multiple buildbots, looks like the extension in
`NUM_PREDEF_TYPE_IDS` might have broken some inheriting usages, causing
indeterminate results for the compiler. Investigating the issue now.
2023-11-15 18:05:07 +08:00
Yueh-Ting (eop) Chen
8434b0b9d3 [Clang][RISCV] Introduce tuple types for RVV bfloat16 (#72216)
The first commit extends the capacity from the compiler infrastructure,
and the second commit continues the effort in #71140 to introduce tuple
types for bfloat16.
2023-11-15 13:50:14 +08:00
Shao-Ce SUN
fbdf6e2724 [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (#71140)
BF16 implementation based on @joshua-arch1's
https://reviews.llvm.org/D152498
Fixed the incorrect f16 type introduced in
https://github.com/llvm/llvm-project/pull/68296

---------

Co-authored-by: Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
2023-11-06 11:22:14 +08:00
Brandon Wu
74f38df1d1 [RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
FP32-to-int8 Ranged Clip Instructions

https://sifive.cdn.prismic.io/sifive/0aacff47-f530-43dc-8446-5caa2260ece0_xsfvfnrclipxfqf-spec.pdf
2023-11-03 10:52:37 +08:00
Brandon Wu
945d2e6e60 [RISCV] Support Xsfvfwmaccqqq extensions (#68296)
Bfloat16 Matrix Multiply Accumulate Instruction

https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf
2023-11-03 10:08:26 +08:00
Yueh-Ting (eop) Chen
d4a885fcbc [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (#70355)
riscv-non-isa/rvv-intrinsic-doc#288
2023-10-31 23:23:32 +08:00
Yueh-Ting (eop) Chen
e9ff4e4291 [Clang][RISCV] Add vundefine intrinsics for tuple types (#70354)
riscv-non-isa/rvv-intrinsic-doc#288
2023-10-30 21:59:02 +08:00
Fangrui Song
7e42545524 [Driver] Reject unsupported -mcmodel= (#70262)
-mcmodel= is supported for a few architectures. Reject the option for
other architectures.

* -mcmodel= is unsupported on x86-32.
* -mcmodel=large is unsupported for PIC on AArch64.
* -mcmodel= is unsupported for aarch64_32 triples.
* https://reviews.llvm.org/D67066 (for RISC-V) made
-mcmodel=medany/-mcmodel=medlow aliases for all architectures. Restrict
this to RISC-V.
* llvm/lib/Target/Sparc has some small/medium/large support, but the
values listed on https://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html
had been supported before https://reviews.llvm.org/D67066. Consider
-mcmodel= unsupported for Sparc.
* https://reviews.llvm.org/D106371 translated -mcmodel=medium to
-mcmodel=large on AIX, even for 32-bit systems. Retain this behavior but
reject -mcmodel= for other PPC32 systems.

In general the accept/reject behavior is more similar to GCC.

err_drv_invalid_argument_to_option is less clear than
err_drv_unsupported_option_argument. As the supported values are
different for
different architectures, add a
err_drv_unsupported_option_argument_for_target
for better clarity.
2023-10-26 14:15:36 -07:00
Wang Pengcheng
0e27cbe187 [RISCV] Run mem2reg to simplify Zbc tests (#70169) 2023-10-25 16:23:32 +08:00
Wang Pengcheng
05b5188c12 [Clang][RISCV] Support CSRs in clobbered registers of inline assembly (#67646)
To match GCC's behaviors.

Fixes #67596
2023-10-23 11:15:20 +08:00
Brandon Wu
d1985e3d1f [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
SiFive Int8 Matrix Multiplication Extensions Specification

https://sifive.cdn.prismic.io/sifive/c4f0e51d-4dd3-402a-98bc-1ffad6011259_int8-matmul-spec.pdf
2023-10-20 11:16:20 +08:00
Yeting Kuo
9ea083f2d4 [Clang][test] Replace legacy -target with --target=. (#66572) 2023-09-18 15:35:57 +08:00
Jianjian GUAN
4d2536c82f [RISCV] Enable more builtin for zvfhmin without zvfh
This patch enables some fp16 vector type builtins that don't use fp arithmetic instruction for zvfhmin without zvfh.
Include following builtins:
  vector load/store,
  vector reinterpret,
  vmerge_vvm,
  vmv_v.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D151869
2023-09-08 10:55:17 +08:00
4vtomat
8609819eb1 [RISCV] Add feature checks for vector crypto C intrinsics
Differential Revision: https://reviews.llvm.org/D158257
2023-08-30 21:03:08 -07:00
4vtomat
bb47721fb7 [RISCV][NFC] Update compile options for some vector crypto C intrinsics
Differential Revision: https://reviews.llvm.org/D158255
2023-08-30 20:29:29 -07:00
eopXD
a173edc987 [NFC][Clang][RISCV] Move test case to its corret belonging
Signed-off by: eop Chen <eop.chen@sifive.com>
2023-08-24 09:02:12 -07:00
Jianjian GUAN
654fa9a7e8 [RISCV] Add Zvfhmin extension for clang
This patch adds the Zvfhmin extension for clang.

Reviewed By: craig.topper, michaelmaitland

Differential Revision: https://reviews.llvm.org/D150253
2023-08-23 17:08:39 +08:00
eopXD
39a41c8905 [CGCall][RISCV] Handle function calls with parameter of RVV tuple type
This was an oversight in D146872, where function calls with tuple type
was not covered. This commit fixes this.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157953
2023-08-22 23:41:23 -07:00
eopXD
0f481f2ff7 [Clang][RISCV] Add vcreate intrinsics for RVV tuple types
Specification PR: riscv-non-isa/rvv-intrinsic-doc#256

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158402
2023-08-22 23:36:53 -07:00
4vtomat
29f11e4fb7 [RISCV] Bump vector crypto to v1.0 RC2
Differential Revision: https://reviews.llvm.org/D158067
2023-08-17 21:19:59 -07:00
Jianjian GUAN
f808788487 [RISCV] Remove experimental for zihintntl
Since zihintntl is ratified now, we could remove the experimental prefix and change its version to 1.0.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D151547
2023-08-10 17:04:49 +08:00
4vtomat
2a05a5215f [RISCV] Support vector crypto extension C intrinsics
Depends on D141672, D138809

Differential Revision: https://reviews.llvm.org/D138810
2023-08-08 17:09:49 -07:00
Alex Bradbury
e3c57fdd84 [clang][RISCV] Fix bug in ABI handling of empty structs with hard FP calling conventions in C++
As reported in <https://github.com/llvm/llvm-project/issues/58929>,
Clang's handling of empty structs in the case of small structs that may
be eligible to be passed using the hard FP calling convention doesn't
match g++. In general, C++ record fields are never empty unless
[[no_unique_address]] is used, but the RISC-V FP ABI overrides this.

After this patch, fields of structs that contain empty records will be
ignored, even in C++, when considering eligibility for the FP calling
convention ('flattening'). It isn't explicitly noted in the RISC-V
psABI, but arrays of empty records will disqualify a struct for
consideration of using the FP calling convention in g++. This patch
matches that behaviour. The psABI issue
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/358> seeks
to clarify this.

This patch was previously committed but reverted after a bug was found.
This recommit adds additional logic to prevent that bug (adding an extra
check for when a candidate from detectFPCCEligibleStructHelper may not
be valid).

Differential Revision: https://reviews.llvm.org/D142327
2023-08-07 10:45:22 +01:00
Piyou Chen
2df05cd01c [RISCV] Support overloaded version ntlh intrinsic function
Here is the proposal https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47.

The version that omit the domain argument imply domain=__RISCV_NTLH_ALL.

```
type __riscv_ntl_load (type *ptr);
void __riscv_ntl_store (type *ptr, type val);
```

Reviewed By: kito-cheng, craig.topper

Differential Revision: https://reviews.llvm.org/D156221
2023-08-04 00:39:25 -07:00
4vtomat
f3ce925083 [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp
This patch does a few things:
  1. Add a new type called Undefined to ScalarTypeKind.
  2. Make RVVType::applyModifier early return when encounter invalid
     ScalarType, otherwise it could be modified to "non-invalid" type in the following code.
  3. When FixedLMULType::SmallerThan is applied, the lmul should be "<" than
     specified one, so lmuls which are ">=" should be marked as invalid.

Differential Revision: https://reviews.llvm.org/D156223
2023-08-03 01:48:23 -07:00
Craig Topper
36ac6ac1db [RISCV] Merge rv32 and rv64 Zvb* intrinsic tests. NFC
There was some duplication between these tests and
we can merge them by checking __riscv_xlen for the parts
that aren't duplicated.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D156851
2023-08-02 00:08:01 -07:00
Craig Topper
244fd4dfc5 [RISCV] Run mem2reg on more scalar C builtin tests to remove allocas and simplify checks. NFC 2023-08-01 22:10:54 -07:00
Jun Sha (Joshua)
a5791bfef4 [RISCV][BF16] Enable __bf16 for riscv targets
The RISC-V psABI recently added __bf16 in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367.
Now we can enable this new type in clang.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150929
2023-08-01 13:59:27 +08:00
eopXD
7cb81c1b8c [Clang][RISCV] Remove RVV intrinsics vread_csr,vwrite_csr
As proposed in riscv-non-isa/rvv-intrinsic-doc#249, removing the interface.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D156321
2023-07-26 22:33:41 -07:00
Alex Bradbury
0fa004e072 Revert "[clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++"
This reverts commit 17a58b3ca7 and the
minor documentation fix 569e99a471.

An issue was reported in https://reviews.llvm.org/D142327#inline-1510301
so reverting until it can be investigated and fixed.
2023-07-24 16:58:48 +01:00
Alex Bradbury
17a58b3ca7 [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++
As reported in <https://github.com/llvm/llvm-project/issues/58929>,
Clang's handling of empty structs in the case of small structs that may
be eligible to be passed using the hard FP calling convention doesn't
match g++. In general, C++ record fields are never empty unless
[[no_unique_address]] is used, but the RISC-V FP ABI overrides this.

After this patch, fields of structs that contain empty records will be
ignored, even in C++, when considering eligibility for the FP calling
convention ('flattening'). See also the relevant psABI issue
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/358> which
seeks to clarify the documentation.

Fixes https://github.com/llvm/llvm-project/issues/58929

Differential Revision: https://reviews.llvm.org/D142327
2023-07-24 10:24:34 +01:00
Craig Topper
7fb0f4a6eb [RISCV] Run mem2reg on the scalar C builtin tests to remove allocas and simplify checks. NFC
As requested on D155647.
2023-07-19 10:30:42 -07:00
Craig Topper
3055c5815a [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
This has been ratified according to https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Differential Revision: https://reviews.llvm.org/D155668
2023-07-19 10:03:57 -07:00
eopXD
c4a5b58497 [Clang][RISCV] Guard RVV intrinsics types that is not available when ELEN < 64
(ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1)
requires at least `zve64x`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155414
2023-07-18 18:57:33 -07:00
Craig Topper
8e6482115c [RISCV] Remove unnecessary _32 and _64 suffixes from some scalar crypto builtins.
The names of these builtins aren't ambiguous so they don't need the suffix.
2023-07-18 12:56:01 -07:00
Craig Topper
a64b3e92c7 [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
Previously we returned i32 on RV32 and i64 on RV64. The instructions
only consume 32 bits and only produce 32 bits. For RV64, the result
is sign extended to 64 bits like *W instructions.

This patch removes this detail from the interface to improve
portability and consistency. This matches the proposal for scalar
intrinsics here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

I've included IR autoupgrade support as well.

I'll be doing this for other builtins/intrinsics that currently use
'long' in other patches.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D154647
2023-07-17 08:58:29 -07:00
Craig Topper
599421ae36 [RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins.
Unsigned is a better representation for bitmanipulation and cryptography.w

The only exception being the return values for clz and ctz intrinsics is
a signed int. That matches the target independent clz and ctz builtins.

This is consistent with the current scalar crypto proposal
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D154616
2023-07-15 11:19:18 -07:00
Craig Topper
143e2c2ac0 [RISCV] Split clmul/clmulh/clmulr builtins into _32 and _64 versions.
This removes another use of 'long' to mean xlen from builtins.

I've also converted the types to unsigned as proposed in D154616.

clmul_32 is available to RV64 as its emulation is clmul+sext.w
clmulh_32 and clmulr_32 are not available on RV64 as their emulation
is currently 6 instructions in the worst case.
2023-07-14 19:09:15 -07:00
Craig Topper
df71216d03 [RISCV] Make __builtin_riscv_clz/ctz return an unsigned int instead of signed int.
This is different than the target independent __builtin_clz/ctz, but
logically makes more sense.
2023-07-14 11:13:47 -07:00