Commit Graph

1815 Commits

Author SHA1 Message Date
Tomas Matheson
92dc23c0e0 [AArch64] add missing test case for v9.4-A 2023-12-21 14:18:33 +00:00
Michael Spencer
a171d248ca [clang][modules] Deprecate module.map in favor of module.modulemap (#75142)
This patch deprecates `module.map` in favor of `module.modulemap`, which
has been the preferred form since 2014. The eventual goal is to remove
support for `module.map` to reduce the number of stats Clang needs to do
while searching for module map files.

This patch touches a lot of files, but the majority of them are just
renaming tests or references to the file in comments or documentation.

The relevant files are:
* lib/Lex/HeaderSearch.cpp
* include/clang/Basic/DiagnosticGroups.td
* include/clang/Basic/DiagnosticLexKinds.td
2023-12-14 14:03:57 -08:00
Yeting Kuo
6095e21130 [RISCV] Bump zicfilp to 0.4 (#75134)
Bump to https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0. Actually
there is no functional change here.
2023-12-13 14:50:24 +08:00
Fangrui Song
1c830b787c [Preprocessor] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 for AArch64 (#74954)
GCC sets `#define HAVE_atomic_compare_and_swapti 1` and therefore
defines `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16`.

Clang compiles the 16-byte legacy `__sync_bool_compare_and_swap` and new
`__atomic_compare_exchange` compile to LDXP/STXP or (with LSE)
CASP{,A,L,AL}.

Link: https://github.com/llvm/llvm-project/issues/71883
2023-12-11 23:09:14 -08:00
Zahira Ammarguellat
b40c534656 [clang] Add support for -fcx-limited-range, #pragma CX_LIMITED_RANGE and -fcx-fortran-rules. (#70244)
This patch adds the #pragma CX_LIMITED_RANGE defined in the C
specification.
It also adds the options -f[no]cx-limited-range and
-f[no]cx-fortran-rules.
-fcx-limited-range enables algebraic formulas for complex multiplication
and division. This option is enabled with -ffast-math.
-fcx-fortran-rules enables algebraic formulas for complex multiplication
and enables Smith’s algorithm for complex division (SMITH, R. L.
Algorithm 116: Complex division. Commun. ACM 5, 8 (1962)).

---------

Signed-off-by: Med Ismail Bennani <ismail@bennani.ma>
Co-authored-by: Joseph Huber <jhuber6@vols.utk.edu>
Co-authored-by: Guray Ozen <guray.ozen@gmail.com>
Co-authored-by: Nishant Patel <nishant.b.patel@intel.com>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Petr Hosek <phosek@google.com>
Co-authored-by: Joseph Huber <35342157+jhuber6@users.noreply.github.com>
Co-authored-by: Craig Topper <craig.topper@sifive.com>
Co-authored-by: Alexander Yermolovich <43973793+ayermolo@users.noreply.github.com>
Co-authored-by: Usama Hameed <u_hameed@apple.com>
Co-authored-by: Philip Reames <preames@rivosinc.com>
Co-authored-by: Evgenii Kudriashov <evgenii.kudriashov@intel.com>
Co-authored-by: Fangrui Song <i@maskray.me>
Co-authored-by: Aart Bik <39774503+aartbik@users.noreply.github.com>
Co-authored-by: Valentin Clement <clementval@gmail.com>
Co-authored-by: Youngsuk Kim <youngsuk.kim@hpe.com>
Co-authored-by: Arthur Eubanks <aeubanks@google.com>
Co-authored-by: Jan Svoboda <jan_svoboda@apple.com>
Co-authored-by: Walter Erquinigo <a20012251@gmail.com>
Co-authored-by: Eric <eric@efcs.ca>
Co-authored-by: Fazlay Rabbi <106703039+mdfazlay@users.noreply.github.com>
Co-authored-by: Pete Lawrence <plawrence@apple.com>
Co-authored-by: Jonas Devlieghere <jonas@devlieghere.com>
Co-authored-by: Adrian Prantl <aprantl@apple.com>
Co-authored-by: Owen Pan <owenpiano@gmail.com>
Co-authored-by: LLVM GN Syncbot <llvmgnsyncbot@gmail.com>
Co-authored-by: Med Ismail Bennani <ismail@bennani.ma>
Co-authored-by: Congcong Cai <congcongcai0907@163.com>
Co-authored-by: Rik Huijzer <github@huijzer.xyz>
Co-authored-by: Wang Pengcheng <wangpengcheng.pp@bytedance.com>
Co-authored-by: Yuanfang Chen <tabloid.adroit@gmail.com>
Co-authored-by: Kazu Hirata <kazu@google.com>
Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
Co-authored-by: Aiden Grossman <agrossman154@yahoo.com>
Co-authored-by: Rana Pratap Reddy <109514914+ranapratap55@users.noreply.github.com>
Co-authored-by: Yingwei Zheng <dtcxzyw2333@gmail.com>
Co-authored-by: Piotr Zegar <me@piotrzegar.pl>
Co-authored-by: KAWASHIMA Takahiro <t-kawashima@fujitsu.com>
Co-authored-by: Tobias Hieta <tobias@hieta.se>
Co-authored-by: Luke Lau <luke@igalia.com>
Co-authored-by: Shivam Gupta <shivam98.tkg@gmail.com>
Co-authored-by: cor3ntin <corentinjabot@gmail.com>
Co-authored-by: Yeting Kuo <46629943+yetingk@users.noreply.github.com>
Co-authored-by: Stanislav Mekhanoshin <rampitec@users.noreply.github.com>
Co-authored-by: David Spickett <david.spickett@linaro.org>
Co-authored-by: Matthew Devereau <matthew.devereau@arm.com>
Co-authored-by: Martin Storsjö <martin@martin.st>
Co-authored-by: Qiu Chaofan <qiucofan@cn.ibm.com>
Co-authored-by: Pierre van Houtryve <pierre.vanhoutryve@amd.com>
Co-authored-by: Mikael Holmen <mikael.holmen@ericsson.com>
Co-authored-by: Uday Bondhugula <uday@polymagelabs.com>
Co-authored-by: Nikita Popov <npopov@redhat.com>
Co-authored-by: Johannes Reifferscheid <jreiffers@google.com>
Co-authored-by: Benjamin Kramer <benny.kra@googlemail.com>
Co-authored-by: Oliver Stannard <oliver.stannard@arm.com>
Co-authored-by: Dmitry Vyukov <dvyukov@google.com>
Co-authored-by: Benjamin Maxwell <benjamin.maxwell@arm.com>
Co-authored-by: Piotr Sobczak <piotr.sobczak@amd.com>
Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
Co-authored-by: Timm Bäder <tbaeder@redhat.com>
Co-authored-by: Sunil Kuravinakop <koops@hpe.com>
Co-authored-by: zhongyunde 00443407 <zhongyunde@huawei.com>
Co-authored-by: Christudasan Devadasan <Christudasan.Devadasan@amd.com>
Co-authored-by: bjacob <jacob.benoit.1@gmail.com>
Co-authored-by: Weining Lu <luweining@loongson.cn>
Co-authored-by: Andrzej Warzyński <andrzej.warzynski@arm.com>
Co-authored-by: Jay Foad <jay.foad@amd.com>
Co-authored-by: Markus Mützel <markus.muetzel@gmx.de>
Co-authored-by: Erik Jonsson <erik.j.jonsson@ericsson.com>
Co-authored-by: Pete Steinfeld <47540744+psteinfeld@users.noreply.github.com>
Co-authored-by: Alexey Bataev <a.bataev@outlook.com>
Co-authored-by: Louis Dionne <ldionne.2@gmail.com>
Co-authored-by: Qizhi Hu <836744285@qq.com>
2023-12-11 10:03:27 -05:00
Joseph Huber
4e80bc7d71 [Clang] Introduce scoped variants of GNU atomic functions (#72280)
Summary:
The standard GNU atomic operations are a very common way to target
hardware atomics on the device. With more heterogenous devices being
introduced, the concept of memory scopes has been in the LLVM language
for awhile via the `syncscope` modifier. For targets, such as the GPU,
this can change code generation depending on whether or not we only need
to be consistent with the memory ordering with the entire system, the
single GPU device, or lower.

Previously these scopes were only exported via the `opencl` and `hip`
variants of these functions. However, this made it difficult to use
outside of those languages and the semantics were different from the
standard GNU versions. This patch introduces a `__scoped_atomic` variant
for the common functions. There was some discussion over whether or not
these should be overloads of the existing ones, or simply new variants.
I leant towards new variants to be less disruptive.

The scope here can be one of the following

```
__MEMORY_SCOPE_SYSTEM // All devices and systems
__MEMORY_SCOPE_DEVICE // Just this device
__MEMORY_SCOPE_WRKGRP // A 'work-group' AKA CUDA block
__MEMORY_SCOPE_WVFRNT // A 'wavefront' AKA CUDA warp
__MEMORY_SCOPE_SINGLE // A single thread.
```
Naming consistency was attempted, but it is difficult to capture to full
spectrum with no many names. Suggestions appreciated.
2023-12-07 13:40:25 -06:00
Shengchen Kan
6d6baef5c9 [X86] Support CFE flags for APX features (#74199)
Positive options: -mapx-features=<comma-separated-features>
Negative options: -mno-apx-features=<comma-separated-features>

-m[no-]apx-features is designed to be able to control separate APX
features.

Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>

Behaviour when positive and negative options are used together:

For boolean flags, the last one wins

-mapxf   -mno-apxf   -> -mno-apxf
-mno-apxf   -mapxf   -> -mapxf

For flags that take a set as arguments, it sets the mask by order of the
flags

-mapx-features=egpr,ndd  -mno-apx-features=egpr  ->   -egpr,+ndd
-mapx-features=egpr  -mno-apx-features=egpr,ndd  ->   -egpr,-ndd
-mno-apx-features=egpr  -mapx-features=egpr,ndd  ->   +egpr,+ndd
-mno-apx-features=egpr,ndd  -mapx-features=egpr  ->   -ndd,+egpr

The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
2023-12-04 19:22:56 +08:00
Aaron Ballman
1d05b21e03 Add test coverage for -Wunknown-directives; NFC
While working on #embed, I noticed that the PR accidentally broke the
warning group but no tests failed as a result. This is adding the
missing test coverage.
2023-11-30 11:00:46 -05:00
Erich Keane
ff219ea9ca [OpenACC] Initial commits to support OpenACC (#70234)
Initial commits to support OpenACC.  This patchset:

adds a clang-command line argument '-fopenacc', and starts
 to define _OPENACC, albeit to '1' instead of the standardized
value (since we don't properly implement OpenACC yet).

The OpenACC spec defines `_OPENACC` to be equal to the latest standard
implemented. However, since we're not done implementing any standard,
we've defined this by default to be `1`. As it is useful to run our
compiler against existing OpenACC workloads, we're providing a
temporary override flag to change the `_OPENACC` value to be any
entirely digit value, permitting testing against any existing OpenACC
project.

Exactly like the OpenMP parser, the OpenACC pragma parser needs to
consume and reprocess the tokens. This patch sets up the infrastructure
to do so by refactoring the OpenMP version of this into a more general
version that works for OpenACC as well.

Additionally, this adds a few diagnostics and token kinds to get us
started.
2023-11-17 06:29:02 -08:00
Lucas Duarte Prates
59b2301508 [AArch64] Introduce the Armv9.5-A architecture version (#72392)
This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.

Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/

Patch by Oliver Stannard.
2023-11-16 15:38:32 +00:00
LiaoChunyu
71a7108ee9 [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158824
2023-11-16 09:46:11 +08:00
yonghong-song
4e67234357 [Clang][BPF] Add __BPF_CPU_VERSION__ macro (#71856)
Sometimes bpf developer might want to develop different codes
based on particular cpu versioins. For example, cpu v1/v2/v3
branch target is 16bit while cpu v4 branch target is 32bit,
thus cpu v4 allows more aggressive loop unrolling than cpu v1/v2/v3
(see [1] for a kernel selftest failure due to this).
We would like to maintain aggressive loop unrolling for cpu v4
while limit loop unrolling for earlier cpu versions.
Another example, signed divide also only available with cpu v4.

Actually, adding cpu specific macros are fairly common
in llvm. For example, x86 has maco like 'i486', '__pentium_mmx__', etc.
AArch64 has '__ARM_NEON', '__ARM_FEATURE_SVE', etc.

This patch added __BPF_CPU_VERSION__ macro. Current possible values
are 0/1/2/3/4. The following are the -mcpu=... to __BPF_CPU_VERSION__
mapping:
```
       cpu                  __BPF_CPU_VERSION__
       no -mcpu=<...>       1
       -mcpu=v1             1
       -mcpu=v2             2
       -mcpu=v3             3
       -mcpu=v4             4
       -mcpu=generic        1
       -mcpu=probe          0
```
    
This patch also added some macros for developers to identify some cpu
insn features:
```
      feature macro               enabled in which cpu
      __BPF_FEATURE_JMP_EXT       >= v2
      __BPF_FEATURE_JMP32         >= v3
      __BPF_FEATURE_ALU32         >= v3
      __BPF_FEATURE_LDSX          >= v4
      __BPF_FEATURE_MOVSX         >= v4
      __BPF_FEATURE_BSWAP         >= v4
      __BPF_FEATURE_SDIV_SMOD     >= v4
      __BPF_FEATURE_GOTOL         >= v4
      __BPF_FEATURE_ST            >= v4
```    
[1]
https://lore.kernel.org/bpf/3e3a8a30-dde0-43a1-981e-2274962780ef@linux.dev/
2023-11-10 10:18:54 -08:00
Arthur Eubanks
955dd8800b Revert "Reland [clang] Canonicalize system headers in dependency file when -canonical-prefixes" (#71697)
This reverts commit 578a4716f5.

This causes multiple issues. Compile time slowdown due to more path
canonicalization, and weird behavior on Windows.

Will reland under a separate flag `-f[no-]canonical-system-headers` to
match gcc in the future and further limit when it's passed by default.

Fixes #70011.
2023-11-08 11:43:35 -08:00
Phoebe Wang
c78aeabaec [X86] Add a EVEX256 macro to match with GCC and MSVC (#71317) 2023-11-07 14:39:24 +08:00
Fangrui Song
071f3b5b65 [Modules] Fix ModuleDeclState transition when module is used as a regular identifier (#71134)
`ModuleDeclState` is incorrectly changed to `NamedModuleImplementation`
for `struct module {}; void foo(module a);`. This is mostly benign but
leads to a spurious warning after #69555.

A real world example is:
```
// pybind11.h
class module_ { ... };
using module = module_;

// tensorflow
void DefineMetricsModule(pybind11::module main_module);
// `module main_module);` incorrectly changes `ModuleDeclState` to `NamedModuleImplementation`

#include <algorithm> // spurious warning
```
2023-11-02 22:13:08 -07:00
Brandon Wu
74f38df1d1 [RISCV] Support Xsfvfnrclipxfqf extensions (#68297)
FP32-to-int8 Ranged Clip Instructions

https://sifive.cdn.prismic.io/sifive/0aacff47-f530-43dc-8446-5caa2260ece0_xsfvfnrclipxfqf-spec.pdf
2023-11-03 10:52:37 +08:00
Brandon Wu
945d2e6e60 [RISCV] Support Xsfvfwmaccqqq extensions (#68296)
Bfloat16 Matrix Multiply Accumulate Instruction

https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf
2023-11-03 10:08:26 +08:00
Chuanqi Xu
0d21436114 [C++20] [Modules] Warn if we found #include <filename> in module purview (#69555)
Close https://github.com/llvm/llvm-project/issues/68615.

It is generally wrong to include <filename> in the module purview.
Although there are cases to include files in the module purview,
generally these use cases should include files by quotes instead of by
angles. Here we think the files got included by angles are the system
headers.

This is consistency with MSVC too:
https://learn.microsoft.com/en-us/cpp/error-messages/compiler-warnings/compiler-warnings-by-compiler-version?view=msvc-170#warnings-introduced-in-visual-studio-2022-version-170-compiler-version-1930
2023-11-02 16:40:20 +08:00
licongtian
8d4e35600f [Clang][LoongArch] Support compiler options -mlsx/-mlasx for clang
This patch adds compiler options -mlsx/-mlasx which enables the
instruction sets of LSX and LASX, and sets related predefined macros
according to the options.
2023-10-31 15:52:05 +08:00
Brad Smith
9925801c7e [Preprocessor][test] Add Haiku 2023-10-30 02:37:05 -04:00
Fangrui Song
7e42545524 [Driver] Reject unsupported -mcmodel= (#70262)
-mcmodel= is supported for a few architectures. Reject the option for
other architectures.

* -mcmodel= is unsupported on x86-32.
* -mcmodel=large is unsupported for PIC on AArch64.
* -mcmodel= is unsupported for aarch64_32 triples.
* https://reviews.llvm.org/D67066 (for RISC-V) made
-mcmodel=medany/-mcmodel=medlow aliases for all architectures. Restrict
this to RISC-V.
* llvm/lib/Target/Sparc has some small/medium/large support, but the
values listed on https://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html
had been supported before https://reviews.llvm.org/D67066. Consider
-mcmodel= unsupported for Sparc.
* https://reviews.llvm.org/D106371 translated -mcmodel=medium to
-mcmodel=large on AIX, even for 32-bit systems. Retain this behavior but
reject -mcmodel= for other PPC32 systems.

In general the accept/reject behavior is more similar to GCC.

err_drv_invalid_argument_to_option is less clear than
err_drv_unsupported_option_argument. As the supported values are
different for
different architectures, add a
err_drv_unsupported_option_argument_for_target
for better clarity.
2023-10-26 14:15:36 -07:00
Yeting Kuo
6e2d67e7d6 [RISCV] Support predefined macro __riscv_misaligned_[fast,avoid]. (#65756)
RISC-V C API introduced predefined macro to achieve hints about
unaligned accesses ([pr]). This patch defines __riscv_misaligned_fast
when using -mno-strict-align, otherwise, defines
__riscv_misaligned_avoid.

Note: This ignores __riscv_misaligned_slow which is also defined by
spec.

[pr]: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/40
2023-10-26 15:10:57 +08:00
Brad Smith
c2f02e3bd6 Clang: Define macro _MIPS_SPFPSET
GCC defines this macro for how many single-precision floating point registers
can be used.

If the -mno-odd-spreg option is given, it will be 16; if either -mno-odd-spreg
nor -modd-spreg are given, we set it to 16 for FPXX.

Reviewed By: theraven

Differential Revision: https://reviews.llvm.org/D157896
2023-10-21 07:08:54 -04:00
Brandon Wu
d1985e3d1f [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
SiFive Int8 Matrix Multiplication Extensions Specification

https://sifive.cdn.prismic.io/sifive/c4f0e51d-4dd3-402a-98bc-1ffad6011259_int8-matmul-spec.pdf
2023-10-20 11:16:20 +08:00
Freddy Ye
278e533ee9 [X86] Support -march=pantherlake,clearwaterforest (#69277) 2023-10-19 15:11:15 +08:00
Phoebe Wang
cfbf0a500f [X86][RFC] Support AVX10 options (#67278)
AVX10 Architecture Specification:
https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC:
https://discourse.llvm.org/t/rfc-design-for-avx10-options-support/73672
2023-10-19 07:52:50 +08:00
Freddy Ye
819ac45d1c [X86] Add USER_MSR instructions. (#68944)
For more details about this instruction, please refer to the latest ISE
document:
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
2023-10-16 10:12:53 +08:00
Sergei Barannikov
79f87be688 [clang] Fix several issues in the generated AttrHasAttributeImpl.inc
1. The generated file contained a lot of duplicate switch cases, e.g.:
```
switch (Syntax) {
case AttributeCommonInfo::Syntax::AS_GNU:
  return llvm::StringSwitch<int>(Name)
...
    .Case("error", 1)
    .Case("warning", 1)
    .Case("error", 1)
    .Case("warning", 1)
```

2. Some attributes were listed in wrong places, e.g.:
```
case AttributeCommonInfo::Syntax::AS_CXX11: {
if (ScopeName == "") {
  return llvm::StringSwitch<int>(Name)
...
    .Case("warn_unused_result", LangOpts.CPlusPlus11 ? 201907 : 0)
```

`warn_unused_result` is a non-standard attribute and should not be
available as [[warn_unused_result]].

3. Some attributes had the wrong version, e.g.:
```
case AttributeCommonInfo::Syntax::AS_CXX11: {
} else if (ScopeName == "gnu") {
  return llvm::StringSwitch<int>(Name)
...
    .Case("fallthrough", LangOpts.CPlusPlus11 ? 201603 : 0)
```

[[gnu::fallthrough]] is a non-standard spelling and should not have the
standard version. Instead, __has_cpp_attribute should return 1 for it.

There is another issue with attributes that share spellings, e.g.:
```
    .Case("interrupt", true && (T.getArch() == llvm::Triple::arm || ...) ? 1 : 0)
    .Case("interrupt", true && (T.getArch() == llvm::Triple::avr) ? 1 : 0)
...
    .Case("interrupt", true && (T.getArch() == llvm::Triple::riscv32 || ...) ? 1 : 0)
```
As can be seen, __has_attribute(interrupt) would only return true for
ARM targets. This patch does not address this issue.

Differential Revision: https://reviews.llvm.org/D159393
2023-10-10 09:03:55 +03:00
XinWang10
057ec767ad [X86][NFC]Update test cases after D159250 (#68517) 2023-10-10 09:32:32 +08:00
Paul Robinson
71d83bb426 Add -fkeep-system-includes modifier for -E
This option will cause -E to preserve the #include directives
for system headers, rather than expanding them into the output.
This can greatly reduce the volume of preprocessed source text
in a test case, making test case reduction simpler.

Note that -fkeep-system-includes is not always appropriate. For
example, if the problem you want to reproduce is induced by a
system header file, it's better to expand those headers fully.
If your source defines symbols that influence the content of a
system header (e.g., _POSIX_SOURCE) then -E will eliminate the
definition, potentially changing the meaning of the preprocessed
source. If you use -isystem to point to non-system headers, for
example to suppress warnings in third-party software, those will
not be expanded and might make the preprocessed source less useful
as a test case.
2023-10-06 12:55:48 -07:00
Pranav Kant
7d21086d0c Revert "[clang] Predefined macros for float128 support (#67196)"
This reverts commit 457f582ffe.
2023-10-04 18:19:24 +00:00
Alex Bradbury
eae1e28cc2 [RISCV] Mark the Zfa extension as non-experimental (#68113)
Following the version bump in #67964 and the bug fix in #68026 I believe
we're ready to mark Zfa as non-experimental. I'll note the GCC torture
suite passes now with Zfa enabled (though it's more of a litmus test
than anything else).
2023-10-03 18:16:13 +01:00
Alex Bradbury
18c3c46858 [RISCV] Update Zfa extension version to 1.0 (#67964)
The Zfa specification was recently ratified
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>. This
commit bumps the version to 1.0, but leaves it as an experimental
extension (to be done in a follow-on patch), so reviews can focus on
confirming there haven't been spec changes we have missed (which as
noted below, is more difficult than usual).

Because the development of the Zfa spec overlapped with the transition
of riscv-isa-manual from LaTeX to AsciiDoc, it's more difficult than
usual to confirm version changes. The linked PDF in RISCVUsage is for
some reason a 404. Key commit histories to review are:
* Changes to zfa.adoc on the main branch
<https://github.com/riscv/riscv-isa-manual/commits/main/src/zfa.adoc>
* Changes to zfa.tex on the now defunct latex branch
<https://github.com/riscv/riscv-isa-manual/commits/latex/src/zfa.tex>

From reviewing these, I believe there have been no changes to the spec
since version 0.1/0.2 (sadly the AsciiDoc and LaTeX versions of the spec
are inconsistent about version numbering).
2023-10-03 17:54:29 +01:00
Alex Voicu
c0f8748d44 [HIP][Clang][Preprocessor] Add Preprocessor support for hipstdpar
This patch adds the Driver changes needed for enabling HIP parallel algorithm offload on AMDGPU targets. This change merely adds two macros to inform user space if we are compiling in `hipstdpar` mode and, respectively, if the optional allocation interposition mode has been requested, as well as associated minimal tests. The macros can be used by the runtime implementation of offload to drive conditional compilation, and are only defined if the HIP language has been enabled.

Reviewed by: yaxunl

Differential Revision: https://reviews.llvm.org/D155826
2023-10-03 13:18:31 +01:00
Pranav Kant
457f582ffe [clang] Predefined macros for float128 support (#67196)
Expose some predefined macros for Float128 support.
2023-10-02 14:14:52 -07:00
Amy Huang
0faee97a92 Recommit "Implement [[msvc::no_unique_address]] (#65675)" (#67199)
This implements the [[msvc::no_unique_address]] attribute.

There is not ABI compatibility in this patch because the attribute is
relatively new and there's still some uncertainty in the MSVC version.

The recommit changes the attribute definitions so that instead of making
two separate attributes for no_unique_address
and msvc::no_unique_address, it modifies the attributes tablegen emitter
to allow spellings to be target-specific.

This reverts commit 71f9e7695b.
2023-09-28 14:29:32 -07:00
Brad Smith
c1300efc78 [Driver] Remove FreeBSD/riscv32 support (#67277)
FreeBSD does not support riscv32 and has no intention of doing so.
2023-09-25 09:43:10 -04:00
Amy Huang
71f9e7695b Revert "Implement [[msvc::no_unique_address]] (#65675)" (#67198)
This reverts commit 4a55d42696.

Reverting because this breaks sphinx documentation, and even with it
fixed the format of the attribute makes the no_unique_address
documentation show up twice.
2023-09-22 14:39:00 -07:00
Amy Huang
4a55d42696 Implement [[msvc::no_unique_address]] (#65675)
This implements the [[msvc::no_unique_address]] attribute.

There is not ABI compatibility in this patch because the attribute is
relatively new and there's still some uncertainty in the MSVC version.

Bug: https://github.com/llvm/llvm-project/issues/49358

Also see https://reviews.llvm.org/D157762.
2023-09-22 13:28:38 -07:00
Yeting Kuo
9ea083f2d4 [Clang][test] Replace legacy -target with --target=. (#66572) 2023-09-18 15:35:57 +08:00
Jianjian Guan
c31dda4e6e [RISCV] Update Zicntr and Zihpm to version 2p0 (#66323) 2023-09-14 15:43:50 +08:00
Billy Laws
97fe519dd2 [Clang][AArch64] Define x86_64 macros for ARM64EC targets (#65420)
The ARM64EC ABI requires that struct layouts match between regular
x86_64 code and ARM64EC code. Ensure this is always the case by defining
the same set of macros as are set when targeting x86_64 but with the
addition of `__arm64ec__/_M_ARM64EC` macros that can be used for any
ARM64EC specific code.

More details can be found here:
https://techcommunity.microsoft.com/t5/windows-os-platform-blog/getting-to-know-arm64ec-defines-and-intrinsic-functions/ba-p/2957235
2023-09-10 23:06:08 +03:00
Jan Svoboda
5523fefb01 [clang][lex] Use preferred path separator in includer-relative lookup
There is a long-standing FIXME in `HeaderSearch.cpp` to use the path separator preferred by the platform instead of forward slash. There was an attempt to fix that (1cf6c28a) which got reverted (cf385dc8). I couldn't find an explanation, but my guess is that some tests assuming forward slash started failing.

This commit fixes tests with that assumption.

This is intended to be NFC, but there are two exceptions to that:
* Some diagnostic messages might now contain backslash instead of forward slash.
* Arguments to the "-remap-file" option that use forward slash might stop kicking in. Separators between potential includer path and header name need to be replaced by backslash in that case.
2023-09-08 16:38:08 -07:00
Phoebe Wang
24194090e1 [X86][RFC] Add new option -m[no-]evex512 to disable ZMM and 64-bit mask instructions for AVX512 features
This is an alternative of D157485 and a pre-feature to support AVX10.

AVX10 Architecture Specification: https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-feature-support/72661

Based on the feedbacks from LLVM and GCC community, we have agreed to
start from supporting `-m[no-]evex512` on existing AVX512 features.
The option `-mno-evex512` can be used with `-mavx512xxx` to build
binaries that can run on both legacy AVX512 targets and AVX10-256.

There're still arguments about what's the expected behavior when this
option as well as `-mavx512xxx` used together with `-mavx10.1-256`. We
decided to defer the support of `-mavx10.1` after we made consensus.
Or furthermore, we start from supporting AVX10.2 and not providing any
AVX10.1 options.

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D159250
2023-09-08 22:47:22 +08:00
Phoebe Wang
0856efbf88 Revert "[X86][RFC] Add new option -m[no-]evex512 to disable ZMM and 64-bit mask instructions for AVX512 features"
This reverts commit 7dd48cc24d.

Causing buildbot failure.
2023-09-07 21:59:01 +08:00
Phoebe Wang
7dd48cc24d [X86][RFC] Add new option -m[no-]evex512 to disable ZMM and 64-bit mask instructions for AVX512 features
This is an alternative of D157485 and a pre-feature to support AVX10.

AVX10 Architecture Specification: https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-feature-support/72661

Based on the feedbacks from LLVM and GCC community, we have agreed to
start from supporting `-m[no-]evex512` on existing AVX512 features.
The option `-mno-evex512` can be used with `-mavx512xxx` to build
binaries that can run on both legacy AVX512 targets and AVX10-256.

There're still arguments about what's the expected behavior when this
option as well as `-mavx512xxx` used together with `-mavx10.1-256`. We
decided to defer the support of `-mavx10.1` after we made consensus.
Or furthermore, we start from supporting AVX10.2 and not providing any
AVX10.1 options.

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D159250
2023-09-07 21:38:35 +08:00
Brad Smith
5165593a97 Delete CloudABI support
After this D108637 and with FreeBSD -current and now 14 dropping support for
CloudABI I think it is time to consider deleting the CloudABI support.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D158920
2023-08-29 22:57:30 -04:00
Aaron Ballman
0f1c1be196 [clang] Remove rdar links; NFC
We have a new policy in place making links to private resources
something we try to avoid in source and test files. Normally, we'd
organically switch to the new policy rather than make a sweeping change
across a project. However, Clang is in a somewhat special circumstance
currently: recently, I've had several new contributors run into rdar
links around test code which their patch was changing the behavior of.
This turns out to be a surprisingly bad experience, especially for
newer folks, for a handful of reasons: not understanding what the link
is and feeling intimidated by it, wondering whether their changes are
actually breaking something important to a downstream in some way,
having to hunt down strangers not involved with the patch to impose on
them for help, accidental pressure from asking for potentially private
IP to be made public, etc. Because folks run into these links entirely
by chance (through fixing bugs or working on new features), there's not
really a set of problematic links to focus on -- all of the links have
basically the same potential for causing these problems. As a result,
this is an omnibus patch to remove all such links.

This was not a mechanical change; it was done by manually searching for
rdar, radar, radr, and other variants to find all the various
problematic links. From there, I tried to retain or reword the
surrounding comments so that we would lose as little context as
possible. However, because most links were just a plain link with no
supporting context, the majority of the changes are simple removals.

Differential Review: https://reviews.llvm.org/D158071
2023-08-28 12:13:42 -04:00
Brad Smith
2a105105a6 Delete Ananas support
After looking at this further I think the Ananas support should be removed.

They stopped using Clang. There have never been any releases either; as in
source only, and the backend is not maintained.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D158946
2023-08-27 18:43:23 -04:00
Fangrui Song
8cfe9d8f2a [Driver] Remove remnant myriad pieces after Myriad.cpp removal
after D104279 and D158706.
2023-08-25 13:29:10 -07:00