Commit Graph

3703 Commits

Author SHA1 Message Date
Alex Richardson
9114ac67a9 Overload all llvm.annotation intrinsics for globals argument
The global constant arguments could be in a different address space
than the first argument, so we have to add another overloaded argument.
This patch was originally made for CHERI LLVM (where globals can be in
address space 200), but it also appears to be useful for in-tree targets
as can be seen from the test diffs.

Differential Revision: https://reviews.llvm.org/D138722
2022-12-07 18:29:18 +00:00
Nikita Popov
4d97a914d7 [SCEV] Use umin_seq for symbolic max BE count
We were using umin_seq when computing the exact BE count, but not
when computing the symbolic max BE count.
2022-12-07 15:32:49 +01:00
Nikita Popov
dcfe2e7a13 [SCEV] Add another symbolic BE count test (NFC) 2022-12-07 15:25:58 +01:00
Max Kazantsev
af7a8866ff [Test] Add a test where we expect to see symbolic max as umin_seq 2022-12-07 19:28:28 +07:00
Max Kazantsev
07de5d18c9 [SCEV] Remember blocks for which we know symbolic exit count but not exact
The old code didn't bother to memoize blocks for which exact exit count is not
known. As result, in situation when exact isn't known but symbolic is known, this
info was lost. This patch fixes the situation: now we memoize when symbolic is
known (exact always implies symbolic, so this is a strict superset of what was before).

Differential Revision: https://reviews.llvm.org/D139515
Reviewed By: nikic
2022-12-07 17:51:30 +07:00
Yeting Kuo
0f8c761c48 [VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support."
This reverts commit 7883e5b061.

The original commit was reverted that it didn't update test files after D136263
landed. The recommit fixed those.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139509
2022-12-07 15:58:12 +08:00
Kazu Hirata
7883e5b061 Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support."
This reverts commit 70de0e0140.

I'm seeing:

Failed Tests (2):
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fshr-fshl-vp.ll

Also reported at:

https://lab.llvm.org/buildbot/#/builders/123/builds/14531
2022-12-06 22:27:43 -08:00
Yeting Kuo
8c8a6e1488 [RISCV] Add basic cost model for vp float rounding instructions.
Reviewed By: craig.topper, reames

Differential Revision: https://reviews.llvm.org/D137766
2022-12-07 14:15:13 +08:00
Yeting Kuo
70de0e0140 [VP][RISCV] Add vp.fshl/fshr and RISC-V support.
The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D138379
2022-12-07 12:16:36 +08:00
liqinweng
cfd73186db [RISCV][CostModel] Add a test for reverse shuffles cost on RISCV, NFC
Reviewed By: benshi001

Differential Revision: https://reviews.llvm.org/D134519
2022-12-07 10:16:20 +08:00
Nikita Popov
fa4b518f1d [BasicAA] Guard against empty successors list (PR59360)
Succs can be empty here if a phi predecessor is unreachable.

Fixes https://github.com/llvm/llvm-project/issues/59360
2022-12-06 16:59:00 +01:00
jacquesguan
d11cc69143 [RISCV][NFC] Add test coverage for insertelement/extractelement of widen vector type.
Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D135534
2022-12-06 15:16:59 +08:00
Matt Arsenault
0a67e771f6 CallGraph: Fix IgnoreAssumeLikeCalls option to Function::hasAddressTaken
This was added in 29e2d9461a and likely never worked in a useful
way.

The test added for it fails when converted to opaque pointers, since
the lifetime intrinsic now directly uses the address. The code was
only trying to handle a user indirectly through a bitcast
instruction. That would never have been useful; a bitcast of a global
value would be folded to a ConstantExpr cast.

I also don't understand why it was special casing use_empty on the
cast. Relax the check to be either BitCastOperator or
AddrSpaceCastOperator. In practice, BitCastOperator won't appear
today.

I believe the change in parallel_deletion_cg_update is a correct
improvement but I didn't fully follow it. .omp_outlined..0 is used in
a constant expression cast to a call which ends up getting deleted.
2022-12-05 21:41:59 -05:00
Nikita Popov
4de3184f07 [LAA] Use cross-iteration alias analysis
LAA analyzes cross-iteration memory dependencies, as such AA should
not make assumptions about equality of values inside the loop, as
they may come from different iterations.

Fix this by exposing the MayBeCrossIteration AA flag and enabling
it for LAA.

Differential Revision: https://reviews.llvm.org/D137958
2022-12-05 09:27:13 +01:00
Matt Arsenault
7cf5581712 Analysis: Update some tests for opaque pointers
StackSafetyAnalysis/lifetime.ll had one bitcast removed that may have
mattered. The concluded lifetime is longer based on the underlying
alloca, instead of the bitcasted pointer so left that as a pointless
cast.

local.ll memintrin.ll needed some manual fixes
2022-12-02 18:47:43 -05:00
Matt Arsenault
81c163e3e1 StackSafetyAnalysis: Don't use anonymous values in test 2022-12-02 18:47:43 -05:00
Matt Arsenault
a74c5707be Fix some test files with executable permissions 2022-12-02 17:12:03 -05:00
Bjorn Pettersson
a11faeed44 [test] Switch to use -passes syntax in various test cases 2022-12-01 21:25:59 +01:00
Philip Reames
73eacf94e0 [RISCV] Incorporate LMUL into costs for arithmetic and shuffles
This reuses the routine implemented in 0e6f0b7 to implement several existing TODOs. Many of the operations scale linearly with LMUL; this change represents that in the cost model.

Differential Revision: https://reviews.llvm.org/D139039
2022-12-01 10:46:27 -08:00
Roman Lebedev
7850ab2112 [NFC] Port an assortment of tests that invoke SROA to new pass manager 2022-12-01 21:17:18 +03:00
Philip Reames
7d82c99403 [RISCV][TTI] Account for constant materialization cost when costing arithmetic operations
At the IR level, we generally assume that constants are free to materialize. However, for RISCV due to some quirks of the ISA, materializing arbitrary constants can be rather expensive. We frequently fallback to constant pool loads.

We've been slowly moving in the direction of modeling the cost of the remat as part of the instruction cost. This has the effect of disincentivizing vectorization - mostly SLP - when we'd have to materialize an expensive constant.

We need better modeling of which constants are expensive and not, but the moment let's be consistent with how we model arithmetic and memory instructions. The difference between the two is that arithmetic can sometimes fold a splat operation which stores can not.

Differential Revision: https://reviews.llvm.org/D138941
2022-11-30 07:20:51 -08:00
Paul Robinson
3558da3d89 [Sanitizers] Fix test that never ran anywhere
Incorrect REQUIRES clause. Also fixed the incorrect 'opt' line
and removed a redundant -mtriple option.
2022-11-30 07:20:27 -08:00
David Green
f2a92db29e [AArch64] Don't treat SVE scalable extends as free widening instructions
The logic in isWideningInstruction handles instructions like uaddw and
smull, where 'add(x, zext(y))' or 'mul(sext(x), sext(y))' can be
converted to single instructions, making the extends free. This doesn't
apply the same to SVE instructions though.
https://godbolt.org/z/695d3nhGd

(There are instructions like SMULLT/B, but they require top/bottom lane
interleaving. That is similar to MVE instructions, which required a
special pass to perform the lane interleaving).

This patch just bails out of the call to isWideningInstruction if the
vector is scalable, getting a more accurate cost.

Differential Revision: https://reviews.llvm.org/D138591
2022-11-30 13:09:48 +00:00
ShihPo Hung
0e6f0b7cc3 [RISCV] Add cost model for fixed broadcast shuffle
This patch adds basic broadcast shuffle costs in order to enable SLP vectorization.
And adds `getLMULCost` to consider reciprocal throughput for different LMUL.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D137276
2022-11-30 04:58:52 -08:00
Philip Reames
3c9d247112 [RISCV] Add test coverage for vector constant materialization costs on arithmetic instructions 2022-11-29 12:00:58 -08:00
Philip Reames
e726c5879a [RISCV] Add cost model coverage for vector arithmetic 2022-11-29 11:50:52 -08:00
Mateja Marjanovic
595a08847a [AMDGPU] Add support for new LLVM vector types
Add VReg, AReg and SReg on AMDGPU for bit widths: 288, 320, 352 and 384.

Differential Revision: https://reviews.llvm.org/D138205
2022-11-29 17:02:04 +01:00
David Green
57dc4a8cab [AArch64] Extend testing for widening conditions under SVE. NFC 2022-11-29 15:53:39 +00:00
Slava Zakharin
5bd8175dd7 [AA] A global cannot escape through nocapture/nocallback call.
When an internal global is passed to a 'nocallback' call as
a 'nocapture' pointer, it cannot escape through this call and
be indirectly referenced in this module.
So it must not alias with any pointer in the module.

This may provide some remedy for Fortran module-private array descriptors
that are usually passed by address to some runtime functions
(e.g. to allocation/deallocation functions). In general, a good aliasing
information derived from Fortran language rules would solve the same issue,
but I think this change may be beneficial as-is (given that nocapture,
nocallback attributes are properly set).

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D138336
2022-11-28 12:50:31 -08:00
Philip Reames
db07d79ab0 [RISCV] Add cost model for integer and float vector arithmetic instructions.
This patch implements getArithmeticInstrCost for RISCV, supports cost
model for integer and float vector arithmetic instructions.

Differential Revision: https://reviews.llvm.org/D133552 (Original patch by jacquesguan.  Subset by me with todos added.)
2022-11-28 09:04:38 -08:00
Matt Arsenault
8c58a9ace0 DivergenceAnalysis: Convert tests to opaque pointers 2022-11-28 08:42:38 -05:00
Zain Jaffal
6e4cea55f0 [AArch64] Fix cost model for udiv instruction when one of the operands is a uniform constant
Currently the model over estimates the cost of a udiv instruction with one constant. The correct cost for a udiv instruction is
insert_cost * extract_cost * num_elements

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D135991
2022-11-28 10:38:17 +02:00
Max Kazantsev
06c4103d41 [Test] Add couple more tests where we can compute symbolic max exit count (fixed) 2022-11-25 14:40:32 +07:00
Max Kazantsev
eb95ab5745 Revert "[Test] Add couple more tests where we can compute symbolic max exit count"
This reverts commit 7e3373c9e1.

Some changes that were not supposed to be commited came with it.
2022-11-25 13:37:24 +07:00
Max Kazantsev
7e3373c9e1 [Test] Add couple more tests where we can compute symbolic max exit count 2022-11-25 13:35:16 +07:00
Max Kazantsev
b9c1d73725 [Test] Add test showing that SCEV fails to evaluate symbolic max for 'and' conditions 2022-11-25 11:45:10 +07:00
Max Kazantsev
4496d553bd [SCEV] Fix misplaced \n in printout of max symbolic exit counts 2022-11-25 11:41:36 +07:00
Florian Hahn
ae852750b3 [MemoryLocation] Support memcpy_chk in getForArgument.
Similar to 9f9e8ba114, add support for memcyp_chk to
MemoryLocation::getForArgument.

The size argument for memcpy_chk is an upper bound for the size of the
pointer argument. memcpy_chk may read/write less than the specified length,
if it exceeds the specified max size and aborts.

Reviewed By: xbolva00, jdoerfert

Differential Revision: https://reviews.llvm.org/D138613
2022-11-24 19:17:48 +00:00
Max Kazantsev
e5fa7eb120 [SCEV] Add printout of symbolic max backedge-taken and block exit count
We do compute it and use in optimizations, but never print it out. We need
to do it in order to be able to track improvements in its computation.
2022-11-24 19:29:58 +07:00
Max Kazantsev
211d941188 [SCEV] Rename max backedge-taken count -> constant max backedge taken-count in printout
This is a preparatory step for introducing symbolic max backedge-taken count.
2022-11-24 18:43:42 +07:00
Florian Hahn
4b4cbbd7fb [BasicAA] Add tests with __memcpy_chk. 2022-11-23 22:09:53 +00:00
Haohai Wen
1215e86a0e [CostModel][X86] Fix permute latency cost
Avx512 permute latency should be 3 instead of 1.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D138427
2022-11-23 19:17:16 +08:00
Haohai Wen
2dfe76e989 [CostModel][X86] Add CostKinds test coverage for shufflevector instruction
Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D138485
2022-11-23 10:30:48 +08:00
Florian Hahn
5dad4c6788 [SCEV] Iteratively compute ranges for deeply nested expressions.
At the moment, getRangeRef may overflow the stack for very deeply nested
expressions.

This patch introduces a new getRangeRefIter function, which first builds
a worklist of N-ary expressions and phi nodes, followed by their
operands iteratively.

getRangeRef has been extended to also take a Depth argument and it
switches to use getRangeRefIter once the depth reaches a certain
threshold.

This ensures compile-time is not impacted in general. Note that
the iterative algorithm may lead to a slightly different evaluation
order, which could result in slightly worse ranges for cyclic phis.

https://llvm-compile-time-tracker.com/compare.php?from=23c3eb7cdf3478c9db86f6cb5115821a8f0f5f40&to=e0e09fa338e77e53242bfc846e1484350ad79773&stat=instructions

Fixes #49579.

Reviewed By: mkazantsev

Differential Revision: https://reviews.llvm.org/D130728
2022-11-21 21:56:14 +00:00
Florian Hahn
535c2da58d [SCEV] Add range test with phi and division.
Extra test coverage for D130728.
2022-11-21 19:58:43 +00:00
Yeting Kuo
ed9638c44b [VP][RISCV] Add vp.nearbyint and RISC-V support.
nearbyint has the property to execute without exception.
For not modifying fflags, the patch added new machine opcode
PseudoVFROUND_NOEXCEPT_V that expands vfcvt.x.f.v and vfcvt.f.x.v between a pair
of frflags and fsflags.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137685
2022-11-16 14:05:35 +08:00
Yeting Kuo
5c3ca10b09 [VP][RISCV] Add vp.bswap and RISC-V support.
The patch also added function expandVPBSWAP to expand ISD::VP_BSWAP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137928
2022-11-16 11:36:38 +08:00
Roman Lebedev
11abb7fedb [NFC][X86][Costmodel] Drop reduntant interleaved cost test coverage
These are already covered by the more general tests i've added.
2022-11-15 21:30:06 +03:00
Roman Lebedev
8e37b53360 [X86] Rewrite getScalarizationOverhead()
All of our insert/extract ops work on 128-bit lanes.

For `Insert`, we need to extract affected 128-bit lane,
unless it's being fully overwritten (FIXME: do we need to be
careful about legalization-induced padding that we obviously don't demand?),
perform insertions, and then insert the 128-bit lane back.

But hold on. If we are operating on an 256-bit legal vector,
and thus have two 128-bit subvectors, and are fully overwriting them both,
we don't actually need to insert *both* subvectors,
only the second one, into the implicitly-widened first one.

Also, `Insert` wasn't actually querying the costs,
but just assuming them to be `1`.

`getShuffleCost(TTI::SK_ExtractSubvector)` notes:
```
  // Note that in general, the insertion starting at the beginning of a vector
  // isn't free, because we need to preserve the rest of the wide vector.
```
... so as far as i can tell, we didn't account for that.

I was hoping this would allow vectorization at a higher VF at one case i looked at,
but the subvector insertion cost is still dis-advising that.

The change for `Extract` is NFC, and is for consistency only,
i wanted to get rid of of that weird explicit discounting of insertion of 0'th element,
since the general code should already deal with that.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D137913
2022-11-15 21:07:12 +03:00
Nikita Popov
458ae539df [AST] Remove legacy AliasSetPrinter pass
A NewPM version of this pass exists, drop the legacy version of
this testing-only pass.
2022-11-14 15:50:38 +01:00