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472 Commits

Author SHA1 Message Date
Jim Grosbach
ed428bc1ce ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

llvm-svn: 152157
 2012-03-06 23:10:38 +00:00
Jim Grosbach
13a292cc74 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
 2012-03-06 22:01:44 +00:00
Jim Grosbach
e5307f9019 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

llvm-svn: 152063
 2012-03-05 21:43:40 +00:00
Jim Grosbach
c71bf4739a ARM Remove a bit of dead code. 
llvm-svn: 152061
 2012-03-05 21:09:58 +00:00
Jim Grosbach
c988e0c521 ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045
 2012-03-05 19:33:30 +00:00
Craig Topper
e55c556a24 Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
Jim Grosbach
a2147ce313 Tidy up. One more return type mismatch fix. 
llvm-svn: 149452
 2012-01-31 23:51:09 +00:00
Jim Grosbach
5e5eabb5ab Keep source information, if available, around for ARM Fixups. 
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.

Before:
LLVM ERROR: unknown ARM fixup kind!

After:
x.s:6:5: error: unsupported relocation on symbol
    beq bar
    ^

rdar://9800182

llvm-svn: 149093
 2012-01-26 23:20:15 +00:00
Jim Grosbach
c8f2b7877b Tidy up. Fix mismatched return types for error handling. 
llvm-svn: 149062
 2012-01-26 15:56:45 +00:00
Jim Grosbach
82f76d1275 ARM assemly parsing and validation of IT instruction. 
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
 2012-01-25 19:52:01 +00:00
Jim Grosbach
086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach
b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Jim Grosbach
8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Jim Grosbach
14952a0e32 NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach
da70eac268 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach
ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach
1e946a4f91 Tidy up. Remove some vertical space for readability. 
llvm-svn: 148761
 2012-01-24 00:43:12 +00:00
Jim Grosbach
d3d36d9315 NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach
1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach
ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Jim Grosbach
a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Jim Grosbach
d28ef9ac46 Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Jim Grosbach
78dcaed8ca Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction. 
llvm-svn: 148601
 2012-01-21 00:07:56 +00:00
David Blaikie
46a9f016c5 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Jim Grosbach
a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Jim Grosbach
235c8d2d94 ARM assembly diagnostic caret in better position for FPImm. 
llvm-svn: 148459
 2012-01-19 02:47:30 +00:00
Jim Grosbach
94298a906a Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
 2012-01-18 22:46:46 +00:00
David Blaikie
486df738c3 Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. 
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262
 2012-01-16 23:24:27 +00:00
Matt Beaumont-Gay
b982d8eb65 Fix malformed assert. 
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

llvm-svn: 147459
 2012-01-03 19:03:59 +00:00
Jim Grosbach
ea2319112f ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

llvm-svn: 147189
 2011-12-22 22:19:05 +00:00
Jim Grosbach
c4d8d2f155 Tidy up. Use predicate function a bit more liberally. 
llvm-svn: 147184
 2011-12-22 22:02:35 +00:00
Jim Grosbach
489ed5929e ARM pre-UAL aliases. fcmp[sd]. 
llvm-svn: 147158
 2011-12-22 19:20:45 +00:00
Jim Grosbach
12ccf45bbb ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

llvm-svn: 147153
 2011-12-22 18:04:04 +00:00
Jim Grosbach
21488b8839 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. 
llvm-svn: 147152
 2011-12-22 17:37:00 +00:00
Jim Grosbach
3794d82af5 Tidy up. Trailing whitespace. 
llvm-svn: 147151
 2011-12-22 17:17:10 +00:00
Jim Grosbach
62bffd8827 Nuke invalid comment from copy/paste. 
llvm-svn: 147150
 2011-12-22 17:04:50 +00:00
Jim Grosbach
1152cc0cad ARM asm parser should be more lenient w/ .thumb_func directive. 
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

llvm-svn: 147100
 2011-12-21 22:30:16 +00:00
Jim Grosbach
8c59bbc1ed Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
 2011-12-21 21:04:19 +00:00
Jim Grosbach
b3ef713e44 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
 2011-12-21 20:54:00 +00:00
Jim Grosbach
7de7ab83fa ARM assembly parsing allows constant expressions for lane indices. 
llvm-svn: 147028
 2011-12-21 01:19:23 +00:00
Jim Grosbach
c5af54ec89 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Jim Grosbach
cd22e4a81e ARM .req register name aliases are case insensitive, just like regnames. 
llvm-svn: 147009
 2011-12-20 23:11:00 +00:00
Jim Grosbach
4eda145c7f Move comment to appropriate place. 
llvm-svn: 147000
 2011-12-20 22:26:38 +00:00
Jim Grosbach
2c59052984 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Jim Grosbach
75e2ab5db2 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Jason W Kim
135d244b56 First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

llvm-svn: 146977
 2011-12-20 17:38:12 +00:00
Jim Grosbach
e2ca9e5b5f ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

llvm-svn: 146937
 2011-12-20 00:59:38 +00:00
Jim Grosbach
045b6c71a6 ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

llvm-svn: 146925
 2011-12-19 23:51:07 +00:00
Jim Grosbach
8648c10184 ARM assembly parsing and encoding support for LDRD(label). 
rdar://9932658

llvm-svn: 146921
 2011-12-19 23:06:24 +00:00
Jim Grosbach
e16acacc3a ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
llvm-svn: 146892
 2011-12-19 19:43:50 +00:00