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39f65335d5e4a8d2fc7cc3cd364984e864b5348a
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3522 Commits

Author SHA1 Message Date
Chris Lattner
39f65335d5 remove some dead target hooks, subsumed by isLegalAddressingMode 
llvm-svn: 35840
 2007-04-09 22:27:04 +00:00
Anton Korobeynikov
da964a2852 Use integer log for metric calculation 
llvm-svn: 35834
 2007-04-09 21:57:03 +00:00
Jeff Cohen
0475f3b4e9 Unbreak VC++ build. 
llvm-svn: 35817
 2007-04-09 14:32:59 +00:00
Anton Korobeynikov
506eaf7915 Next stage into switch lowering refactoring 
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.

llvm-svn: 35816
 2007-04-09 12:31:58 +00:00
Reid Spencer
71b79e3d99 For PR1146: 
Adapt handling of parameter attributes to use the new ParamAttrsList class.

llvm-svn: 35814
 2007-04-09 06:17:21 +00:00
Chris Lattner
7b2decfa0a implement CodeGen/X86/inline-asm-x-scalar.ll:test3 
llvm-svn: 35802
 2007-04-09 05:31:20 +00:00
Chris Lattner
18d6718e78 add some assertions 
llvm-svn: 35800
 2007-04-09 05:23:13 +00:00
Chris Lattner
f73d215023 Fix a bug introduced with my previous patch, where it didn't correctly handle 
instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll

llvm-svn: 35789
 2007-04-09 01:19:33 +00:00
Chris Lattner
0df5357436 Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308: 
some instructions can have multiple frame indices in them.  If this happens,
rewrite all of them.

llvm-svn: 35785
 2007-04-09 00:46:10 +00:00
Chris Lattner
b49917da92 Fix PR1316 
llvm-svn: 35783
 2007-04-09 00:33:58 +00:00
Chris Lattner
e55ecfb870 Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314 
llvm-svn: 35779
 2007-04-08 22:23:26 +00:00
Chris Lattner
1c741e95d3 minor comment fix 
llvm-svn: 35696
 2007-04-06 17:47:14 +00:00
Reid Spencer
85460acfbf Change the bit_part_select (non)implementation from "return 0" to abort. 
llvm-svn: 35679
 2007-04-05 01:20:18 +00:00
Reid Spencer
cce90f55ed Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic. 
llvm-svn: 35678
 2007-04-04 23:48:25 +00:00
Anton Korobeynikov
915e61736b Properly emit range comparisons for switch cases, where neighbour cases 
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase

llvm-svn: 35672
 2007-04-04 21:14:49 +00:00
Evan Cheng
8be98c1572 Re-materialize all loads from fixed stack slots. 
llvm-svn: 35660
 2007-04-04 07:40:01 +00:00
Evan Cheng
2bf2aadd9a Trivially re-materializable instructions have spill weights that are half of what it would be otherwise. 
llvm-svn: 35658
 2007-04-04 07:04:55 +00:00
Evan Cheng
06a7041ff9 Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found. 
llvm-svn: 35618
 2007-04-03 06:43:29 +00:00
Scott Michel
16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
 2007-04-02 21:36:32 +00:00
Evan Cheng
476fb6a5c9 Ugh. Copy coalescer does not update register numbers. 
llvm-svn: 35600
 2007-04-02 18:49:18 +00:00
Reid Spencer
fad9bd6b92 For PR1297: 
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).

llvm-svn: 35567
 2007-04-02 01:01:49 +00:00
Reid Spencer
6bba6c8143 For PR1297: 
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.

llvm-svn: 35547
 2007-04-01 07:35:23 +00:00
Reid Spencer
3a0843e734 For PR1297: 
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546
 2007-04-01 07:34:11 +00:00
Reid Spencer
a090ffb2ab For PR1297: 
Change getOperationName to return std::string instead of const char*

llvm-svn: 35545
 2007-04-01 07:32:19 +00:00
Chris Lattner
f6a6d3c8b0 move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare". 
llvm-svn: 35529
 2007-03-31 04:18:03 +00:00
Chris Lattner
f2d71d49e2 switch TL::getValueType to use MVT::getValueType. 
llvm-svn: 35527
 2007-03-31 04:05:24 +00:00
Chris Lattner
bafc837c83 Add a -print-lsr-output option to LLC, to print the output of the LSR pass. 
llvm-svn: 35522
 2007-03-31 00:24:43 +00:00
Chris Lattner
ac3f81508c add one addressing mode description hook to rule them all. 
llvm-svn: 35520
 2007-03-30 23:14:50 +00:00
Dale Johannesen
4bbd2eefba Fix incorrect combination of different loads. Reenable zext-over-truncate 
combination.

llvm-svn: 35517
 2007-03-30 21:38:07 +00:00
Evan Cheng
9a2a7b174a Don't add the same MI to register reuse "last def/use" twice if it reads the 
register more than once.

llvm-svn: 35513
 2007-03-30 20:21:35 +00:00
Evan Cheng
48dd5e7d44 Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep length 
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.

llvm-svn: 35512
 2007-03-30 20:18:35 +00:00
Evan Cheng
ccee35fd0d Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
 2007-03-29 07:56:46 +00:00
Evan Cheng
86de3a009d New entries. 
llvm-svn: 35445
 2007-03-29 02:48:56 +00:00
Evan Cheng
d771485d89 Notes on re-materialization. 
llvm-svn: 35420
 2007-03-28 08:30:04 +00:00
Evan Cheng
603e49c6da Move rematerialization out of beta. 
llvm-svn: 35419
 2007-03-28 08:26:40 +00:00
Evan Cheng
4388043b25 Scale 1 is always ok. 
llvm-svn: 35407
 2007-03-28 01:55:52 +00:00
Evan Cheng
c2cba18f2b Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Evan Cheng
07c42d43a2 GEP index sinking fixes: 
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).

llvm-svn: 35403
 2007-03-28 01:49:39 +00:00
Evan Cheng
b41697c006 Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should 
not violate that.

llvm-svn: 35396
 2007-03-28 01:30:37 +00:00
Anton Korobeynikov
37a0bfe128 Remove dead code 
llvm-svn: 35380
 2007-03-27 12:05:48 +00:00
Anton Korobeynikov
3a9d68181a Split big monster into small helpers. No functionality change. 
llvm-svn: 35379
 2007-03-27 11:29:11 +00:00
Evan Cheng
c42406b5ad SDISel does not preserve all, it changes CFG and other info. 
llvm-svn: 35376
 2007-03-27 00:53:36 +00:00
Evan Cheng
fdbdf43632 Don't call getOperandConstraint() if operand index is greater than 
TID->numOperands.

llvm-svn: 35375
 2007-03-27 00:48:28 +00:00
Evan Cheng
4a09b1b5be Fix for PR1266. Don't mark a two address operand IsKill. 
llvm-svn: 35365
 2007-03-26 22:40:42 +00:00
Evan Cheng
ec3ac316e2 Change findRegisterUseOperand() to return operand index instead. 
llvm-svn: 35363
 2007-03-26 22:37:45 +00:00
Dale Johannesen
fd18a0cdf4 Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to 
hopefully forestall similar errors.

llvm-svn: 35362
 2007-03-26 22:23:54 +00:00
Evan Cheng
8275f0e0af SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
llvm-svn: 35350
 2007-03-26 07:12:51 +00:00
Anton Korobeynikov
7037826c86 First step of switch lowering refactoring: perform worklist-driven 
strategy, emit JT's where possible.

llvm-svn: 35338
 2007-03-25 15:07:15 +00:00
Chris Lattner
77f0479833 Implement support for vector operands to inline asm, implementing 
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332
 2007-03-25 05:00:54 +00:00
Chris Lattner
3d7efa2586 implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll 
llvm-svn: 35327
 2007-03-25 04:35:41 +00:00