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327 Commits

Author SHA1 Message Date
Jim Grosbach
e7fbce7acb ARM assembly parsing and encoding for VMOV immediate. 
llvm-svn: 141046
 2011-10-03 23:38:36 +00:00
Jim Grosbach
46b6646059 ARM parsing/encoding for VCMP/VCMPE. 
llvm-svn: 141038
 2011-10-03 22:30:24 +00:00
Jim Grosbach
4ab23b5273 ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
James Molloy
21efa7d6e1 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00
Owen Anderson
f01e2de5e6 ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
llvm-svn: 140560
 2011-09-26 21:06:22 +00:00
Owen Anderson
4916840eb8 Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
llvm-svn: 140426
 2011-09-23 22:25:02 +00:00
Jim Grosbach
b35198021a Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
llvm-svn: 140125
 2011-09-20 00:46:54 +00:00
Jim Grosbach
fc5451832a Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
llvm-svn: 140095
 2011-09-19 23:31:02 +00:00
Jim Grosbach
05541f45f3 Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
Jim Grosbach
8221319707 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
llvm-svn: 140047
 2011-09-19 20:29:33 +00:00
Jim Grosbach
40700e0992 ARM asm parsing should handle pre-indexed writeback w/o immediate. 
For example, 'ldrb r9, [sp]!' is odd, but valid.

llvm-svn: 140035
 2011-09-19 18:42:21 +00:00
Jim Grosbach
d0c435c23c Thumb2 assembly parsing and encoding for SUB(immediate). 
llvm-svn: 139966
 2011-09-16 22:58:42 +00:00
Jim Grosbach
9c0b86a76d Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

llvm-svn: 139949
 2011-09-16 21:55:56 +00:00
Jim Grosbach
099c9767c3 Thumb2 assembly parsing and encoding for STMIA. 
llvm-svn: 139938
 2011-09-16 20:50:13 +00:00
Jim Grosbach
d73c6458de Thumb2 assembly parsing and encoding for SMMULL. 
llvm-svn: 139921
 2011-09-16 18:05:48 +00:00
Jim Grosbach
5e6d5cd7da Kill some dead code. 
llvm-svn: 139904
 2011-09-16 16:45:40 +00:00
Jim Grosbach
6c45b75154 Tidy up a bit. 
llvm-svn: 139903
 2011-09-16 16:39:25 +00:00
Jim Grosbach
f9799d2c2d Thumb2 assembly parsing and encoding for SMLAL. 
llvm-svn: 139902
 2011-09-16 16:38:00 +00:00
Owen Anderson
d7791b961c Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
llvm-svn: 139747
 2011-09-14 22:46:14 +00:00
Jim Grosbach
9c8b9932d6 Thumb2 assembly parsing and encoding for MUL. 
llvm-svn: 139735
 2011-09-14 21:00:40 +00:00
Jim Grosbach
0ecd395095 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

llvm-svn: 139721
 2011-09-14 20:03:46 +00:00
Jim Grosbach
18b8b17579 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

llvm-svn: 139714
 2011-09-14 19:12:11 +00:00
Jim Grosbach
3ac26b138b ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573

llvm-svn: 139707
 2011-09-14 18:08:35 +00:00
Jim Grosbach
75461af000 Remove unnecessary scope resolution operator. 
llvm-svn: 139656
 2011-09-13 22:56:44 +00:00
Jim Grosbach
e3a6a82f16 There's only 16 regs legal in a register list. 
llvm-svn: 139637
 2011-09-13 20:35:57 +00:00
Owen Anderson
44ae2da4ec Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
llvm-svn: 139610
 2011-09-13 17:59:19 +00:00
Jim Grosbach
3337e396c8 Tidy up a bit. 
llvm-svn: 139559
 2011-09-12 23:36:42 +00:00
Jim Grosbach
b908b7af31 Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440
 2011-09-10 00:15:36 +00:00
Owen Anderson
29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
llvm-svn: 139415
 2011-09-09 21:48:23 +00:00
Jim Grosbach
62c33955e2 Thumb2 assembly parsing and encoding for MLA and MLS. 
llvm-svn: 139399
 2011-09-09 20:24:45 +00:00
Jim Grosbach
a05627ebaf Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Jim Grosbach
7db8d697cf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
Jim Grosbach
c086f689f8 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270
 2011-09-08 00:39:19 +00:00
Jim Grosbach
2392c53e73 Thumb2 assembly parsing and encoding for LDRBT. 
llvm-svn: 139267
 2011-09-07 23:39:14 +00:00
Jim Grosbach
e0ebc1c396 Thumb2 assembly parsing and encoding for LDR(register). 
llvm-svn: 139264
 2011-09-07 23:10:15 +00:00
Jim Grosbach
5bfa8bab06 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
 2011-09-07 20:58:57 +00:00
Jim Grosbach
a31f223af8 Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242
 2011-09-07 18:05:34 +00:00
Jim Grosbach
39c6e1d66d Better diagnostic location information for mnemonic suffices. 
llvm-svn: 139232
 2011-09-07 16:06:04 +00:00
Jim Grosbach
803898f119 Thumb2 parsing and encoding for CLREX. 
llvm-svn: 139172
 2011-09-06 20:27:04 +00:00
Jim Grosbach
f471ac3c72 ARM .code directive should always go to the streamer. 
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

llvm-svn: 139155
 2011-09-06 18:46:23 +00:00
Jim Grosbach
a0d34d3b5e Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Jim Grosbach
f6d5d60f99 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Owen Anderson
35d240f9e8 t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jim Grosbach
1d3c137839 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Jim Grosbach
99bc84662f Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
llvm-svn: 138898
 2011-08-31 21:17:31 +00:00
Jim Grosbach
cfa9421e16 Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879
 2011-08-31 18:39:39 +00:00
Jim Grosbach
c61fc8f301 tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
llvm-svn: 138873
 2011-08-31 18:29:05 +00:00
Jim Grosbach
6d606fbe14 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Jim Grosbach
ed16ec4248 Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Owen Anderson
967674d26c Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00