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236 Commits

Author SHA1 Message Date
Duncan Sands
f2641e1bc1 Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
 2011-09-06 19:07:46 +00:00
Eli Friedman
7dfa791f4f Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
llvm-svn: 138751
 2011-08-29 18:23:02 +00:00
Akira Hatanaka
419fd4f315 Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not 
needed for Mips32.

llvm-svn: 138132
 2011-08-19 22:59:00 +00:00
Akira Hatanaka
fb4161ae88 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Akira Hatanaka
73d78b7ab1 Make IsShiftedMask a static function rather than defining it in an 
anonymous namespace.

llvm-svn: 137975
 2011-08-18 20:07:42 +00:00
Akira Hatanaka
eea541ce4e Changed definition of EXT and INS per Bruno's comments. 
llvm-svn: 137892
 2011-08-17 22:59:46 +00:00
Akira Hatanaka
b2e7558c40 Add support for half-word unaligned loads and stores. 
llvm-svn: 137848
 2011-08-17 18:49:18 +00:00
Akira Hatanaka
184b63d09c Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. 
llvm-svn: 137831
 2011-08-17 17:45:08 +00:00
Akira Hatanaka
5360f88355 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Akira Hatanaka
2fcc1cfdce Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Eli Friedman
30a49e93e3 New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. 
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
 2011-08-03 21:06:02 +00:00
Eli Friedman
26a484852e Code generation for 'fence' instruction. 
llvm-svn: 136283
 2011-07-27 22:21:52 +00:00
Akira Hatanaka
a4c09bce9b Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Akira Hatanaka
9663dd3f00 Change variable name. 
llvm-svn: 135522
 2011-07-19 20:56:53 +00:00
Akira Hatanaka
f3b29992d5 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Akira Hatanaka
0e01959327 Use descriptive variable names. 
llvm-svn: 135514
 2011-07-19 20:11:17 +00:00
Akira Hatanaka
db2ccdcfd2 Fix comments. 
llvm-svn: 135496
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
e450358a21 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
08636b4633 Separate code that modifies control flow from code that adds instruction to 
basic blocks.

llvm-svn: 135490
 2011-07-19 17:09:53 +00:00
Akira Hatanaka
e4e9a590d2 Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465
 2011-07-19 03:42:13 +00:00
Akira Hatanaka
e97bd81f07 Do not insert instructions in reverse order. 
llvm-svn: 135464
 2011-07-19 03:14:58 +00:00
Akira Hatanaka
338879a7f4 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka
27292638bd Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Akira Hatanaka
8b98515c29 Change destination register operands of SC instructions so that unique 
virtual registers are used. 

llvm-svn: 135403
 2011-07-18 17:44:27 +00:00
Chris Lattner
229907cd11 land David Blaikie's patch to de-constify Type, with a few tweaks. 
llvm-svn: 135375
 2011-07-18 04:54:35 +00:00
Cameron Zwarich
f03fa189ca Add an intrinsic and codegen support for fused multiply-accumulate. The intent 
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
 2011-07-08 21:39:21 +00:00
Akira Hatanaka
9c6028f98e Lower MachineInstr to MC Inst and print to .s files. 
llvm-svn: 134661
 2011-07-07 23:56:50 +00:00
Akira Hatanaka
2e766ed2f8 Reverse order of operands of address operand mem so that the base operand comes 
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
 2011-07-07 18:57:00 +00:00
Eric Christopher
eaf77dc2bd Update comment for getRegForInlineAsmConstraint for Mips. 
llvm-svn: 134087
 2011-06-29 19:33:04 +00:00
Eric Christopher
9519c08a43 Remove getRegClassForInlineAsmConstraint for Mips. 
Part of rdar://9643582

llvm-svn: 134084
 2011-06-29 19:04:31 +00:00
Akira Hatanaka
35792089e7 Change the chain input of nodes that load the address of a function. This change 
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811
 2011-06-24 19:01:25 +00:00
Akira Hatanaka
5b350be79d Coding style fixes. 
llvm-svn: 133496
 2011-06-21 01:02:03 +00:00
Akira Hatanaka
4c406e7457 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Bruno Cardoso Lopes
5444a7b4cd Silence warnings in non assert builds. Patch by David Blaikie 
llvm-svn: 133118
 2011-06-16 00:40:02 +00:00
Eric Christopher
f15601f19a Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Eric Christopher
0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Akira Hatanaka
4e9af454f7 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.

llvm-svn: 132758
 2011-06-08 21:28:09 +00:00
Akira Hatanaka
195a1e2184 Reorganize code in MipsTargetLowering::LowerCall to improve readability. 
llvm-svn: 132756
 2011-06-08 17:39:33 +00:00
Akira Hatanaka
41956cf6e3 Refactor MipsTargetLowering::EmitInstrWithCustomInserter. 
llvm-svn: 132726
 2011-06-07 19:28:39 +00:00
Akira Hatanaka
1550678765 Coding style fixes. 
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724
 2011-06-07 18:58:42 +00:00
Akira Hatanaka
6627752050 Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
llvm-svn: 132444
 2011-06-02 00:24:44 +00:00
Bruno Cardoso Lopes
f771a0f490 Fix uninitialized variables and silence warnings 
llvm-svn: 132355
 2011-05-31 20:25:26 +00:00
Bruno Cardoso Lopes
98fc4c8bbc This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, 
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
 2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
bf3c1251e0 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Akira Hatanaka
b406843fe5 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00
Akira Hatanaka
077964a03c Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if 
a function has any function calls.

llvm-svn: 132140
 2011-05-26 20:30:31 +00:00
Akira Hatanaka
aa560006ed Add support for C++ exception handling. 
llvm-svn: 132131
 2011-05-26 18:59:03 +00:00
Akira Hatanaka
f1412e4d2f Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already 
been defined in MipsInstrFPU.td.

llvm-svn: 132076
 2011-05-25 20:08:05 +00:00
Akira Hatanaka
44eba3ac49 Custom-lower FCOPYSIGN nodes. 
llvm-svn: 132074
 2011-05-25 19:32:07 +00:00
Akira Hatanaka
d72cc55fcc Update MaxCallFrameSize regardless of the relocation model selected. 
llvm-svn: 132070
 2011-05-25 18:08:32 +00:00